[qemu.git] / hw / vt82c686.c

/*
 * VT82C686B south bridge support
 *
 * Copyright (c) 2008 yajin ([email protected])
 * Copyright (c) 2009 chenming ([email protected])
 * Copyright (c) 2010 Huacai Chen ([email protected])
 * This code is licensed under the GNU GPL v2.
 */

#include "hw.h"
#include "pc.h"
#include "vt82c686.h"
#include "i2c.h"
#include "smbus.h"
#include "pci.h"
#include "isa.h"
#include "sysbus.h"
#include "mips.h"
#include "apm.h"
#include "acpi.h"
#include "pm_smbus.h"
#include "sysemu.h"
#include "qemu-timer.h"

typedef uint32_t pci_addr_t;
#include "pci_host.h"
//#define DEBUG_VT82C686B

#ifdef DEBUG_VT82C686B
#define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__)
#else
#define DPRINTF(fmt, ...)
#endif

typedef struct SuperIOConfig
{
    uint8_t config[0xff];
    uint8_t index;
    uint8_t data;
} SuperIOConfig;

typedef struct VT82C686BState {
    PCIDevice dev;
    SuperIOConfig superio_conf;
} VT82C686BState;

static void superio_ioport_writeb(void *opaque, uint32_t addr, uint32_t data)
{
    int can_write;
    SuperIOConfig *superio_conf = opaque;

    DPRINTF("superio_ioport_writeb  address 0x%x  val 0x%x\n", addr, data);
    if (addr == 0x3f0) {
        superio_conf->index = data & 0xff;
    } else {
        /* 0x3f1 */
        switch (superio_conf->index) {
        case 0x00 ... 0xdf:
        case 0xe4:
        case 0xe5:
        case 0xe9 ... 0xed:
        case 0xf3:
        case 0xf5:
        case 0xf7:
        case 0xf9 ... 0xfb:
        case 0xfd ... 0xff:
            can_write = 0;
            break;
        default:
            can_write = 1;

            if (can_write) {
                switch (superio_conf->index) {
                case 0xe7:
                    if ((data & 0xff) != 0xfe) {
                        DPRINTF("chage uart 1 base. unsupported yet\n");
                    }
                    break;
                case 0xe8:
                    if ((data & 0xff) != 0xbe) {
                        DPRINTF("chage uart 2 base. unsupported yet\n");
                    }
                    break;

                default:
                    superio_conf->config[superio_conf->index] = data & 0xff;
                }
            }
        }
        superio_conf->config[superio_conf->index] = data & 0xff;
    }
}

static uint32_t superio_ioport_readb(void *opaque, uint32_t addr)
{
    SuperIOConfig *superio_conf = opaque;

    DPRINTF("superio_ioport_readb  address 0x%x\n", addr);
    return (superio_conf->config[superio_conf->index]);
}

static void vt82c686b_reset(void * opaque)
{
    PCIDevice *d = opaque;
    uint8_t *pci_conf = d->config;
    VT82C686BState *vt82c = DO_UPCAST(VT82C686BState, dev, d);

    pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0);
    pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
                 PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL);
    pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM);

    pci_conf[0x48] = 0x01; /* Miscellaneous Control 3 */
    pci_conf[0x4a] = 0x04; /* IDE interrupt Routing */
    pci_conf[0x4f] = 0x03; /* DMA/Master Mem Access Control 3 */
    pci_conf[0x50] = 0x2d; /* PnP DMA Request Control */
    pci_conf[0x59] = 0x04;
    pci_conf[0x5a] = 0x04; /* KBC/RTC Control*/
    pci_conf[0x5f] = 0x04;
    pci_conf[0x77] = 0x10; /* GPIO Control 1/2/3/4 */

    vt82c->superio_conf.config[0xe0] = 0x3c;
    vt82c->superio_conf.config[0xe2] = 0x03;
    vt82c->superio_conf.config[0xe3] = 0xfc;
    vt82c->superio_conf.config[0xe6] = 0xde;
    vt82c->superio_conf.config[0xe7] = 0xfe;
    vt82c->superio_conf.config[0xe8] = 0xbe;
}

/* write config pci function0 registers. PCI-ISA bridge */
static void vt82c686b_write_config(PCIDevice * d, uint32_t address,
                                   uint32_t val, int len)
{
    VT82C686BState *vt686 = DO_UPCAST(VT82C686BState, dev, d);

    DPRINTF("vt82c686b_write_config  address 0x%x  val 0x%x len 0x%x\n",
           address, val, len);

    pci_default_write_config(d, address, val, len);
    if (address == 0x85) {  /* enable or disable super IO configure */
        if (val & 0x2) {
            /* floppy also uses 0x3f0 and 0x3f1.
             * But we do not emulate flopy,so just set it here. */
            isa_unassign_ioport(0x3f0, 2);
            register_ioport_read(0x3f0, 2, 1, superio_ioport_readb,
                                 &vt686->superio_conf);
            register_ioport_write(0x3f0, 2, 1, superio_ioport_writeb,
                                  &vt686->superio_conf);
        } else {
            isa_unassign_ioport(0x3f0, 2);
        }
    }
}

#define ACPI_DBG_IO_ADDR  0xb044

typedef struct VT686PMState {
    PCIDevice dev;
    ACPIPM1EVT pm1a;
    ACPIPM1CNT pm1_cnt;
    APMState apm;
    ACPIPMTimer tmr;
    PMSMBus smb;
    uint32_t smb_io_base;
} VT686PMState;

typedef struct VT686AC97State {
    PCIDevice dev;
} VT686AC97State;

typedef struct VT686MC97State {
    PCIDevice dev;
} VT686MC97State;

static void pm_update_sci(VT686PMState *s)
{
    int sci_level, pmsts;

    pmsts = acpi_pm1_evt_get_sts(&s->pm1a, s->tmr.overflow_time);
    sci_level = (((pmsts & s->pm1a.en) &
                  (ACPI_BITMASK_RT_CLOCK_ENABLE |
                   ACPI_BITMASK_POWER_BUTTON_ENABLE |
                   ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
                   ACPI_BITMASK_TIMER_ENABLE)) != 0);
    qemu_set_irq(s->dev.irq[0], sci_level);
    /* schedule a timer interruption if needed */
    acpi_pm_tmr_update(&s->tmr, (s->pm1a.en & ACPI_BITMASK_TIMER_ENABLE) &&
                       !(pmsts & ACPI_BITMASK_TIMER_STATUS));
}

static void pm_tmr_timer(ACPIPMTimer *tmr)
{
    VT686PMState *s = container_of(tmr, VT686PMState, tmr);
    pm_update_sci(s);
}

static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
{
    VT686PMState *s = opaque;

    addr &= 0x0f;
    switch (addr) {
    case 0x00:
        acpi_pm1_evt_write_sts(&s->pm1a, &s->tmr, val);
        pm_update_sci(s);
        break;
    case 0x02:
        s->pm1a.en = val;
        pm_update_sci(s);
        break;
    case 0x04:
        acpi_pm1_cnt_write(&s->pm1a, &s->pm1_cnt, val);
        break;
    default:
        break;
    }
    DPRINTF("PM writew port=0x%04x val=0x%02x\n", addr, val);
}

static uint32_t pm_ioport_readw(void *opaque, uint32_t addr)
{
    VT686PMState *s = opaque;
    uint32_t val;

    addr &= 0x0f;
    switch (addr) {
    case 0x00:
        val = acpi_pm1_evt_get_sts(&s->pm1a, s->tmr.overflow_time);
        break;
    case 0x02:
        val = s->pm1a.en;
        break;
    case 0x04:
        val = s->pm1_cnt.cnt;
        break;
    default:
        val = 0;
        break;
    }
    DPRINTF("PM readw port=0x%04x val=0x%02x\n", addr, val);
    return val;
}

static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
{
    addr &= 0x0f;
    DPRINTF("PM writel port=0x%04x val=0x%08x\n", addr, val);
}

static uint32_t pm_ioport_readl(void *opaque, uint32_t addr)
{
    VT686PMState *s = opaque;
    uint32_t val;

    addr &= 0x0f;
    switch (addr) {
    case 0x08:
        val = acpi_pm_tmr_get(&s->tmr);
        break;
    default:
        val = 0;
        break;
    }
    DPRINTF("PM readl port=0x%04x val=0x%08x\n", addr, val);
    return val;
}

static void pm_io_space_update(VT686PMState *s)
{
    uint32_t pm_io_base;

    if (s->dev.config[0x80] & 1) {
        pm_io_base = pci_get_long(s->dev.config + 0x40);
        pm_io_base &= 0xffc0;

        /* XXX: need to improve memory and ioport allocation */
        DPRINTF("PM: mapping to 0x%x\n", pm_io_base);
        register_ioport_write(pm_io_base, 64, 2, pm_ioport_writew, s);
        register_ioport_read(pm_io_base, 64, 2, pm_ioport_readw, s);
        register_ioport_write(pm_io_base, 64, 4, pm_ioport_writel, s);
        register_ioport_read(pm_io_base, 64, 4, pm_ioport_readl, s);
    }
}

static void pm_write_config(PCIDevice *d,
                            uint32_t address, uint32_t val, int len)
{
    DPRINTF("pm_write_config  address 0x%x  val 0x%x len 0x%x\n",
           address, val, len);
    pci_default_write_config(d, address, val, len);
}

static int vmstate_acpi_post_load(void *opaque, int version_id)
{
    VT686PMState *s = opaque;

    pm_io_space_update(s);
    return 0;
}

static const VMStateDescription vmstate_acpi = {
    .name = "vt82c686b_pm",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .post_load = vmstate_acpi_post_load,
    .fields      = (VMStateField []) {
        VMSTATE_PCI_DEVICE(dev, VT686PMState),
        VMSTATE_UINT16(pm1a.sts, VT686PMState),
        VMSTATE_UINT16(pm1a.en, VT686PMState),
        VMSTATE_UINT16(pm1_cnt.cnt, VT686PMState),
        VMSTATE_STRUCT(apm, VT686PMState, 0, vmstate_apm, APMState),
        VMSTATE_TIMER(tmr.timer, VT686PMState),
        VMSTATE_INT64(tmr.overflow_time, VT686PMState),
        VMSTATE_END_OF_LIST()
    }
};

/*
 * TODO: vt82c686b_ac97_init() and vt82c686b_mc97_init()
 * just register a PCI device now, functionalities will be implemented later.
 */

static int vt82c686b_ac97_initfn(PCIDevice *dev)
{
    VT686AC97State *s = DO_UPCAST(VT686AC97State, dev, dev);
    uint8_t *pci_conf = s->dev.config;

    pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE |
                 PCI_COMMAND_PARITY);
    pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_CAP_LIST |
                 PCI_STATUS_DEVSEL_MEDIUM);
    pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03);

    return 0;
}

void vt82c686b_ac97_init(PCIBus *bus, int devfn)
{
    PCIDevice *dev;

    dev = pci_create(bus, devfn, "VT82C686B_AC97");
    qdev_init_nofail(&dev->qdev);
}

static PCIDeviceInfo via_ac97_info = {
    .qdev.name          = "VT82C686B_AC97",
    .qdev.desc          = "AC97",
    .qdev.size          = sizeof(VT686AC97State),
    .init               = vt82c686b_ac97_initfn,
    .vendor_id          = PCI_VENDOR_ID_VIA,
    .device_id          = PCI_DEVICE_ID_VIA_AC97,
    .revision           = 0x50,
    .class_id           = PCI_CLASS_MULTIMEDIA_AUDIO,
};

static void vt82c686b_ac97_register(void)
{
    pci_qdev_register(&via_ac97_info);
}

device_init(vt82c686b_ac97_register);

static int vt82c686b_mc97_initfn(PCIDevice *dev)
{
    VT686MC97State *s = DO_UPCAST(VT686MC97State, dev, dev);
    uint8_t *pci_conf = s->dev.config;

    pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE |
                 PCI_COMMAND_VGA_PALETTE);
    pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM);
    pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03);

    return 0;
}

void vt82c686b_mc97_init(PCIBus *bus, int devfn)
{
    PCIDevice *dev;

    dev = pci_create(bus, devfn, "VT82C686B_MC97");
    qdev_init_nofail(&dev->qdev);
}

static PCIDeviceInfo via_mc97_info = {
    .qdev.name          = "VT82C686B_MC97",
    .qdev.desc          = "MC97",
    .qdev.size          = sizeof(VT686MC97State),
    .init               = vt82c686b_mc97_initfn,
    .vendor_id          = PCI_VENDOR_ID_VIA,
    .device_id          = PCI_DEVICE_ID_VIA_MC97,
    .class_id           = PCI_CLASS_COMMUNICATION_OTHER,
    .revision           = 0x30,
};

static void vt82c686b_mc97_register(void)
{
    pci_qdev_register(&via_mc97_info);
}

device_init(vt82c686b_mc97_register);

/* vt82c686 pm init */
static int vt82c686b_pm_initfn(PCIDevice *dev)
{
    VT686PMState *s = DO_UPCAST(VT686PMState, dev, dev);
    uint8_t *pci_conf;

    pci_conf = s->dev.config;
    pci_set_word(pci_conf + PCI_COMMAND, 0);
    pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK |
                 PCI_STATUS_DEVSEL_MEDIUM);

    /* 0x48-0x4B is Power Management I/O Base */
    pci_set_long(pci_conf + 0x48, 0x00000001);

    /* SMB ports:0xeee0~0xeeef */
    s->smb_io_base =((s->smb_io_base & 0xfff0) + 0x0);
    pci_conf[0x90] = s->smb_io_base | 1;
    pci_conf[0x91] = s->smb_io_base >> 8;
    pci_conf[0xd2] = 0x90;
    register_ioport_write(s->smb_io_base, 0xf, 1, smb_ioport_writeb, &s->smb);
    register_ioport_read(s->smb_io_base, 0xf, 1, smb_ioport_readb, &s->smb);

    apm_init(&s->apm, NULL, s);

    acpi_pm_tmr_init(&s->tmr, pm_tmr_timer);
    acpi_pm1_cnt_init(&s->pm1_cnt, NULL);

    pm_smbus_init(&s->dev.qdev, &s->smb);

    return 0;
}

i2c_bus *vt82c686b_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
                       qemu_irq sci_irq)
{
    PCIDevice *dev;
    VT686PMState *s;

    dev = pci_create(bus, devfn, "VT82C686B_PM");
    qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base);

    s = DO_UPCAST(VT686PMState, dev, dev);

    qdev_init_nofail(&dev->qdev);

    return s->smb.smbus;
}

static PCIDeviceInfo via_pm_info = {
    .qdev.name          = "VT82C686B_PM",
    .qdev.desc          = "PM",
    .qdev.size          = sizeof(VT686PMState),
    .qdev.vmsd          = &vmstate_acpi,
    .init               = vt82c686b_pm_initfn,
    .config_write       = pm_write_config,
    .vendor_id          = PCI_VENDOR_ID_VIA,
    .device_id          = PCI_DEVICE_ID_VIA_ACPI,
    .class_id           = PCI_CLASS_BRIDGE_OTHER,
    .revision           = 0x40,
    .qdev.props         = (Property[]) {
        DEFINE_PROP_UINT32("smb_io_base", VT686PMState, smb_io_base, 0),
        DEFINE_PROP_END_OF_LIST(),
    }
};

static void vt82c686b_pm_register(void)
{
    pci_qdev_register(&via_pm_info);
}

device_init(vt82c686b_pm_register);

static const VMStateDescription vmstate_via = {
    .name = "vt82c686b",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields      = (VMStateField []) {
        VMSTATE_PCI_DEVICE(dev, VT82C686BState),
        VMSTATE_END_OF_LIST()
    }
};

/* init the PCI-to-ISA bridge */
static int vt82c686b_initfn(PCIDevice *d)
{
    uint8_t *pci_conf;
    uint8_t *wmask;
    int i;

    isa_bus_new(&d->qdev, pci_address_space_io(d));

    pci_conf = d->config;
    pci_config_set_prog_interface(pci_conf, 0x0);

    wmask = d->wmask;
    for (i = 0x00; i < 0xff; i++) {
       if (i<=0x03 || (i>=0x08 && i<=0x3f)) {
           wmask[i] = 0x00;
       }
    }

    qemu_register_reset(vt82c686b_reset, d);

    return 0;
}

int vt82c686b_init(PCIBus *bus, int devfn)
{
    PCIDevice *d;

    d = pci_create_simple_multifunction(bus, devfn, true, "VT82C686B");

    return d->devfn;
}

static PCIDeviceInfo via_info = {
    .qdev.name    = "VT82C686B",
    .qdev.desc    = "ISA bridge",
    .qdev.size    = sizeof(VT82C686BState),
    .qdev.vmsd    = &vmstate_via,
    .qdev.no_user = 1,
    .init         = vt82c686b_initfn,
    .config_write = vt82c686b_write_config,
    .vendor_id    = PCI_VENDOR_ID_VIA,
    .device_id    = PCI_DEVICE_ID_VIA_ISA_BRIDGE,
    .class_id     = PCI_CLASS_BRIDGE_ISA,
    .revision     = 0x40,
};

static void vt82c686b_register(void)
{
    pci_qdev_register(&via_info);
}
device_init(vt82c686b_register);
Commit	Line	Data
edf79e66 HC	1	/*
	2	* VT82C686B south bridge support
	3	*
	4	* Copyright (c) 2008 yajin ([email protected])
	5	* Copyright (c) 2009 chenming ([email protected])
	6	* Copyright (c) 2010 Huacai Chen ([email protected])
	7	* This code is licensed under the GNU GPL v2.
	8	*/
	9
	10	#include "hw.h"
	11	#include "pc.h"
	12	#include "vt82c686.h"
	13	#include "i2c.h"
	14	#include "smbus.h"
	15	#include "pci.h"
	16	#include "isa.h"
	17	#include "sysbus.h"
	18	#include "mips.h"
	19	#include "apm.h"
	20	#include "acpi.h"
	21	#include "pm_smbus.h"
	22	#include "sysemu.h"
	23	#include "qemu-timer.h"
	24
	25	typedef uint32_t pci_addr_t;
	26	#include "pci_host.h"
	27	//#define DEBUG_VT82C686B
	28
	29	#ifdef DEBUG_VT82C686B
	30	#define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__)
	31	#else
	32	#define DPRINTF(fmt, ...)
	33	#endif
	34
	35	typedef struct SuperIOConfig
	36	{
	37	uint8_t config[0xff];
	38	uint8_t index;
	39	uint8_t data;
	40	} SuperIOConfig;
	41
	42	typedef struct VT82C686BState {
	43	PCIDevice dev;
	44	SuperIOConfig superio_conf;
	45	} VT82C686BState;
	46
	47	static void superio_ioport_writeb(void *opaque, uint32_t addr, uint32_t data)
	48	{
	49	int can_write;
	50	SuperIOConfig *superio_conf = opaque;
	51
b2bedb21	52	DPRINTF("superio_ioport_writeb address 0x%x val 0x%x\n", addr, data);
edf79e66 HC	53	if (addr == 0x3f0) {
	54	superio_conf->index = data & 0xff;
	55	} else {
	56	/* 0x3f1 */
	57	switch (superio_conf->index) {
	58	case 0x00 ... 0xdf:
	59	case 0xe4:
	60	case 0xe5:
	61	case 0xe9 ... 0xed:
	62	case 0xf3:
	63	case 0xf5:
	64	case 0xf7:
	65	case 0xf9 ... 0xfb:
	66	case 0xfd ... 0xff:
	67	can_write = 0;
	68	break;
	69	default:
	70	can_write = 1;
	71
	72	if (can_write) {
	73	switch (superio_conf->index) {
	74	case 0xe7:
	75	if ((data & 0xff) != 0xfe) {
b2bedb21	76	DPRINTF("chage uart 1 base. unsupported yet\n");
edf79e66 HC	77	}
	78	break;
	79	case 0xe8:
	80	if ((data & 0xff) != 0xbe) {
b2bedb21	81	DPRINTF("chage uart 2 base. unsupported yet\n");
edf79e66 HC	82	}
	83	break;
	84
	85	default:
	86	superio_conf->config[superio_conf->index] = data & 0xff;
	87	}
	88	}
	89	}
	90	superio_conf->config[superio_conf->index] = data & 0xff;
	91	}
	92	}
	93
	94	static uint32_t superio_ioport_readb(void *opaque, uint32_t addr)
	95	{
	96	SuperIOConfig *superio_conf = opaque;
	97
b2bedb21	98	DPRINTF("superio_ioport_readb address 0x%x\n", addr);
edf79e66 HC	99	return (superio_conf->config[superio_conf->index]);
	100	}
	101
	102	static void vt82c686b_reset(void * opaque)
	103	{
	104	PCIDevice *d = opaque;
	105	uint8_t *pci_conf = d->config;
	106	VT82C686BState *vt82c = DO_UPCAST(VT82C686BState, dev, d);
	107
	108	pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0);
	109	pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO \| PCI_COMMAND_MEMORY \|
	110	PCI_COMMAND_MASTER \| PCI_COMMAND_SPECIAL);
	111	pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM);
	112
	113	pci_conf[0x48] = 0x01; /* Miscellaneous Control 3 */
	114	pci_conf[0x4a] = 0x04; /* IDE interrupt Routing */
	115	pci_conf[0x4f] = 0x03; /* DMA/Master Mem Access Control 3 */
	116	pci_conf[0x50] = 0x2d; /* PnP DMA Request Control */
	117	pci_conf[0x59] = 0x04;
	118	pci_conf[0x5a] = 0x04; /* KBC/RTC Control*/
	119	pci_conf[0x5f] = 0x04;
	120	pci_conf[0x77] = 0x10; /* GPIO Control 1/2/3/4 */
	121
	122	vt82c->superio_conf.config[0xe0] = 0x3c;
	123	vt82c->superio_conf.config[0xe2] = 0x03;
	124	vt82c->superio_conf.config[0xe3] = 0xfc;
	125	vt82c->superio_conf.config[0xe6] = 0xde;
	126	vt82c->superio_conf.config[0xe7] = 0xfe;
	127	vt82c->superio_conf.config[0xe8] = 0xbe;
	128	}
	129
	130	/* write config pci function0 registers. PCI-ISA bridge */
	131	static void vt82c686b_write_config(PCIDevice * d, uint32_t address,
	132	uint32_t val, int len)
	133	{
	134	VT82C686BState *vt686 = DO_UPCAST(VT82C686BState, dev, d);
	135
b2bedb21	136	DPRINTF("vt82c686b_write_config address 0x%x val 0x%x len 0x%x\n",
edf79e66 HC	137	address, val, len);
	138
	139	pci_default_write_config(d, address, val, len);
	140	if (address == 0x85) { /* enable or disable super IO configure */
	141	if (val & 0x2) {
	142	/* floppy also uses 0x3f0 and 0x3f1.
	143	* But we do not emulate flopy,so just set it here. */
	144	isa_unassign_ioport(0x3f0, 2);
	145	register_ioport_read(0x3f0, 2, 1, superio_ioport_readb,
	146	&vt686->superio_conf);
	147	register_ioport_write(0x3f0, 2, 1, superio_ioport_writeb,
	148	&vt686->superio_conf);
	149	} else {
	150	isa_unassign_ioport(0x3f0, 2);
	151	}
	152	}
	153	}
	154
	155	#define ACPI_DBG_IO_ADDR 0xb044
	156
	157	typedef struct VT686PMState {
	158	PCIDevice dev;
04dc308f	159	ACPIPM1EVT pm1a;
eaba51c5	160	ACPIPM1CNT pm1_cnt;
edf79e66	161	APMState apm;
a54d41a8	162	ACPIPMTimer tmr;
edf79e66 HC	163	PMSMBus smb;
	164	uint32_t smb_io_base;
	165	} VT686PMState;
	166
	167	typedef struct VT686AC97State {
	168	PCIDevice dev;
	169	} VT686AC97State;
	170
	171	typedef struct VT686MC97State {
	172	PCIDevice dev;
	173	} VT686MC97State;
	174
edf79e66 HC	175	static void pm_update_sci(VT686PMState *s)
	176	{
	177	int sci_level, pmsts;
edf79e66	178
04dc308f IY	179	pmsts = acpi_pm1_evt_get_sts(&s->pm1a, s->tmr.overflow_time);
	180	sci_level = (((pmsts & s->pm1a.en) &
	181	(ACPI_BITMASK_RT_CLOCK_ENABLE \|
	182	ACPI_BITMASK_POWER_BUTTON_ENABLE \|
	183	ACPI_BITMASK_GLOBAL_LOCK_ENABLE \|
	184	ACPI_BITMASK_TIMER_ENABLE)) != 0);
edf79e66 HC	185	qemu_set_irq(s->dev.irq[0], sci_level);
edf79e66 HC	186	/* schedule a timer interruption if needed */
04dc308f	187	acpi_pm_tmr_update(&s->tmr, (s->pm1a.en & ACPI_BITMASK_TIMER_ENABLE) &&
a54d41a8	188	!(pmsts & ACPI_BITMASK_TIMER_STATUS));
edf79e66 HC	189	}
edf79e66 HC	190
a54d41a8	191	static void pm_tmr_timer(ACPIPMTimer *tmr)
edf79e66	192	{
a54d41a8	193	VT686PMState *s = container_of(tmr, VT686PMState, tmr);
edf79e66 HC	194	pm_update_sci(s);
	195	}
	196
	197	static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
	198	{
	199	VT686PMState *s = opaque;
	200
	201	addr &= 0x0f;
	202	switch (addr) {
	203	case 0x00:
04dc308f IY	204	acpi_pm1_evt_write_sts(&s->pm1a, &s->tmr, val);
04dc308f IY	205	pm_update_sci(s);
edf79e66 HC	206	break;
edf79e66 HC	207	case 0x02:
04dc308f	208	s->pm1a.en = val;
edf79e66 HC	209	pm_update_sci(s);
	210	break;
	211	case 0x04:
eaba51c5	212	acpi_pm1_cnt_write(&s->pm1a, &s->pm1_cnt, val);
edf79e66 HC	213	break;
	214	default:
	215	break;
	216	}
	217	DPRINTF("PM writew port=0x%04x val=0x%02x\n", addr, val);
	218	}
	219
	220	static uint32_t pm_ioport_readw(void *opaque, uint32_t addr)
	221	{
	222	VT686PMState *s = opaque;
	223	uint32_t val;
	224
	225	addr &= 0x0f;
	226	switch (addr) {
	227	case 0x00:
04dc308f	228	val = acpi_pm1_evt_get_sts(&s->pm1a, s->tmr.overflow_time);
edf79e66 HC	229	break;
edf79e66 HC	230	case 0x02:
04dc308f	231	val = s->pm1a.en;
edf79e66 HC	232	break;
edf79e66 HC	233	case 0x04:
eaba51c5	234	val = s->pm1_cnt.cnt;
edf79e66 HC	235	break;
	236	default:
	237	val = 0;
	238	break;
	239	}
	240	DPRINTF("PM readw port=0x%04x val=0x%02x\n", addr, val);
	241	return val;
	242	}
	243
	244	static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
	245	{
	246	addr &= 0x0f;
	247	DPRINTF("PM writel port=0x%04x val=0x%08x\n", addr, val);
	248	}
	249
	250	static uint32_t pm_ioport_readl(void *opaque, uint32_t addr)
	251	{
	252	VT686PMState *s = opaque;
	253	uint32_t val;
	254
	255	addr &= 0x0f;
	256	switch (addr) {
	257	case 0x08:
a54d41a8	258	val = acpi_pm_tmr_get(&s->tmr);
edf79e66 HC	259	break;
	260	default:
	261	val = 0;
	262	break;
	263	}
	264	DPRINTF("PM readl port=0x%04x val=0x%08x\n", addr, val);
	265	return val;
	266	}
	267
	268	static void pm_io_space_update(VT686PMState *s)
	269	{
	270	uint32_t pm_io_base;
	271
	272	if (s->dev.config[0x80] & 1) {
	273	pm_io_base = pci_get_long(s->dev.config + 0x40);
	274	pm_io_base &= 0xffc0;
	275
	276	/* XXX: need to improve memory and ioport allocation */
	277	DPRINTF("PM: mapping to 0x%x\n", pm_io_base);
	278	register_ioport_write(pm_io_base, 64, 2, pm_ioport_writew, s);
	279	register_ioport_read(pm_io_base, 64, 2, pm_ioport_readw, s);
	280	register_ioport_write(pm_io_base, 64, 4, pm_ioport_writel, s);
	281	register_ioport_read(pm_io_base, 64, 4, pm_ioport_readl, s);
	282	}
	283	}
	284
	285	static void pm_write_config(PCIDevice *d,
	286	uint32_t address, uint32_t val, int len)
	287	{
b2bedb21	288	DPRINTF("pm_write_config address 0x%x val 0x%x len 0x%x\n",
edf79e66 HC	289	address, val, len);
	290	pci_default_write_config(d, address, val, len);
	291	}
	292
	293	static int vmstate_acpi_post_load(void *opaque, int version_id)
	294	{
	295	VT686PMState *s = opaque;
	296
	297	pm_io_space_update(s);
	298	return 0;
	299	}
	300
	301	static const VMStateDescription vmstate_acpi = {
	302	.name = "vt82c686b_pm",
	303	.version_id = 1,
	304	.minimum_version_id = 1,
	305	.minimum_version_id_old = 1,
	306	.post_load = vmstate_acpi_post_load,
	307	.fields = (VMStateField []) {
	308	VMSTATE_PCI_DEVICE(dev, VT686PMState),
04dc308f IY	309	VMSTATE_UINT16(pm1a.sts, VT686PMState),
04dc308f IY	310	VMSTATE_UINT16(pm1a.en, VT686PMState),
eaba51c5	311	VMSTATE_UINT16(pm1_cnt.cnt, VT686PMState),
edf79e66	312	VMSTATE_STRUCT(apm, VT686PMState, 0, vmstate_apm, APMState),
a54d41a8 IY	313	VMSTATE_TIMER(tmr.timer, VT686PMState),
a54d41a8 IY	314	VMSTATE_INT64(tmr.overflow_time, VT686PMState),
edf79e66 HC	315	VMSTATE_END_OF_LIST()
	316	}
	317	};
	318
	319	/*
	320	* TODO: vt82c686b_ac97_init() and vt82c686b_mc97_init()
	321	* just register a PCI device now, functionalities will be implemented later.
	322	*/
	323
	324	static int vt82c686b_ac97_initfn(PCIDevice *dev)
	325	{
	326	VT686AC97State *s = DO_UPCAST(VT686AC97State, dev, dev);
	327	uint8_t *pci_conf = s->dev.config;
	328
edf79e66 HC	329	pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE \|
	330	PCI_COMMAND_PARITY);
	331	pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_CAP_LIST \|
	332	PCI_STATUS_DEVSEL_MEDIUM);
	333	pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03);
	334
	335	return 0;
	336	}
	337
	338	void vt82c686b_ac97_init(PCIBus *bus, int devfn)
	339	{
	340	PCIDevice *dev;
	341
	342	dev = pci_create(bus, devfn, "VT82C686B_AC97");
	343	qdev_init_nofail(&dev->qdev);
	344	}
	345
	346	static PCIDeviceInfo via_ac97_info = {
	347	.qdev.name = "VT82C686B_AC97",
	348	.qdev.desc = "AC97",
	349	.qdev.size = sizeof(VT686AC97State),
	350	.init = vt82c686b_ac97_initfn,
1cf0d2b8 IY	351	.vendor_id = PCI_VENDOR_ID_VIA,
	352	.device_id = PCI_DEVICE_ID_VIA_AC97,
	353	.revision = 0x50,
	354	.class_id = PCI_CLASS_MULTIMEDIA_AUDIO,
edf79e66 HC	355	};
	356
	357	static void vt82c686b_ac97_register(void)
	358	{
	359	pci_qdev_register(&via_ac97_info);
	360	}
	361
	362	device_init(vt82c686b_ac97_register);
	363
	364	static int vt82c686b_mc97_initfn(PCIDevice *dev)
	365	{
	366	VT686MC97State *s = DO_UPCAST(VT686MC97State, dev, dev);
	367	uint8_t *pci_conf = s->dev.config;
	368
edf79e66 HC	369	pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE \|
	370	PCI_COMMAND_VGA_PALETTE);
	371	pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM);
	372	pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03);
	373
	374	return 0;
	375	}
	376
	377	void vt82c686b_mc97_init(PCIBus *bus, int devfn)
	378	{
	379	PCIDevice *dev;
	380
	381	dev = pci_create(bus, devfn, "VT82C686B_MC97");
	382	qdev_init_nofail(&dev->qdev);
	383	}
	384
	385	static PCIDeviceInfo via_mc97_info = {
	386	.qdev.name = "VT82C686B_MC97",
	387	.qdev.desc = "MC97",
	388	.qdev.size = sizeof(VT686MC97State),
	389	.init = vt82c686b_mc97_initfn,
1cf0d2b8 IY	390	.vendor_id = PCI_VENDOR_ID_VIA,
	391	.device_id = PCI_DEVICE_ID_VIA_MC97,
	392	.class_id = PCI_CLASS_COMMUNICATION_OTHER,
	393	.revision = 0x30,
edf79e66 HC	394	};
	395
	396	static void vt82c686b_mc97_register(void)
	397	{
	398	pci_qdev_register(&via_mc97_info);
	399	}
	400
	401	device_init(vt82c686b_mc97_register);
	402
	403	/* vt82c686 pm init */
	404	static int vt82c686b_pm_initfn(PCIDevice *dev)
	405	{
	406	VT686PMState *s = DO_UPCAST(VT686PMState, dev, dev);
	407	uint8_t *pci_conf;
	408
	409	pci_conf = s->dev.config;
edf79e66 HC	410	pci_set_word(pci_conf + PCI_COMMAND, 0);
	411	pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK \|
	412	PCI_STATUS_DEVSEL_MEDIUM);
	413
	414	/* 0x48-0x4B is Power Management I/O Base */
	415	pci_set_long(pci_conf + 0x48, 0x00000001);
	416
	417	/* SMB ports:0xeee0~0xeeef */
	418	s->smb_io_base =((s->smb_io_base & 0xfff0) + 0x0);
	419	pci_conf[0x90] = s->smb_io_base \| 1;
	420	pci_conf[0x91] = s->smb_io_base >> 8;
	421	pci_conf[0xd2] = 0x90;
	422	register_ioport_write(s->smb_io_base, 0xf, 1, smb_ioport_writeb, &s->smb);
	423	register_ioport_read(s->smb_io_base, 0xf, 1, smb_ioport_readb, &s->smb);
	424
	425	apm_init(&s->apm, NULL, s);
	426
a54d41a8	427	acpi_pm_tmr_init(&s->tmr, pm_tmr_timer);
eaba51c5	428	acpi_pm1_cnt_init(&s->pm1_cnt, NULL);
edf79e66 HC	429
	430	pm_smbus_init(&s->dev.qdev, &s->smb);
	431
	432	return 0;
	433	}
	434
	435	i2c_bus vt82c686b_pm_init(PCIBus bus, int devfn, uint32_t smb_io_base,
	436	qemu_irq sci_irq)
	437	{
	438	PCIDevice *dev;
	439	VT686PMState *s;
	440
	441	dev = pci_create(bus, devfn, "VT82C686B_PM");
	442	qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base);
	443
	444	s = DO_UPCAST(VT686PMState, dev, dev);
	445
	446	qdev_init_nofail(&dev->qdev);
	447
	448	return s->smb.smbus;
	449	}
	450
	451	static PCIDeviceInfo via_pm_info = {
	452	.qdev.name = "VT82C686B_PM",
	453	.qdev.desc = "PM",
	454	.qdev.size = sizeof(VT686PMState),
	455	.qdev.vmsd = &vmstate_acpi,
	456	.init = vt82c686b_pm_initfn,
	457	.config_write = pm_write_config,
1cf0d2b8 IY	458	.vendor_id = PCI_VENDOR_ID_VIA,
	459	.device_id = PCI_DEVICE_ID_VIA_ACPI,
	460	.class_id = PCI_CLASS_BRIDGE_OTHER,
	461	.revision = 0x40,
edf79e66 HC	462	.qdev.props = (Property[]) {
	463	DEFINE_PROP_UINT32("smb_io_base", VT686PMState, smb_io_base, 0),
	464	DEFINE_PROP_END_OF_LIST(),
	465	}
	466	};
	467
	468	static void vt82c686b_pm_register(void)
	469	{
	470	pci_qdev_register(&via_pm_info);
	471	}
	472
	473	device_init(vt82c686b_pm_register);
	474
	475	static const VMStateDescription vmstate_via = {
	476	.name = "vt82c686b",
	477	.version_id = 1,
	478	.minimum_version_id = 1,
	479	.minimum_version_id_old = 1,
	480	.fields = (VMStateField []) {
	481	VMSTATE_PCI_DEVICE(dev, VT82C686BState),
	482	VMSTATE_END_OF_LIST()
	483	}
	484	};
	485
	486	/* init the PCI-to-ISA bridge */
	487	static int vt82c686b_initfn(PCIDevice *d)
	488	{
	489	uint8_t *pci_conf;
	490	uint8_t *wmask;
	491	int i;
	492
c2d0d012	493	isa_bus_new(&d->qdev, pci_address_space_io(d));
edf79e66 HC	494
edf79e66 HC	495	pci_conf = d->config;
edf79e66	496	pci_config_set_prog_interface(pci_conf, 0x0);
edf79e66 HC	497
	498	wmask = d->wmask;
	499	for (i = 0x00; i < 0xff; i++) {
	500	if (i<=0x03 \|\| (i>=0x08 && i<=0x3f)) {
	501	wmask[i] = 0x00;
	502	}
	503	}
	504
	505	qemu_register_reset(vt82c686b_reset, d);
	506
	507	return 0;
	508	}
	509
	510	int vt82c686b_init(PCIBus *bus, int devfn)
	511	{
	512	PCIDevice *d;
	513
aa5fb7b3	514	d = pci_create_simple_multifunction(bus, devfn, true, "VT82C686B");
edf79e66 HC	515
	516	return d->devfn;
	517	}
	518
	519	static PCIDeviceInfo via_info = {
	520	.qdev.name = "VT82C686B",
	521	.qdev.desc = "ISA bridge",
	522	.qdev.size = sizeof(VT82C686BState),
	523	.qdev.vmsd = &vmstate_via,
	524	.qdev.no_user = 1,
	525	.init = vt82c686b_initfn,
	526	.config_write = vt82c686b_write_config,
1cf0d2b8 IY	527	.vendor_id = PCI_VENDOR_ID_VIA,
	528	.device_id = PCI_DEVICE_ID_VIA_ISA_BRIDGE,
	529	.class_id = PCI_CLASS_BRIDGE_ISA,
	530	.revision = 0x40,
edf79e66 HC	531	};
	532
	533	static void vt82c686b_register(void)
	534	{
	535	pci_qdev_register(&via_info);
	536	}
	537	device_init(vt82c686b_register);