[qemu.git] / hw / arm_timer.c

/*
 * ARM PrimeCell Timer modules.
 *
 * Copyright (c) 2005-2006 CodeSourcery.
 * Written by Paul Brook
 *
 * This code is licensed under the GPL.
 */

#include "sysbus.h"
#include "qemu-timer.h"

/* Common timer implementation.  */

#define TIMER_CTRL_ONESHOT      (1 << 0)
#define TIMER_CTRL_32BIT        (1 << 1)
#define TIMER_CTRL_DIV1         (0 << 2)
#define TIMER_CTRL_DIV16        (1 << 2)
#define TIMER_CTRL_DIV256       (2 << 2)
#define TIMER_CTRL_IE           (1 << 5)
#define TIMER_CTRL_PERIODIC     (1 << 6)
#define TIMER_CTRL_ENABLE       (1 << 7)

typedef struct {
    ptimer_state *timer;
    uint32_t control;
    uint32_t limit;
    int freq;
    int int_level;
    qemu_irq irq;
} arm_timer_state;

/* Check all active timers, and schedule the next timer interrupt.  */

static void arm_timer_update(arm_timer_state *s)
{
    /* Update interrupts.  */
    if (s->int_level && (s->control & TIMER_CTRL_IE)) {
        qemu_irq_raise(s->irq);
    } else {
        qemu_irq_lower(s->irq);
    }
}

static uint32_t arm_timer_read(void *opaque, target_phys_addr_t offset)
{
    arm_timer_state *s = (arm_timer_state *)opaque;

    switch (offset >> 2) {
    case 0: /* TimerLoad */
    case 6: /* TimerBGLoad */
        return s->limit;
    case 1: /* TimerValue */
        return ptimer_get_count(s->timer);
    case 2: /* TimerControl */
        return s->control;
    case 4: /* TimerRIS */
        return s->int_level;
    case 5: /* TimerMIS */
        if ((s->control & TIMER_CTRL_IE) == 0)
            return 0;
        return s->int_level;
    default:
        hw_error("arm_timer_read: Bad offset %x\n", (int)offset);
        return 0;
    }
}

/* Reset the timer limit after settings have changed.  */
static void arm_timer_recalibrate(arm_timer_state *s, int reload)
{
    uint32_t limit;

    if ((s->control & (TIMER_CTRL_PERIODIC | TIMER_CTRL_ONESHOT)) == 0) {
        /* Free running.  */
        if (s->control & TIMER_CTRL_32BIT)
            limit = 0xffffffff;
        else
            limit = 0xffff;
    } else {
          /* Periodic.  */
          limit = s->limit;
    }
    ptimer_set_limit(s->timer, limit, reload);
}

static void arm_timer_write(void *opaque, target_phys_addr_t offset,
                            uint32_t value)
{
    arm_timer_state *s = (arm_timer_state *)opaque;
    int freq;

    switch (offset >> 2) {
    case 0: /* TimerLoad */
        s->limit = value;
        arm_timer_recalibrate(s, 1);
        break;
    case 1: /* TimerValue */
        /* ??? Linux seems to want to write to this readonly register.
           Ignore it.  */
        break;
    case 2: /* TimerControl */
        if (s->control & TIMER_CTRL_ENABLE) {
            /* Pause the timer if it is running.  This may cause some
               inaccuracy dure to rounding, but avoids a whole lot of other
               messyness.  */
            ptimer_stop(s->timer);
        }
        s->control = value;
        freq = s->freq;
        /* ??? Need to recalculate expiry time after changing divisor.  */
        switch ((value >> 2) & 3) {
        case 1: freq >>= 4; break;
        case 2: freq >>= 8; break;
        }
        arm_timer_recalibrate(s, s->control & TIMER_CTRL_ENABLE);
        ptimer_set_freq(s->timer, freq);
        if (s->control & TIMER_CTRL_ENABLE) {
            /* Restart the timer if still enabled.  */
            ptimer_run(s->timer, (s->control & TIMER_CTRL_ONESHOT) != 0);
        }
        break;
    case 3: /* TimerIntClr */
        s->int_level = 0;
        break;
    case 6: /* TimerBGLoad */
        s->limit = value;
        arm_timer_recalibrate(s, 0);
        break;
    default:
        hw_error("arm_timer_write: Bad offset %x\n", (int)offset);
    }
    arm_timer_update(s);
}

static void arm_timer_tick(void *opaque)
{
    arm_timer_state *s = (arm_timer_state *)opaque;
    s->int_level = 1;
    arm_timer_update(s);
}

static const VMStateDescription vmstate_arm_timer = {
    .name = "arm_timer",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields      = (VMStateField[]) {
        VMSTATE_UINT32(control, arm_timer_state),
        VMSTATE_UINT32(limit, arm_timer_state),
        VMSTATE_INT32(int_level, arm_timer_state),
        VMSTATE_PTIMER(timer, arm_timer_state),
        VMSTATE_END_OF_LIST()
    }
};

static arm_timer_state *arm_timer_init(uint32_t freq)
{
    arm_timer_state *s;
    QEMUBH *bh;

    s = (arm_timer_state *)g_malloc0(sizeof(arm_timer_state));
    s->freq = freq;
    s->control = TIMER_CTRL_IE;

    bh = qemu_bh_new(arm_timer_tick, s);
    s->timer = ptimer_init(bh);
    vmstate_register(NULL, -1, &vmstate_arm_timer, s);
    return s;
}

/* ARM PrimeCell SP804 dual timer module.
   Docs for this device don't seem to be publicly available.  This
   implementation is based on guesswork, the linux kernel sources and the
   Integrator/CP timer modules.  */

typedef struct {
    SysBusDevice busdev;
    MemoryRegion iomem;
    arm_timer_state *timer[2];
    int level[2];
    qemu_irq irq;
} sp804_state;

/* Merge the IRQs from the two component devices.  */
static void sp804_set_irq(void *opaque, int irq, int level)
{
    sp804_state *s = (sp804_state *)opaque;

    s->level[irq] = level;
    qemu_set_irq(s->irq, s->level[0] || s->level[1]);
}

static uint64_t sp804_read(void *opaque, target_phys_addr_t offset,
                           unsigned size)
{
    sp804_state *s = (sp804_state *)opaque;

    /* ??? Don't know the PrimeCell ID for this device.  */
    if (offset < 0x20) {
        return arm_timer_read(s->timer[0], offset);
    } else {
        return arm_timer_read(s->timer[1], offset - 0x20);
    }
}

static void sp804_write(void *opaque, target_phys_addr_t offset,
                        uint64_t value, unsigned size)
{
    sp804_state *s = (sp804_state *)opaque;

    if (offset < 0x20) {
        arm_timer_write(s->timer[0], offset, value);
    } else {
        arm_timer_write(s->timer[1], offset - 0x20, value);
    }
}

static const MemoryRegionOps sp804_ops = {
    .read = sp804_read,
    .write = sp804_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static const VMStateDescription vmstate_sp804 = {
    .name = "sp804",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields      = (VMStateField[]) {
        VMSTATE_INT32_ARRAY(level, sp804_state, 2),
        VMSTATE_END_OF_LIST()
    }
};

static int sp804_init(SysBusDevice *dev)
{
    sp804_state *s = FROM_SYSBUS(sp804_state, dev);
    qemu_irq *qi;

    qi = qemu_allocate_irqs(sp804_set_irq, s, 2);
    sysbus_init_irq(dev, &s->irq);
    /* ??? The timers are actually configurable between 32kHz and 1MHz, but
       we don't implement that.  */
    s->timer[0] = arm_timer_init(1000000);
    s->timer[1] = arm_timer_init(1000000);
    s->timer[0]->irq = qi[0];
    s->timer[1]->irq = qi[1];
    memory_region_init_io(&s->iomem, &sp804_ops, s, "sp804", 0x1000);
    sysbus_init_mmio_region(dev, &s->iomem);
    vmstate_register(&dev->qdev, -1, &vmstate_sp804, s);
    return 0;
}


/* Integrator/CP timer module.  */

typedef struct {
    SysBusDevice busdev;
    MemoryRegion iomem;
    arm_timer_state *timer[3];
} icp_pit_state;

static uint64_t icp_pit_read(void *opaque, target_phys_addr_t offset,
                             unsigned size)
{
    icp_pit_state *s = (icp_pit_state *)opaque;
    int n;

    /* ??? Don't know the PrimeCell ID for this device.  */
    n = offset >> 8;
    if (n > 3) {
        hw_error("sp804_read: Bad timer %d\n", n);
    }

    return arm_timer_read(s->timer[n], offset & 0xff);
}

static void icp_pit_write(void *opaque, target_phys_addr_t offset,
                          uint64_t value, unsigned size)
{
    icp_pit_state *s = (icp_pit_state *)opaque;
    int n;

    n = offset >> 8;
    if (n > 3) {
        hw_error("sp804_write: Bad timer %d\n", n);
    }

    arm_timer_write(s->timer[n], offset & 0xff, value);
}

static const MemoryRegionOps icp_pit_ops = {
    .read = icp_pit_read,
    .write = icp_pit_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static int icp_pit_init(SysBusDevice *dev)
{
    icp_pit_state *s = FROM_SYSBUS(icp_pit_state, dev);

    /* Timer 0 runs at the system clock speed (40MHz).  */
    s->timer[0] = arm_timer_init(40000000);
    /* The other two timers run at 1MHz.  */
    s->timer[1] = arm_timer_init(1000000);
    s->timer[2] = arm_timer_init(1000000);

    sysbus_init_irq(dev, &s->timer[0]->irq);
    sysbus_init_irq(dev, &s->timer[1]->irq);
    sysbus_init_irq(dev, &s->timer[2]->irq);

    memory_region_init_io(&s->iomem, &icp_pit_ops, s, "icp_pit", 0x1000);
    sysbus_init_mmio_region(dev, &s->iomem);
    /* This device has no state to save/restore.  The component timers will
       save themselves.  */
    return 0;
}

static void arm_timer_register_devices(void)
{
    sysbus_register_dev("integrator_pit", sizeof(icp_pit_state), icp_pit_init);
    sysbus_register_dev("sp804", sizeof(sp804_state), sp804_init);
}

device_init(arm_timer_register_devices)
Commit	Line	Data
5fafdf24	1	/*
cdbdb648 PB	2	* ARM PrimeCell Timer modules.
	3	*
	4	* Copyright (c) 2005-2006 CodeSourcery.
	5	* Written by Paul Brook
	6	*
8e31bf38	7	* This code is licensed under the GPL.
cdbdb648 PB	8	*/
cdbdb648 PB	9
6a824ec3	10	#include "sysbus.h"
87ecb68b	11	#include "qemu-timer.h"
cdbdb648 PB	12
	13	/* Common timer implementation. */
	14
	15	#define TIMER_CTRL_ONESHOT (1 << 0)
	16	#define TIMER_CTRL_32BIT (1 << 1)
	17	#define TIMER_CTRL_DIV1 (0 << 2)
	18	#define TIMER_CTRL_DIV16 (1 << 2)
	19	#define TIMER_CTRL_DIV256 (2 << 2)
	20	#define TIMER_CTRL_IE (1 << 5)
	21	#define TIMER_CTRL_PERIODIC (1 << 6)
	22	#define TIMER_CTRL_ENABLE (1 << 7)
	23
	24	typedef struct {
423f0742	25	ptimer_state *timer;
cdbdb648	26	uint32_t control;
cdbdb648	27	uint32_t limit;
cdbdb648 PB	28	int freq;
cdbdb648 PB	29	int int_level;
d537cf6c	30	qemu_irq irq;
cdbdb648 PB	31	} arm_timer_state;
cdbdb648 PB	32
cdbdb648 PB	33	/* Check all active timers, and schedule the next timer interrupt. */
cdbdb648 PB	34
423f0742	35	static void arm_timer_update(arm_timer_state *s)
cdbdb648	36	{
cdbdb648 PB	37	/* Update interrupts. */
cdbdb648 PB	38	if (s->int_level && (s->control & TIMER_CTRL_IE)) {
d537cf6c	39	qemu_irq_raise(s->irq);
cdbdb648	40	} else {
d537cf6c	41	qemu_irq_lower(s->irq);
cdbdb648	42	}
cdbdb648 PB	43	}
cdbdb648 PB	44
c227f099	45	static uint32_t arm_timer_read(void *opaque, target_phys_addr_t offset)
cdbdb648 PB	46	{
	47	arm_timer_state s = (arm_timer_state )opaque;
	48
	49	switch (offset >> 2) {
	50	case 0: /* TimerLoad */
	51	case 6: /* TimerBGLoad */
	52	return s->limit;
	53	case 1: /* TimerValue */
423f0742	54	return ptimer_get_count(s->timer);
cdbdb648 PB	55	case 2: /* TimerControl */
	56	return s->control;
	57	case 4: /* TimerRIS */
	58	return s->int_level;
	59	case 5: /* TimerMIS */
	60	if ((s->control & TIMER_CTRL_IE) == 0)
	61	return 0;
	62	return s->int_level;
	63	default:
2ac71179	64	hw_error("arm_timer_read: Bad offset %x\n", (int)offset);
cdbdb648 PB	65	return 0;
	66	}
	67	}
	68
423f0742 PB	69	/* Reset the timer limit after settings have changed. */
	70	static void arm_timer_recalibrate(arm_timer_state *s, int reload)
	71	{
	72	uint32_t limit;
	73
a9cf98d9	74	if ((s->control & (TIMER_CTRL_PERIODIC \| TIMER_CTRL_ONESHOT)) == 0) {
423f0742 PB	75	/* Free running. */
	76	if (s->control & TIMER_CTRL_32BIT)
	77	limit = 0xffffffff;
	78	else
	79	limit = 0xffff;
	80	} else {
	81	/* Periodic. */
	82	limit = s->limit;
	83	}
	84	ptimer_set_limit(s->timer, limit, reload);
	85	}
	86
c227f099	87	static void arm_timer_write(void *opaque, target_phys_addr_t offset,
cdbdb648 PB	88	uint32_t value)
	89	{
	90	arm_timer_state s = (arm_timer_state )opaque;
423f0742	91	int freq;
cdbdb648	92
cdbdb648 PB	93	switch (offset >> 2) {
	94	case 0: /* TimerLoad */
	95	s->limit = value;
423f0742	96	arm_timer_recalibrate(s, 1);
cdbdb648 PB	97	break;
	98	case 1: /* TimerValue */
	99	/* ??? Linux seems to want to write to this readonly register.
	100	Ignore it. */
	101	break;
	102	case 2: /* TimerControl */
	103	if (s->control & TIMER_CTRL_ENABLE) {
	104	/* Pause the timer if it is running. This may cause some
	105	inaccuracy dure to rounding, but avoids a whole lot of other
	106	messyness. */
423f0742	107	ptimer_stop(s->timer);
cdbdb648 PB	108	}
cdbdb648 PB	109	s->control = value;
423f0742	110	freq = s->freq;
cdbdb648 PB	111	/* ??? Need to recalculate expiry time after changing divisor. */
cdbdb648 PB	112	switch ((value >> 2) & 3) {
423f0742 PB	113	case 1: freq >>= 4; break;
423f0742 PB	114	case 2: freq >>= 8; break;
cdbdb648	115	}
d6759902	116	arm_timer_recalibrate(s, s->control & TIMER_CTRL_ENABLE);
423f0742	117	ptimer_set_freq(s->timer, freq);
cdbdb648 PB	118	if (s->control & TIMER_CTRL_ENABLE) {
cdbdb648 PB	119	/* Restart the timer if still enabled. */
423f0742	120	ptimer_run(s->timer, (s->control & TIMER_CTRL_ONESHOT) != 0);
cdbdb648 PB	121	}
	122	break;
	123	case 3: /* TimerIntClr */
	124	s->int_level = 0;
	125	break;
	126	case 6: /* TimerBGLoad */
	127	s->limit = value;
423f0742	128	arm_timer_recalibrate(s, 0);
cdbdb648 PB	129	break;
cdbdb648 PB	130	default:
2ac71179	131	hw_error("arm_timer_write: Bad offset %x\n", (int)offset);
cdbdb648	132	}
423f0742	133	arm_timer_update(s);
cdbdb648 PB	134	}
	135
	136	static void arm_timer_tick(void *opaque)
	137	{
423f0742 PB	138	arm_timer_state s = (arm_timer_state )opaque;
	139	s->int_level = 1;
	140	arm_timer_update(s);
cdbdb648 PB	141	}
cdbdb648 PB	142
eecd33a5 JQ	143	static const VMStateDescription vmstate_arm_timer = {
	144	.name = "arm_timer",
	145	.version_id = 1,
	146	.minimum_version_id = 1,
	147	.minimum_version_id_old = 1,
	148	.fields = (VMStateField[]) {
	149	VMSTATE_UINT32(control, arm_timer_state),
	150	VMSTATE_UINT32(limit, arm_timer_state),
	151	VMSTATE_INT32(int_level, arm_timer_state),
	152	VMSTATE_PTIMER(timer, arm_timer_state),
	153	VMSTATE_END_OF_LIST()
	154	}
	155	};
23e39294	156
6a824ec3	157	static arm_timer_state *arm_timer_init(uint32_t freq)
cdbdb648 PB	158	{
cdbdb648 PB	159	arm_timer_state *s;
423f0742	160	QEMUBH *bh;
cdbdb648	161
7267c094	162	s = (arm_timer_state *)g_malloc0(sizeof(arm_timer_state));
423f0742	163	s->freq = freq;
cdbdb648	164	s->control = TIMER_CTRL_IE;
cdbdb648	165
423f0742 PB	166	bh = qemu_bh_new(arm_timer_tick, s);
423f0742 PB	167	s->timer = ptimer_init(bh);
eecd33a5	168	vmstate_register(NULL, -1, &vmstate_arm_timer, s);
cdbdb648 PB	169	return s;
	170	}
	171
	172	/* ARM PrimeCell SP804 dual timer module.
	173	Docs for this device don't seem to be publicly available. This
d85fb99b	174	implementation is based on guesswork, the linux kernel sources and the
cdbdb648 PB	175	Integrator/CP timer modules. */
	176
	177	typedef struct {
6a824ec3	178	SysBusDevice busdev;
e219dea2	179	MemoryRegion iomem;
6a824ec3	180	arm_timer_state *timer[2];
cdbdb648	181	int level[2];
d537cf6c	182	qemu_irq irq;
cdbdb648 PB	183	} sp804_state;
cdbdb648 PB	184
d537cf6c	185	/* Merge the IRQs from the two component devices. */
cdbdb648 PB	186	static void sp804_set_irq(void *opaque, int irq, int level)
	187	{
	188	sp804_state s = (sp804_state )opaque;
	189
	190	s->level[irq] = level;
d537cf6c	191	qemu_set_irq(s->irq, s->level[0] \|\| s->level[1]);
cdbdb648 PB	192	}
cdbdb648 PB	193
e219dea2 AK	194	static uint64_t sp804_read(void *opaque, target_phys_addr_t offset,
e219dea2 AK	195	unsigned size)
cdbdb648 PB	196	{
	197	sp804_state s = (sp804_state )opaque;
	198
	199	/* ??? Don't know the PrimeCell ID for this device. */
cdbdb648 PB	200	if (offset < 0x20) {
	201	return arm_timer_read(s->timer[0], offset);
	202	} else {
	203	return arm_timer_read(s->timer[1], offset - 0x20);
	204	}
	205	}
	206
c227f099	207	static void sp804_write(void *opaque, target_phys_addr_t offset,
e219dea2	208	uint64_t value, unsigned size)
cdbdb648 PB	209	{
	210	sp804_state s = (sp804_state )opaque;
	211
cdbdb648 PB	212	if (offset < 0x20) {
	213	arm_timer_write(s->timer[0], offset, value);
	214	} else {
	215	arm_timer_write(s->timer[1], offset - 0x20, value);
	216	}
	217	}
	218
e219dea2 AK	219	static const MemoryRegionOps sp804_ops = {
	220	.read = sp804_read,
	221	.write = sp804_write,
	222	.endianness = DEVICE_NATIVE_ENDIAN,
cdbdb648 PB	223	};
cdbdb648 PB	224
81986ac4 JQ	225	static const VMStateDescription vmstate_sp804 = {
	226	.name = "sp804",
	227	.version_id = 1,
	228	.minimum_version_id = 1,
	229	.minimum_version_id_old = 1,
	230	.fields = (VMStateField[]) {
	231	VMSTATE_INT32_ARRAY(level, sp804_state, 2),
	232	VMSTATE_END_OF_LIST()
	233	}
	234	};
23e39294	235
81a322d4	236	static int sp804_init(SysBusDevice *dev)
cdbdb648	237	{
6a824ec3	238	sp804_state *s = FROM_SYSBUS(sp804_state, dev);
d537cf6c	239	qemu_irq *qi;
cdbdb648	240
d537cf6c	241	qi = qemu_allocate_irqs(sp804_set_irq, s, 2);
6a824ec3	242	sysbus_init_irq(dev, &s->irq);
cdbdb648 PB	243	/* ??? The timers are actually configurable between 32kHz and 1MHz, but
cdbdb648 PB	244	we don't implement that. */
6a824ec3 PB	245	s->timer[0] = arm_timer_init(1000000);
	246	s->timer[1] = arm_timer_init(1000000);
	247	s->timer[0]->irq = qi[0];
	248	s->timer[1]->irq = qi[1];
e219dea2 AK	249	memory_region_init_io(&s->iomem, &sp804_ops, s, "sp804", 0x1000);
e219dea2 AK	250	sysbus_init_mmio_region(dev, &s->iomem);
81986ac4	251	vmstate_register(&dev->qdev, -1, &vmstate_sp804, s);
81a322d4	252	return 0;
cdbdb648 PB	253	}
	254
	255
	256	/* Integrator/CP timer module. */
	257
	258	typedef struct {
6a824ec3	259	SysBusDevice busdev;
e219dea2	260	MemoryRegion iomem;
6a824ec3	261	arm_timer_state *timer[3];
cdbdb648 PB	262	} icp_pit_state;
cdbdb648 PB	263
e219dea2 AK	264	static uint64_t icp_pit_read(void *opaque, target_phys_addr_t offset,
e219dea2 AK	265	unsigned size)
cdbdb648 PB	266	{
	267	icp_pit_state s = (icp_pit_state )opaque;
	268	int n;
	269
	270	/* ??? Don't know the PrimeCell ID for this device. */
cdbdb648	271	n = offset >> 8;
2ac71179 PB	272	if (n > 3) {
	273	hw_error("sp804_read: Bad timer %d\n", n);
	274	}
cdbdb648 PB	275
	276	return arm_timer_read(s->timer[n], offset & 0xff);
	277	}
	278
c227f099	279	static void icp_pit_write(void *opaque, target_phys_addr_t offset,
e219dea2	280	uint64_t value, unsigned size)
cdbdb648 PB	281	{
	282	icp_pit_state s = (icp_pit_state )opaque;
	283	int n;
	284
cdbdb648	285	n = offset >> 8;
2ac71179 PB	286	if (n > 3) {
	287	hw_error("sp804_write: Bad timer %d\n", n);
	288	}
cdbdb648 PB	289
	290	arm_timer_write(s->timer[n], offset & 0xff, value);
	291	}
	292
e219dea2 AK	293	static const MemoryRegionOps icp_pit_ops = {
	294	.read = icp_pit_read,
	295	.write = icp_pit_write,
	296	.endianness = DEVICE_NATIVE_ENDIAN,
cdbdb648 PB	297	};
cdbdb648 PB	298
81a322d4	299	static int icp_pit_init(SysBusDevice *dev)
cdbdb648	300	{
6a824ec3	301	icp_pit_state *s = FROM_SYSBUS(icp_pit_state, dev);
cdbdb648	302
cdbdb648	303	/* Timer 0 runs at the system clock speed (40MHz). */
6a824ec3	304	s->timer[0] = arm_timer_init(40000000);
cdbdb648	305	/* The other two timers run at 1MHz. */
6a824ec3 PB	306	s->timer[1] = arm_timer_init(1000000);
	307	s->timer[2] = arm_timer_init(1000000);
	308
	309	sysbus_init_irq(dev, &s->timer[0]->irq);
	310	sysbus_init_irq(dev, &s->timer[1]->irq);
	311	sysbus_init_irq(dev, &s->timer[2]->irq);
cdbdb648	312
e219dea2 AK	313	memory_region_init_io(&s->iomem, &icp_pit_ops, s, "icp_pit", 0x1000);
e219dea2 AK	314	sysbus_init_mmio_region(dev, &s->iomem);
23e39294 PB	315	/* This device has no state to save/restore. The component timers will
23e39294 PB	316	save themselves. */
81a322d4	317	return 0;
cdbdb648	318	}
6a824ec3 PB	319
	320	static void arm_timer_register_devices(void)
	321	{
	322	sysbus_register_dev("integrator_pit", sizeof(icp_pit_state), icp_pit_init);
	323	sysbus_register_dev("sp804", sizeof(sp804_state), sp804_init);
	324	}
	325
	326	device_init(arm_timer_register_devices)