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vga: set owner in vga_update_memory_access
[qemu.git] / hw / display / vga.c
CommitLineData
e89f66ec 1/*
4fa0f5d2 2 * QEMU VGA Emulator.
5fafdf24 3 *
e89f66ec 4 * Copyright (c) 2003 Fabrice Bellard
5fafdf24 5 *
e89f66ec
FB		 6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
83c9f4ca 24#include "hw/hw.h"
47b43a1f 25#include "vga.h"
28ecbaee 26#include "ui/console.h"
0d09e41a 27#include "hw/i386/pc.h"
83c9f4ca 28#include "hw/pci/pci.h"
47b43a1f 29#include "vga_int.h"
28ecbaee 30#include "ui/pixel_ops.h"
1de7afc9 31#include "qemu/timer.h"
0d09e41a 32#include "hw/xen/xen.h"
72750018 33#include "trace.h"
e89f66ec 34
e89f66ec 35//#define DEBUG_VGA
17b0018b 36//#define DEBUG_VGA_MEM
a41bc9af
FB		 37//#define DEBUG_VGA_REG
38
4fa0f5d2
FB		 39//#define DEBUG_BOCHS_VBE
40
9aa0ff0b
JK		 41/* 16 state changes per vertical frame @60 Hz */
42#define VGA_TEXT_CURSOR_PERIOD_MS (1000 * 2 * 16 / 60)
43
47c012e2
BS		 44/*
45 * Video Graphics Array (VGA)
46 *
47 * Chipset docs for original IBM VGA:
48 * http://www.mcamafia.de/pdf/ibm_vgaxga_trm2.pdf
49 *
50 * FreeVGA site:
51 * http://www.osdever.net/FreeVGA/home.htm
52 *
53 * Standard VGA features and Bochs VBE extensions are implemented.
54 */
55
e89f66ec 56/* force some bits to zero */
798b0c25 57const uint8_t sr_mask[8] = {
9e622b15
BS		 58 0x03,
59 0x3d,
60 0x0f,
61 0x3f,
62 0x0e,
63 0x00,
64 0x00,
65 0xff,
e89f66ec
FB		 66};
67
798b0c25 68const uint8_t gr_mask[16] = {
9e622b15
BS		 69 0x0f, /* 0x00 */
70 0x0f, /* 0x01 */
71 0x0f, /* 0x02 */
72 0x1f, /* 0x03 */
73 0x03, /* 0x04 */
74 0x7b, /* 0x05 */
75 0x0f, /* 0x06 */
76 0x0f, /* 0x07 */
77 0xff, /* 0x08 */
78 0x00, /* 0x09 */
79 0x00, /* 0x0a */
80 0x00, /* 0x0b */
81 0x00, /* 0x0c */
82 0x00, /* 0x0d */
83 0x00, /* 0x0e */
84 0x00, /* 0x0f */
e89f66ec
FB		 85};
86
87#define cbswap_32(__x) \
88((uint32_t)( \
89 (((uint32_t)(__x) & (uint32_t)0x000000ffUL) << 24) | \
90 (((uint32_t)(__x) & (uint32_t)0x0000ff00UL) << 8) | \
91 (((uint32_t)(__x) & (uint32_t)0x00ff0000UL) >> 8) | \
92 (((uint32_t)(__x) & (uint32_t)0xff000000UL) >> 24) ))
93
e2542fe2 94#ifdef HOST_WORDS_BIGENDIAN
e89f66ec
FB		 95#define PAT(x) cbswap_32(x)
96#else
97#define PAT(x) (x)
98#endif
99
e2542fe2 100#ifdef HOST_WORDS_BIGENDIAN
b8ed223b
FB		 101#define BIG 1
102#else
103#define BIG 0
104#endif
105
e2542fe2 106#ifdef HOST_WORDS_BIGENDIAN
b8ed223b
FB		 107#define GET_PLANE(data, p) (((data) >> (24 - (p) * 8)) & 0xff)
108#else
109#define GET_PLANE(data, p) (((data) >> ((p) * 8)) & 0xff)
110#endif
111
e89f66ec
FB		 112static const uint32_t mask16[16] = {
113 PAT(0x00000000),
114 PAT(0x000000ff),
115 PAT(0x0000ff00),
116 PAT(0x0000ffff),
117 PAT(0x00ff0000),
118 PAT(0x00ff00ff),
119 PAT(0x00ffff00),
120 PAT(0x00ffffff),
121 PAT(0xff000000),
122 PAT(0xff0000ff),
123 PAT(0xff00ff00),
124 PAT(0xff00ffff),
125 PAT(0xffff0000),
126 PAT(0xffff00ff),
127 PAT(0xffffff00),
128 PAT(0xffffffff),
129};
130
131#undef PAT
132
e2542fe2 133#ifdef HOST_WORDS_BIGENDIAN
e89f66ec
FB		 134#define PAT(x) (x)
135#else
136#define PAT(x) cbswap_32(x)
137#endif
138
139static const uint32_t dmask16[16] = {
140 PAT(0x00000000),
141 PAT(0x000000ff),
142 PAT(0x0000ff00),
143 PAT(0x0000ffff),
144 PAT(0x00ff0000),
145 PAT(0x00ff00ff),
146 PAT(0x00ffff00),
147 PAT(0x00ffffff),
148 PAT(0xff000000),
149 PAT(0xff0000ff),
150 PAT(0xff00ff00),
151 PAT(0xff00ffff),
152 PAT(0xffff0000),
153 PAT(0xffff00ff),
154 PAT(0xffffff00),
155 PAT(0xffffffff),
156};
157
158static const uint32_t dmask4[4] = {
159 PAT(0x00000000),
160 PAT(0x0000ffff),
161 PAT(0xffff0000),
162 PAT(0xffffffff),
163};
164
165static uint32_t expand4[256];
166static uint16_t expand2[256];
17b0018b 167static uint8_t expand4to8[16];
e89f66ec 168
80763888
JK		 169static void vga_update_memory_access(VGACommonState *s)
170{
171 MemoryRegion *region, *old_region = s->chain4_alias;
a8170e5e 172 hwaddr base, offset, size;
80763888
JK		 173
174 s->chain4_alias = NULL;
175
5e55efc9
BS		 176 if ((s->sr[VGA_SEQ_PLANE_WRITE] & VGA_SR02_ALL_PLANES) ==
177 VGA_SR02_ALL_PLANES && s->sr[VGA_SEQ_MEMORY_MODE] & VGA_SR04_CHN_4M) {
80763888 178 offset = 0;
5e55efc9 179 switch ((s->gr[VGA_GFX_MISC] >> 2) & 3) {
80763888
JK		 180 case 0:
181 base = 0xa0000;
182 size = 0x20000;
183 break;
184 case 1:
185 base = 0xa0000;
186 size = 0x10000;
187 offset = s->bank_offset;
188 break;
189 case 2:
190 base = 0xb0000;
191 size = 0x8000;
192 break;
193 case 3:
f065aa0a 194 default:
80763888
JK		 195 base = 0xb8000;
196 size = 0x8000;
197 break;
198 }
71579cae 199 base += isa_mem_base;
80763888 200 region = g_malloc(sizeof(*region));
42e038fe
PB		 201 memory_region_init_alias(region, memory_region_owner(&s->vram),
202 "vga.chain4", &s->vram, offset, size);
80763888
JK		 203 memory_region_add_subregion_overlap(s->legacy_address_space, base,
204 region, 2);
205 s->chain4_alias = region;
206 }
207 if (old_region) {
208 memory_region_del_subregion(s->legacy_address_space, old_region);
209 memory_region_destroy(old_region);
210 g_free(old_region);
211 s->plane_updated = 0xf;
212 }
213}
214
cedd91d2 215static void vga_dumb_update_retrace_info(VGACommonState *s)
cb5a7aa8 216{
217 (void) s;
218}
219
cedd91d2 220static void vga_precise_update_retrace_info(VGACommonState *s)
cb5a7aa8 221{
222 int htotal_chars;
223 int hretr_start_char;
224 int hretr_skew_chars;
225 int hretr_end_char;
226
227 int vtotal_lines;
228 int vretr_start_line;
229 int vretr_end_line;
230
7f5b7d3e
BS		 231 int dots;
232#if 0
233 int div2, sldiv2;
234#endif
cb5a7aa8 235 int clocking_mode;
236 int clock_sel;
b0f74c87 237 const int clk_hz[] = {25175000, 28322000, 25175000, 25175000};
cb5a7aa8 238 int64_t chars_per_sec;
239 struct vga_precise_retrace *r = &s->retrace_info.precise;
240
5e55efc9
BS		 241 htotal_chars = s->cr[VGA_CRTC_H_TOTAL] + 5;
242 hretr_start_char = s->cr[VGA_CRTC_H_SYNC_START];
243 hretr_skew_chars = (s->cr[VGA_CRTC_H_SYNC_END] >> 5) & 3;
244 hretr_end_char = s->cr[VGA_CRTC_H_SYNC_END] & 0x1f;
cb5a7aa8 245
5e55efc9
BS		 246 vtotal_lines = (s->cr[VGA_CRTC_V_TOTAL] |
247 (((s->cr[VGA_CRTC_OVERFLOW] & 1) |
248 ((s->cr[VGA_CRTC_OVERFLOW] >> 4) & 2)) << 8)) + 2;
249 vretr_start_line = s->cr[VGA_CRTC_V_SYNC_START] |
250 ((((s->cr[VGA_CRTC_OVERFLOW] >> 2) & 1) |
251 ((s->cr[VGA_CRTC_OVERFLOW] >> 6) & 2)) << 8);
252 vretr_end_line = s->cr[VGA_CRTC_V_SYNC_END] & 0xf;
cb5a7aa8 253
5e55efc9 254 clocking_mode = (s->sr[VGA_SEQ_CLOCK_MODE] >> 3) & 1;
cb5a7aa8 255 clock_sel = (s->msr >> 2) & 3;
f87fc09b 256 dots = (s->msr & 1) ? 8 : 9;
cb5a7aa8 257
b0f74c87 258 chars_per_sec = clk_hz[clock_sel] / dots;
cb5a7aa8 259
260 htotal_chars <<= clocking_mode;
261
262 r->total_chars = vtotal_lines * htotal_chars;
cb5a7aa8 263 if (r->freq) {
6ee093c9 264 r->ticks_per_char = get_ticks_per_sec() / (r->total_chars * r->freq);
cb5a7aa8 265 } else {
6ee093c9 266 r->ticks_per_char = get_ticks_per_sec() / chars_per_sec;
cb5a7aa8 267 }
268
269 r->vstart = vretr_start_line;
270 r->vend = r->vstart + vretr_end_line + 1;
271
272 r->hstart = hretr_start_char + hretr_skew_chars;
273 r->hend = r->hstart + hretr_end_char + 1;
274 r->htotal = htotal_chars;
275
f87fc09b 276#if 0
5e55efc9
BS		 277 div2 = (s->cr[VGA_CRTC_MODE] >> 2) & 1;
278 sldiv2 = (s->cr[VGA_CRTC_MODE] >> 3) & 1;
cb5a7aa8 279 printf (
f87fc09b 280 "hz=%f\n"
cb5a7aa8 281 "htotal = %d\n"
282 "hretr_start = %d\n"
283 "hretr_skew = %d\n"
284 "hretr_end = %d\n"
285 "vtotal = %d\n"
286 "vretr_start = %d\n"
287 "vretr_end = %d\n"
288 "div2 = %d sldiv2 = %d\n"
289 "clocking_mode = %d\n"
290 "clock_sel = %d %d\n"
291 "dots = %d\n"
0bfcd599 292 "ticks/char = %" PRId64 "\n"
cb5a7aa8 293 "\n",
6ee093c9 294 (double) get_ticks_per_sec() / (r->ticks_per_char * r->total_chars),
cb5a7aa8 295 htotal_chars,
296 hretr_start_char,
297 hretr_skew_chars,
298 hretr_end_char,
299 vtotal_lines,
300 vretr_start_line,
301 vretr_end_line,
302 div2, sldiv2,
303 clocking_mode,
304 clock_sel,
b0f74c87 305 clk_hz[clock_sel],
cb5a7aa8 306 dots,
307 r->ticks_per_char
308 );
309#endif
310}
311
cedd91d2 312static uint8_t vga_precise_retrace(VGACommonState *s)
cb5a7aa8 313{
314 struct vga_precise_retrace *r = &s->retrace_info.precise;
315 uint8_t val = s->st01 & ~(ST01_V_RETRACE | ST01_DISP_ENABLE);
316
317 if (r->total_chars) {
318 int cur_line, cur_line_char, cur_char;
319 int64_t cur_tick;
320
74475455 321 cur_tick = qemu_get_clock_ns(vm_clock);
cb5a7aa8 322
323 cur_char = (cur_tick / r->ticks_per_char) % r->total_chars;
324 cur_line = cur_char / r->htotal;
325
326 if (cur_line >= r->vstart && cur_line <= r->vend) {
327 val |= ST01_V_RETRACE | ST01_DISP_ENABLE;
f87fc09b 328 } else {
329 cur_line_char = cur_char % r->htotal;
330 if (cur_line_char >= r->hstart && cur_line_char <= r->hend) {
331 val |= ST01_DISP_ENABLE;
332 }
cb5a7aa8 333 }
334
335 return val;
336 } else {
337 return s->st01 ^ (ST01_V_RETRACE | ST01_DISP_ENABLE);
338 }
339}
340
cedd91d2 341static uint8_t vga_dumb_retrace(VGACommonState *s)
cb5a7aa8 342{
343 return s->st01 ^ (ST01_V_RETRACE | ST01_DISP_ENABLE);
344}
345
25a18cbd
JQ		 346int vga_ioport_invalid(VGACommonState *s, uint32_t addr)
347{
5e55efc9 348 if (s->msr & VGA_MIS_COLOR) {
25a18cbd
JQ		 349 /* Color */
350 return (addr >= 0x3b0 && addr <= 0x3bf);
351 } else {
352 /* Monochrome */
353 return (addr >= 0x3d0 && addr <= 0x3df);
354 }
355}
356
43bf782b 357uint32_t vga_ioport_read(void *opaque, uint32_t addr)
e89f66ec 358{
43bf782b 359 VGACommonState *s = opaque;
e89f66ec
FB		 360 int val, index;
361
bd8f2f5d
JK		 362 qemu_flush_coalesced_mmio_buffer();
363
25a18cbd 364 if (vga_ioport_invalid(s, addr)) {
e89f66ec
FB		 365 val = 0xff;
366 } else {
367 switch(addr) {
5e55efc9 368 case VGA_ATT_W:
e89f66ec
FB		 369 if (s->ar_flip_flop == 0) {
370 val = s->ar_index;
371 } else {
372 val = 0;
373 }
374 break;
5e55efc9 375 case VGA_ATT_R:
e89f66ec 376 index = s->ar_index & 0x1f;
5e55efc9 377 if (index < VGA_ATT_C) {
e89f66ec 378 val = s->ar[index];
5e55efc9 379 } else {
e89f66ec 380 val = 0;
5e55efc9 381 }
e89f66ec 382 break;
5e55efc9 383 case VGA_MIS_W:
e89f66ec
FB		 384 val = s->st00;
385 break;
5e55efc9 386 case VGA_SEQ_I:
e89f66ec
FB		 387 val = s->sr_index;
388 break;
5e55efc9 389 case VGA_SEQ_D:
e89f66ec 390 val = s->sr[s->sr_index];
a41bc9af
FB		 391#ifdef DEBUG_VGA_REG
392 printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
393#endif
e89f66ec 394 break;
5e55efc9 395 case VGA_PEL_IR:
e89f66ec
FB		 396 val = s->dac_state;
397 break;
5e55efc9 398 case VGA_PEL_IW:
e9b43ea3
JQ		 399 val = s->dac_write_index;
400 break;
5e55efc9 401 case VGA_PEL_D:
e89f66ec
FB		 402 val = s->palette[s->dac_read_index * 3 + s->dac_sub_index];
403 if (++s->dac_sub_index == 3) {
404 s->dac_sub_index = 0;
405 s->dac_read_index++;
406 }
407 break;
5e55efc9 408 case VGA_FTC_R:
e89f66ec
FB		 409 val = s->fcr;
410 break;
5e55efc9 411 case VGA_MIS_R:
e89f66ec
FB		 412 val = s->msr;
413 break;
5e55efc9 414 case VGA_GFX_I:
e89f66ec
FB		 415 val = s->gr_index;
416 break;
5e55efc9 417 case VGA_GFX_D:
e89f66ec 418 val = s->gr[s->gr_index];
a41bc9af
FB		 419#ifdef DEBUG_VGA_REG
420 printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
421#endif
e89f66ec 422 break;
5e55efc9
BS		 423 case VGA_CRT_IM:
424 case VGA_CRT_IC:
e89f66ec
FB		 425 val = s->cr_index;
426 break;
5e55efc9
BS		 427 case VGA_CRT_DM:
428 case VGA_CRT_DC:
e89f66ec 429 val = s->cr[s->cr_index];
a41bc9af
FB		 430#ifdef DEBUG_VGA_REG
431 printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
a41bc9af 432#endif
e89f66ec 433 break;
5e55efc9
BS		 434 case VGA_IS1_RM:
435 case VGA_IS1_RC:
e89f66ec 436 /* just toggle to fool polling */
cb5a7aa8 437 val = s->st01 = s->retrace(s);
e89f66ec
FB		 438 s->ar_flip_flop = 0;
439 break;
440 default:
441 val = 0x00;
442 break;
443 }
444 }
4fa0f5d2 445#if defined(DEBUG_VGA)
e89f66ec
FB		 446 printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
447#endif
448 return val;
449}
450
43bf782b 451void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
e89f66ec 452{
43bf782b 453 VGACommonState *s = opaque;
5467a722 454 int index;
e89f66ec 455
bd8f2f5d
JK		 456 qemu_flush_coalesced_mmio_buffer();
457
e89f66ec 458 /* check port range access depending on color/monochrome mode */
25a18cbd 459 if (vga_ioport_invalid(s, addr)) {
e89f66ec 460 return;
25a18cbd 461 }
e89f66ec
FB		 462#ifdef DEBUG_VGA
463 printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
464#endif
465
466 switch(addr) {
5e55efc9 467 case VGA_ATT_W:
e89f66ec
FB		 468 if (s->ar_flip_flop == 0) {
469 val &= 0x3f;
470 s->ar_index = val;
471 } else {
472 index = s->ar_index & 0x1f;
473 switch(index) {
5e55efc9 474 case VGA_ATC_PALETTE0 ... VGA_ATC_PALETTEF:
e89f66ec
FB		 475 s->ar[index] = val & 0x3f;
476 break;
5e55efc9 477 case VGA_ATC_MODE:
e89f66ec
FB		 478 s->ar[index] = val & ~0x10;
479 break;
5e55efc9 480 case VGA_ATC_OVERSCAN:
e89f66ec
FB		 481 s->ar[index] = val;
482 break;
5e55efc9 483 case VGA_ATC_PLANE_ENABLE:
e89f66ec
FB		 484 s->ar[index] = val & ~0xc0;
485 break;
5e55efc9 486 case VGA_ATC_PEL:
e89f66ec
FB		 487 s->ar[index] = val & ~0xf0;
488 break;
5e55efc9 489 case VGA_ATC_COLOR_PAGE:
e89f66ec
FB		 490 s->ar[index] = val & ~0xf0;
491 break;
492 default:
493 break;
494 }
495 }
496 s->ar_flip_flop ^= 1;
497 break;
5e55efc9 498 case VGA_MIS_W:
e89f66ec 499 s->msr = val & ~0x10;
cb5a7aa8 500 s->update_retrace_info(s);
e89f66ec 501 break;
5e55efc9 502 case VGA_SEQ_I:
e89f66ec
FB		 503 s->sr_index = val & 7;
504 break;
5e55efc9 505 case VGA_SEQ_D:
a41bc9af
FB		 506#ifdef DEBUG_VGA_REG
507 printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
508#endif
e89f66ec 509 s->sr[s->sr_index] = val & sr_mask[s->sr_index];
5e55efc9
BS		 510 if (s->sr_index == VGA_SEQ_CLOCK_MODE) {
511 s->update_retrace_info(s);
512 }
80763888 513 vga_update_memory_access(s);
e89f66ec 514 break;
5e55efc9 515 case VGA_PEL_IR:
e89f66ec
FB		 516 s->dac_read_index = val;
517 s->dac_sub_index = 0;
518 s->dac_state = 3;
519 break;
5e55efc9 520 case VGA_PEL_IW:
e89f66ec
FB		 521 s->dac_write_index = val;
522 s->dac_sub_index = 0;
523 s->dac_state = 0;
524 break;
5e55efc9 525 case VGA_PEL_D:
e89f66ec
FB		 526 s->dac_cache[s->dac_sub_index] = val;
527 if (++s->dac_sub_index == 3) {
528 memcpy(&s->palette[s->dac_write_index * 3], s->dac_cache, 3);
529 s->dac_sub_index = 0;
530 s->dac_write_index++;
531 }
532 break;
5e55efc9 533 case VGA_GFX_I:
e89f66ec
FB		 534 s->gr_index = val & 0x0f;
535 break;
5e55efc9 536 case VGA_GFX_D:
a41bc9af
FB		 537#ifdef DEBUG_VGA_REG
538 printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
539#endif
e89f66ec 540 s->gr[s->gr_index] = val & gr_mask[s->gr_index];
80763888 541 vga_update_memory_access(s);
e89f66ec 542 break;
5e55efc9
BS		 543 case VGA_CRT_IM:
544 case VGA_CRT_IC:
e89f66ec
FB		 545 s->cr_index = val;
546 break;
5e55efc9
BS		 547 case VGA_CRT_DM:
548 case VGA_CRT_DC:
a41bc9af
FB		 549#ifdef DEBUG_VGA_REG
550 printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
551#endif
e89f66ec 552 /* handle CR0-7 protection */
df800210 553 if ((s->cr[VGA_CRTC_V_SYNC_END] & VGA_CR11_LOCK_CR0_CR7) &&
554 s->cr_index <= VGA_CRTC_OVERFLOW) {
555 /* can always write bit 4 of CR7 */
556 if (s->cr_index == VGA_CRTC_OVERFLOW) {
557 s->cr[VGA_CRTC_OVERFLOW] = (s->cr[VGA_CRTC_OVERFLOW] & ~0x10) |
558 (val & 0x10);
5e55efc9 559 }
df800210 560 return;
e89f66ec 561 }
a46007a0 562 s->cr[s->cr_index] = val;
cb5a7aa8 563
564 switch(s->cr_index) {
5e55efc9
BS		 565 case VGA_CRTC_H_TOTAL:
566 case VGA_CRTC_H_SYNC_START:
567 case VGA_CRTC_H_SYNC_END:
568 case VGA_CRTC_V_TOTAL:
569 case VGA_CRTC_OVERFLOW:
570 case VGA_CRTC_V_SYNC_END:
571 case VGA_CRTC_MODE:
cb5a7aa8 572 s->update_retrace_info(s);
573 break;
574 }
e89f66ec 575 break;
5e55efc9
BS		 576 case VGA_IS1_RM:
577 case VGA_IS1_RC:
e89f66ec
FB		 578 s->fcr = val & 0x10;
579 break;
580 }
581}
582
09a79b49 583static uint32_t vbe_ioport_read_index(void *opaque, uint32_t addr)
4fa0f5d2 584{
cedd91d2 585 VGACommonState *s = opaque;
4fa0f5d2 586 uint32_t val;
09a79b49
FB		 587 val = s->vbe_index;
588 return val;
589}
4fa0f5d2 590
803ff052 591uint32_t vbe_ioport_read_data(void *opaque, uint32_t addr)
09a79b49 592{
cedd91d2 593 VGACommonState *s = opaque;
09a79b49
FB		 594 uint32_t val;
595
af92284b 596 if (s->vbe_index < VBE_DISPI_INDEX_NB) {
8454df8b
FB		 597 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_GETCAPS) {
598 switch(s->vbe_index) {
599 /* XXX: do not hardcode ? */
600 case VBE_DISPI_INDEX_XRES:
601 val = VBE_DISPI_MAX_XRES;
602 break;
603 case VBE_DISPI_INDEX_YRES:
604 val = VBE_DISPI_MAX_YRES;
605 break;
606 case VBE_DISPI_INDEX_BPP:
607 val = VBE_DISPI_MAX_BPP;
608 break;
609 default:
5fafdf24 610 val = s->vbe_regs[s->vbe_index];
8454df8b
FB		 611 break;
612 }
613 } else {
5fafdf24 614 val = s->vbe_regs[s->vbe_index];
8454df8b 615 }
af92284b
GH		 616 } else if (s->vbe_index == VBE_DISPI_INDEX_VIDEO_MEMORY_64K) {
617 val = s->vram_size / (64 * 1024);
8454df8b 618 } else {
09a79b49 619 val = 0;
8454df8b 620 }
4fa0f5d2 621#ifdef DEBUG_BOCHS_VBE
09a79b49 622 printf("VBE: read index=0x%x val=0x%x\n", s->vbe_index, val);
4fa0f5d2 623#endif
4fa0f5d2
FB		 624 return val;
625}
626
803ff052 627void vbe_ioport_write_index(void *opaque, uint32_t addr, uint32_t val)
09a79b49 628{
cedd91d2 629 VGACommonState *s = opaque;
09a79b49
FB		 630 s->vbe_index = val;
631}
632
803ff052 633void vbe_ioport_write_data(void *opaque, uint32_t addr, uint32_t val)
4fa0f5d2 634{
cedd91d2 635 VGACommonState *s = opaque;
4fa0f5d2 636
09a79b49 637 if (s->vbe_index <= VBE_DISPI_INDEX_NB) {
4fa0f5d2
FB		 638#ifdef DEBUG_BOCHS_VBE
639 printf("VBE: write index=0x%x val=0x%x\n", s->vbe_index, val);
640#endif
641 switch(s->vbe_index) {
642 case VBE_DISPI_INDEX_ID:
cae61cef
FB		 643 if (val == VBE_DISPI_ID0 ||
644 val == VBE_DISPI_ID1 ||
37dd208d
FB		 645 val == VBE_DISPI_ID2 ||
646 val == VBE_DISPI_ID3 ||
647 val == VBE_DISPI_ID4) {
cae61cef
FB		 648 s->vbe_regs[s->vbe_index] = val;
649 }
4fa0f5d2
FB		 650 break;
651 case VBE_DISPI_INDEX_XRES:
cae61cef
FB		 652 if ((val <= VBE_DISPI_MAX_XRES) && ((val & 7) == 0)) {
653 s->vbe_regs[s->vbe_index] = val;
654 }
4fa0f5d2
FB		 655 break;
656 case VBE_DISPI_INDEX_YRES:
cae61cef
FB		 657 if (val <= VBE_DISPI_MAX_YRES) {
658 s->vbe_regs[s->vbe_index] = val;
659 }
4fa0f5d2
FB		 660 break;
661 case VBE_DISPI_INDEX_BPP:
662 if (val == 0)
663 val = 8;
5fafdf24 664 if (val == 4 || val == 8 || val == 15 ||
cae61cef
FB		 665 val == 16 || val == 24 || val == 32) {
666 s->vbe_regs[s->vbe_index] = val;
667 }
4fa0f5d2
FB		 668 break;
669 case VBE_DISPI_INDEX_BANK:
42fc925e
FB		 670 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) {
671 val &= (s->vbe_bank_mask >> 2);
672 } else {
673 val &= s->vbe_bank_mask;
674 }
cae61cef 675 s->vbe_regs[s->vbe_index] = val;
26aa7d72 676 s->bank_offset = (val << 16);
80763888 677 vga_update_memory_access(s);
4fa0f5d2
FB		 678 break;
679 case VBE_DISPI_INDEX_ENABLE:
8454df8b
FB		 680 if ((val & VBE_DISPI_ENABLED) &&
681 !(s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED)) {
4fa0f5d2
FB		 682 int h, shift_control;
683
5fafdf24 684 s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] =
4fa0f5d2 685 s->vbe_regs[VBE_DISPI_INDEX_XRES];
5fafdf24 686 s->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] =
4fa0f5d2
FB		 687 s->vbe_regs[VBE_DISPI_INDEX_YRES];
688 s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET] = 0;
689 s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET] = 0;
3b46e624 690
4fa0f5d2
FB		 691 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
692 s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 1;
693 else
5fafdf24 694 s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] *
4fa0f5d2
FB		 695 ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
696 s->vbe_start_addr = 0;
8454df8b 697
4fa0f5d2
FB		 698 /* clear the screen (should be done in BIOS) */
699 if (!(val & VBE_DISPI_NOCLEARMEM)) {
5fafdf24 700 memset(s->vram_ptr, 0,
4fa0f5d2
FB		 701 s->vbe_regs[VBE_DISPI_INDEX_YRES] * s->vbe_line_offset);
702 }
3b46e624 703
cae61cef
FB		 704 /* we initialize the VGA graphic mode (should be done
705 in BIOS) */
5e55efc9
BS		 706 /* graphic mode + memory map 1 */
707 s->gr[VGA_GFX_MISC] = (s->gr[VGA_GFX_MISC] & ~0x0c) | 0x04 |
708 VGA_GR06_GRAPHICS_MODE;
709 s->cr[VGA_CRTC_MODE] |= 3; /* no CGA modes */
710 s->cr[VGA_CRTC_OFFSET] = s->vbe_line_offset >> 3;
4fa0f5d2 711 /* width */
5e55efc9
BS		 712 s->cr[VGA_CRTC_H_DISP] =
713 (s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 3) - 1;
8454df8b 714 /* height (only meaningful if < 1024) */
4fa0f5d2 715 h = s->vbe_regs[VBE_DISPI_INDEX_YRES] - 1;
5e55efc9
BS		 716 s->cr[VGA_CRTC_V_DISP_END] = h;
717 s->cr[VGA_CRTC_OVERFLOW] = (s->cr[VGA_CRTC_OVERFLOW] & ~0x42) |
4fa0f5d2
FB		 718 ((h >> 7) & 0x02) | ((h >> 3) & 0x40);
719 /* line compare to 1023 */
5e55efc9
BS		 720 s->cr[VGA_CRTC_LINE_COMPARE] = 0xff;
721 s->cr[VGA_CRTC_OVERFLOW] |= 0x10;
722 s->cr[VGA_CRTC_MAX_SCAN] |= 0x40;
3b46e624 723
4fa0f5d2
FB		 724 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) {
725 shift_control = 0;
5e55efc9 726 s->sr[VGA_SEQ_CLOCK_MODE] &= ~8; /* no double line */
4fa0f5d2
FB		 727 } else {
728 shift_control = 2;
5e55efc9
BS		 729 /* set chain 4 mode */
730 s->sr[VGA_SEQ_MEMORY_MODE] |= VGA_SR04_CHN_4M;
731 /* activate all planes */
732 s->sr[VGA_SEQ_PLANE_WRITE] |= VGA_SR02_ALL_PLANES;
4fa0f5d2 733 }
5e55efc9
BS		 734 s->gr[VGA_GFX_MODE] = (s->gr[VGA_GFX_MODE] & ~0x60) |
735 (shift_control << 5);
736 s->cr[VGA_CRTC_MAX_SCAN] &= ~0x9f; /* no double scan */
cae61cef
FB		 737 } else {
738 /* XXX: the bios should do that */
26aa7d72 739 s->bank_offset = 0;
cae61cef 740 }
37dd208d 741 s->dac_8bit = (val & VBE_DISPI_8BIT_DAC) > 0;
141253b2 742 s->vbe_regs[s->vbe_index] = val;
80763888 743 vga_update_memory_access(s);
cae61cef
FB		 744 break;
745 case VBE_DISPI_INDEX_VIRT_WIDTH:
746 {
747 int w, h, line_offset;
748
749 if (val < s->vbe_regs[VBE_DISPI_INDEX_XRES])
750 return;
751 w = val;
752 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
753 line_offset = w >> 1;
754 else
755 line_offset = w * ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
756 h = s->vram_size / line_offset;
757 /* XXX: support weird bochs semantics ? */
758 if (h < s->vbe_regs[VBE_DISPI_INDEX_YRES])
759 return;
760 s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] = w;
761 s->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] = h;
762 s->vbe_line_offset = line_offset;
763 }
764 break;
765 case VBE_DISPI_INDEX_X_OFFSET:
766 case VBE_DISPI_INDEX_Y_OFFSET:
767 {
768 int x;
769 s->vbe_regs[s->vbe_index] = val;
770 s->vbe_start_addr = s->vbe_line_offset * s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET];
771 x = s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET];
772 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
773 s->vbe_start_addr += x >> 1;
774 else
775 s->vbe_start_addr += x * ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
776 s->vbe_start_addr >>= 2;
4fa0f5d2
FB		 777 }
778 break;
779 default:
780 break;
781 }
4fa0f5d2
FB		 782 }
783}
4fa0f5d2 784
e89f66ec 785/* called for accesses between 0xa0000 and 0xc0000 */
a8170e5e 786uint32_t vga_mem_readb(VGACommonState *s, hwaddr addr)
e89f66ec 787{
e89f66ec
FB		 788 int memory_map_mode, plane;
789 uint32_t ret;
3b46e624 790
e89f66ec 791 /* convert to VGA memory offset */
5e55efc9 792 memory_map_mode = (s->gr[VGA_GFX_MISC] >> 2) & 3;
26aa7d72 793 addr &= 0x1ffff;
e89f66ec
FB		 794 switch(memory_map_mode) {
795 case 0:
e89f66ec
FB		 796 break;
797 case 1:
26aa7d72 798 if (addr >= 0x10000)
e89f66ec 799 return 0xff;
cae61cef 800 addr += s->bank_offset;
e89f66ec
FB		 801 break;
802 case 2:
26aa7d72 803 addr -= 0x10000;
e89f66ec
FB		 804 if (addr >= 0x8000)
805 return 0xff;
806 break;
807 default:
808 case 3:
26aa7d72 809 addr -= 0x18000;
c92b2e84
FB		 810 if (addr >= 0x8000)
811 return 0xff;
e89f66ec
FB		 812 break;
813 }
3b46e624 814
5e55efc9 815 if (s->sr[VGA_SEQ_MEMORY_MODE] & VGA_SR04_CHN_4M) {
e89f66ec
FB		 816 /* chain 4 mode : simplest access */
817 ret = s->vram_ptr[addr];
5e55efc9 818 } else if (s->gr[VGA_GFX_MODE] & 0x10) {
e89f66ec 819 /* odd/even mode (aka text mode mapping) */
5e55efc9 820 plane = (s->gr[VGA_GFX_PLANE_READ] & 2) | (addr & 1);
e89f66ec
FB		 821 ret = s->vram_ptr[((addr & ~1) << 1) | plane];
822 } else {
823 /* standard VGA latched access */
824 s->latch = ((uint32_t *)s->vram_ptr)[addr];
825
5e55efc9 826 if (!(s->gr[VGA_GFX_MODE] & 0x08)) {
e89f66ec 827 /* read mode 0 */
5e55efc9 828 plane = s->gr[VGA_GFX_PLANE_READ];
b8ed223b 829 ret = GET_PLANE(s->latch, plane);
e89f66ec
FB		 830 } else {
831 /* read mode 1 */
5e55efc9
BS		 832 ret = (s->latch ^ mask16[s->gr[VGA_GFX_COMPARE_VALUE]]) &
833 mask16[s->gr[VGA_GFX_COMPARE_MASK]];
e89f66ec
FB		 834 ret |= ret >> 16;
835 ret |= ret >> 8;
836 ret = (~ret) & 0xff;
837 }
838 }
839 return ret;
840}
841
e89f66ec 842/* called for accesses between 0xa0000 and 0xc0000 */
a8170e5e 843void vga_mem_writeb(VGACommonState *s, hwaddr addr, uint32_t val)
e89f66ec 844{
546fa6ab 845 int memory_map_mode, plane, write_mode, b, func_select, mask;
e89f66ec
FB		 846 uint32_t write_mask, bit_mask, set_mask;
847
17b0018b 848#ifdef DEBUG_VGA_MEM
0bf9e31a 849 printf("vga: [0x" TARGET_FMT_plx "] = 0x%02x\n", addr, val);
e89f66ec
FB		 850#endif
851 /* convert to VGA memory offset */
5e55efc9 852 memory_map_mode = (s->gr[VGA_GFX_MISC] >> 2) & 3;
26aa7d72 853 addr &= 0x1ffff;
e89f66ec
FB		 854 switch(memory_map_mode) {
855 case 0:
e89f66ec
FB		 856 break;
857 case 1:
26aa7d72 858 if (addr >= 0x10000)
e89f66ec 859 return;
cae61cef 860 addr += s->bank_offset;
e89f66ec
FB		 861 break;
862 case 2:
26aa7d72 863 addr -= 0x10000;
e89f66ec
FB		 864 if (addr >= 0x8000)
865 return;
866 break;
867 default:
868 case 3:
26aa7d72 869 addr -= 0x18000;
c92b2e84
FB		 870 if (addr >= 0x8000)
871 return;
e89f66ec
FB		 872 break;
873 }
3b46e624 874
5e55efc9 875 if (s->sr[VGA_SEQ_MEMORY_MODE] & VGA_SR04_CHN_4M) {
e89f66ec
FB		 876 /* chain 4 mode : simplest access */
877 plane = addr & 3;
546fa6ab 878 mask = (1 << plane);
5e55efc9 879 if (s->sr[VGA_SEQ_PLANE_WRITE] & mask) {
e89f66ec 880 s->vram_ptr[addr] = val;
17b0018b 881#ifdef DEBUG_VGA_MEM
0bf9e31a 882 printf("vga: chain4: [0x" TARGET_FMT_plx "]\n", addr);
e89f66ec 883#endif
546fa6ab 884 s->plane_updated |= mask; /* only used to detect font change */
fd4aa979 885 memory_region_set_dirty(&s->vram, addr, 1);
e89f66ec 886 }
5e55efc9 887 } else if (s->gr[VGA_GFX_MODE] & 0x10) {
e89f66ec 888 /* odd/even mode (aka text mode mapping) */
5e55efc9 889 plane = (s->gr[VGA_GFX_PLANE_READ] & 2) | (addr & 1);
546fa6ab 890 mask = (1 << plane);
5e55efc9 891 if (s->sr[VGA_SEQ_PLANE_WRITE] & mask) {
e89f66ec
FB		 892 addr = ((addr & ~1) << 1) | plane;
893 s->vram_ptr[addr] = val;
17b0018b 894#ifdef DEBUG_VGA_MEM
0bf9e31a 895 printf("vga: odd/even: [0x" TARGET_FMT_plx "]\n", addr);
e89f66ec 896#endif
546fa6ab 897 s->plane_updated |= mask; /* only used to detect font change */
fd4aa979 898 memory_region_set_dirty(&s->vram, addr, 1);
e89f66ec
FB		 899 }
900 } else {
901 /* standard VGA latched access */
5e55efc9 902 write_mode = s->gr[VGA_GFX_MODE] & 3;
e89f66ec
FB		 903 switch(write_mode) {
904 default:
905 case 0:
906 /* rotate */
5e55efc9 907 b = s->gr[VGA_GFX_DATA_ROTATE] & 7;
e89f66ec
FB		 908 val = ((val >> b) | (val << (8 - b))) & 0xff;
909 val |= val << 8;
910 val |= val << 16;
911
912 /* apply set/reset mask */
5e55efc9
BS		 913 set_mask = mask16[s->gr[VGA_GFX_SR_ENABLE]];
914 val = (val & ~set_mask) |
915 (mask16[s->gr[VGA_GFX_SR_VALUE]] & set_mask);
916 bit_mask = s->gr[VGA_GFX_BIT_MASK];
e89f66ec
FB		 917 break;
918 case 1:
919 val = s->latch;
920 goto do_write;
921 case 2:
922 val = mask16[val & 0x0f];
5e55efc9 923 bit_mask = s->gr[VGA_GFX_BIT_MASK];
e89f66ec
FB		 924 break;
925 case 3:
926 /* rotate */
5e55efc9 927 b = s->gr[VGA_GFX_DATA_ROTATE] & 7;
a41bc9af 928 val = (val >> b) | (val << (8 - b));
e89f66ec 929
5e55efc9
BS		 930 bit_mask = s->gr[VGA_GFX_BIT_MASK] & val;
931 val = mask16[s->gr[VGA_GFX_SR_VALUE]];
e89f66ec
FB		 932 break;
933 }
934
935 /* apply logical operation */
5e55efc9 936 func_select = s->gr[VGA_GFX_DATA_ROTATE] >> 3;
e89f66ec
FB		 937 switch(func_select) {
938 case 0:
939 default:
940 /* nothing to do */
941 break;
942 case 1:
943 /* and */
944 val &= s->latch;
945 break;
946 case 2:
947 /* or */
948 val |= s->latch;
949 break;
950 case 3:
951 /* xor */
952 val ^= s->latch;
953 break;
954 }
955
956 /* apply bit mask */
957 bit_mask |= bit_mask << 8;
958 bit_mask |= bit_mask << 16;
959 val = (val & bit_mask) | (s->latch & ~bit_mask);
960
961 do_write:
962 /* mask data according to sr[2] */
5e55efc9 963 mask = s->sr[VGA_SEQ_PLANE_WRITE];
546fa6ab
FB		 964 s->plane_updated |= mask; /* only used to detect font change */
965 write_mask = mask16[mask];
5fafdf24
TS		 966 ((uint32_t *)s->vram_ptr)[addr] =
967 (((uint32_t *)s->vram_ptr)[addr] & ~write_mask) |
e89f66ec 968 (val & write_mask);
17b0018b 969#ifdef DEBUG_VGA_MEM
0bf9e31a
BS		 970 printf("vga: latch: [0x" TARGET_FMT_plx "] mask=0x%08x val=0x%08x\n",
971 addr * 4, write_mask, val);
e89f66ec 972#endif
fd4aa979 973 memory_region_set_dirty(&s->vram, addr << 2, sizeof(uint32_t));
e89f66ec
FB		 974 }
975}
976
e89f66ec
FB		 977typedef void vga_draw_glyph8_func(uint8_t *d, int linesize,
978 const uint8_t *font_ptr, int h,
979 uint32_t fgcol, uint32_t bgcol);
980typedef void vga_draw_glyph9_func(uint8_t *d, int linesize,
5fafdf24 981 const uint8_t *font_ptr, int h,
e89f66ec 982 uint32_t fgcol, uint32_t bgcol, int dup9);
cedd91d2 983typedef void vga_draw_line_func(VGACommonState *s1, uint8_t *d,
e89f66ec
FB		 984 const uint8_t *s, int width);
985
e89f66ec 986#define DEPTH 8
47b43a1f 987#include "vga_template.h"
e89f66ec
FB		 988
989#define DEPTH 15
47b43a1f 990#include "vga_template.h"
e89f66ec 991
a2502b58
BS		 992#define BGR_FORMAT
993#define DEPTH 15
47b43a1f 994#include "vga_template.h"
a2502b58
BS		 995
996#define DEPTH 16
47b43a1f 997#include "vga_template.h"
a2502b58
BS		 998
999#define BGR_FORMAT
e89f66ec 1000#define DEPTH 16
47b43a1f 1001#include "vga_template.h"
e89f66ec
FB		 1002
1003#define DEPTH 32
47b43a1f 1004#include "vga_template.h"
e89f66ec 1005
d3079cd2
FB		 1006#define BGR_FORMAT
1007#define DEPTH 32
47b43a1f 1008#include "vga_template.h"
d3079cd2 1009
17b0018b
FB		 1010static unsigned int rgb_to_pixel8_dup(unsigned int r, unsigned int g, unsigned b)
1011{
1012 unsigned int col;
1013 col = rgb_to_pixel8(r, g, b);
1014 col |= col << 8;
1015 col |= col << 16;
1016 return col;
1017}
1018
1019static unsigned int rgb_to_pixel15_dup(unsigned int r, unsigned int g, unsigned b)
1020{
1021 unsigned int col;
1022 col = rgb_to_pixel15(r, g, b);
1023 col |= col << 16;
1024 return col;
1025}
1026
b29169d2
BS		 1027static unsigned int rgb_to_pixel15bgr_dup(unsigned int r, unsigned int g,
1028 unsigned int b)
1029{
1030 unsigned int col;
1031 col = rgb_to_pixel15bgr(r, g, b);
1032 col |= col << 16;
1033 return col;
1034}
1035
17b0018b
FB		 1036static unsigned int rgb_to_pixel16_dup(unsigned int r, unsigned int g, unsigned b)
1037{
1038 unsigned int col;
1039 col = rgb_to_pixel16(r, g, b);
1040 col |= col << 16;
1041 return col;
1042}
1043
b29169d2
BS		 1044static unsigned int rgb_to_pixel16bgr_dup(unsigned int r, unsigned int g,
1045 unsigned int b)
1046{
1047 unsigned int col;
1048 col = rgb_to_pixel16bgr(r, g, b);
1049 col |= col << 16;
1050 return col;
1051}
1052
17b0018b
FB		 1053static unsigned int rgb_to_pixel32_dup(unsigned int r, unsigned int g, unsigned b)
1054{
1055 unsigned int col;
1056 col = rgb_to_pixel32(r, g, b);
1057 return col;
1058}
1059
d3079cd2
FB		 1060static unsigned int rgb_to_pixel32bgr_dup(unsigned int r, unsigned int g, unsigned b)
1061{
1062 unsigned int col;
1063 col = rgb_to_pixel32bgr(r, g, b);
1064 return col;
1065}
1066
e89f66ec 1067/* return true if the palette was modified */
cedd91d2 1068static int update_palette16(VGACommonState *s)
e89f66ec 1069{
17b0018b 1070 int full_update, i;
e89f66ec 1071 uint32_t v, col, *palette;
e89f66ec
FB		 1072
1073 full_update = 0;
1074 palette = s->last_palette;
1075 for(i = 0; i < 16; i++) {
1076 v = s->ar[i];
5e55efc9
BS		 1077 if (s->ar[VGA_ATC_MODE] & 0x80) {
1078 v = ((s->ar[VGA_ATC_COLOR_PAGE] & 0xf) << 4) | (v & 0xf);
1079 } else {
1080 v = ((s->ar[VGA_ATC_COLOR_PAGE] & 0xc) << 4) | (v & 0x3f);
1081 }
e89f66ec 1082 v = v * 3;
5fafdf24
TS		 1083 col = s->rgb_to_pixel(c6_to_8(s->palette[v]),
1084 c6_to_8(s->palette[v + 1]),
17b0018b
FB		 1085 c6_to_8(s->palette[v + 2]));
1086 if (col != palette[i]) {
1087 full_update = 1;
1088 palette[i] = col;
e89f66ec 1089 }
17b0018b
FB		 1090 }
1091 return full_update;
1092}
1093
1094/* return true if the palette was modified */
cedd91d2 1095static int update_palette256(VGACommonState *s)
17b0018b
FB		 1096{
1097 int full_update, i;
1098 uint32_t v, col, *palette;
1099
1100 full_update = 0;
1101 palette = s->last_palette;
1102 v = 0;
1103 for(i = 0; i < 256; i++) {
37dd208d 1104 if (s->dac_8bit) {
5fafdf24
TS		 1105 col = s->rgb_to_pixel(s->palette[v],
1106 s->palette[v + 1],
37dd208d
FB		 1107 s->palette[v + 2]);
1108 } else {
5fafdf24
TS		 1109 col = s->rgb_to_pixel(c6_to_8(s->palette[v]),
1110 c6_to_8(s->palette[v + 1]),
37dd208d
FB		 1111 c6_to_8(s->palette[v + 2]));
1112 }
e89f66ec
FB		 1113 if (col != palette[i]) {
1114 full_update = 1;
1115 palette[i] = col;
1116 }
17b0018b 1117 v += 3;
e89f66ec
FB		 1118 }
1119 return full_update;
1120}
1121
cedd91d2 1122static void vga_get_offsets(VGACommonState *s,
5fafdf24 1123 uint32_t *pline_offset,
83acc96b
FB		 1124 uint32_t *pstart_addr,
1125 uint32_t *pline_compare)
e89f66ec 1126{
83acc96b 1127 uint32_t start_addr, line_offset, line_compare;
a96d8bea 1128
4fa0f5d2
FB		 1129 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1130 line_offset = s->vbe_line_offset;
1131 start_addr = s->vbe_start_addr;
83acc96b 1132 line_compare = 65535;
a96d8bea 1133 } else {
4fa0f5d2 1134 /* compute line_offset in bytes */
5e55efc9 1135 line_offset = s->cr[VGA_CRTC_OFFSET];
4fa0f5d2 1136 line_offset <<= 3;
08e48902 1137
4fa0f5d2 1138 /* starting address */
5e55efc9
BS		 1139 start_addr = s->cr[VGA_CRTC_START_LO] |
1140 (s->cr[VGA_CRTC_START_HI] << 8);
83acc96b
FB		 1141
1142 /* line compare */
5e55efc9
BS		 1143 line_compare = s->cr[VGA_CRTC_LINE_COMPARE] |
1144 ((s->cr[VGA_CRTC_OVERFLOW] & 0x10) << 4) |
1145 ((s->cr[VGA_CRTC_MAX_SCAN] & 0x40) << 3);
4fa0f5d2 1146 }
798b0c25
FB		 1147 *pline_offset = line_offset;
1148 *pstart_addr = start_addr;
83acc96b 1149 *pline_compare = line_compare;
798b0c25
FB		 1150}
1151
1152/* update start_addr and line_offset. Return TRUE if modified */
cedd91d2 1153static int update_basic_params(VGACommonState *s)
798b0c25
FB		 1154{
1155 int full_update;
1156 uint32_t start_addr, line_offset, line_compare;
3b46e624 1157
798b0c25
FB		 1158 full_update = 0;
1159
83acc96b 1160 s->get_offsets(s, &line_offset, &start_addr, &line_compare);
e89f66ec
FB		 1161
1162 if (line_offset != s->line_offset ||
1163 start_addr != s->start_addr ||
1164 line_compare != s->line_compare) {
1165 s->line_offset = line_offset;
1166 s->start_addr = start_addr;
1167 s->line_compare = line_compare;
1168 full_update = 1;
1169 }
1170 return full_update;
1171}
1172
b29169d2 1173#define NB_DEPTHS 7
d3079cd2 1174
c78f7137 1175static inline int get_depth_index(DisplaySurface *s)
e89f66ec 1176{
c78f7137 1177 switch (surface_bits_per_pixel(s)) {
e89f66ec
FB		 1178 default:
1179 case 8:
1180 return 0;
1181 case 15:
8927bcfd 1182 return 1;
e89f66ec 1183 case 16:
8927bcfd 1184 return 2;
e89f66ec 1185 case 32:
c78f7137 1186 if (is_surface_bgr(s)) {
7b5d76da 1187 return 4;
c78f7137 1188 } else {
7b5d76da 1189 return 3;
c78f7137 1190 }
e89f66ec
FB		 1191 }
1192}
1193
68f04a3c 1194static vga_draw_glyph8_func * const vga_draw_glyph8_table[NB_DEPTHS] = {
e89f66ec
FB		 1195 vga_draw_glyph8_8,
1196 vga_draw_glyph8_16,
1197 vga_draw_glyph8_16,
1198 vga_draw_glyph8_32,
d3079cd2 1199 vga_draw_glyph8_32,
b29169d2
BS		 1200 vga_draw_glyph8_16,
1201 vga_draw_glyph8_16,
e89f66ec
FB		 1202};
1203
68f04a3c 1204static vga_draw_glyph8_func * const vga_draw_glyph16_table[NB_DEPTHS] = {
17b0018b
FB		 1205 vga_draw_glyph16_8,
1206 vga_draw_glyph16_16,
1207 vga_draw_glyph16_16,
1208 vga_draw_glyph16_32,
d3079cd2 1209 vga_draw_glyph16_32,
b29169d2
BS		 1210 vga_draw_glyph16_16,
1211 vga_draw_glyph16_16,
17b0018b
FB		 1212};
1213
68f04a3c 1214static vga_draw_glyph9_func * const vga_draw_glyph9_table[NB_DEPTHS] = {
e89f66ec
FB		 1215 vga_draw_glyph9_8,
1216 vga_draw_glyph9_16,
1217 vga_draw_glyph9_16,
1218 vga_draw_glyph9_32,
d3079cd2 1219 vga_draw_glyph9_32,
b29169d2
BS		 1220 vga_draw_glyph9_16,
1221 vga_draw_glyph9_16,
e89f66ec 1222};
3b46e624 1223
e89f66ec
FB		 1224static const uint8_t cursor_glyph[32 * 4] = {
1225 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1226 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1227 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1228 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1229 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1230 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1231 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1232 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1233 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1234 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1235 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1236 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1237 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1238 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1239 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1240 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
3b46e624 1241};
e89f66ec 1242
cedd91d2 1243static void vga_get_text_resolution(VGACommonState *s, int *pwidth, int *pheight,
4c5e8c5c
BS		 1244 int *pcwidth, int *pcheight)
1245{
1246 int width, cwidth, height, cheight;
1247
1248 /* total width & height */
5e55efc9 1249 cheight = (s->cr[VGA_CRTC_MAX_SCAN] & 0x1f) + 1;
4c5e8c5c 1250 cwidth = 8;
5e55efc9 1251 if (!(s->sr[VGA_SEQ_CLOCK_MODE] & VGA_SR01_CHAR_CLK_8DOTS)) {
4c5e8c5c 1252 cwidth = 9;
5e55efc9
BS		 1253 }
1254 if (s->sr[VGA_SEQ_CLOCK_MODE] & 0x08) {
4c5e8c5c 1255 cwidth = 16; /* NOTE: no 18 pixel wide */
5e55efc9
BS		 1256 }
1257 width = (s->cr[VGA_CRTC_H_DISP] + 1);
1258 if (s->cr[VGA_CRTC_V_TOTAL] == 100) {
4c5e8c5c
BS		 1259 /* ugly hack for CGA 160x100x16 - explain me the logic */
1260 height = 100;
1261 } else {
5e55efc9
BS		 1262 height = s->cr[VGA_CRTC_V_DISP_END] |
1263 ((s->cr[VGA_CRTC_OVERFLOW] & 0x02) << 7) |
1264 ((s->cr[VGA_CRTC_OVERFLOW] & 0x40) << 3);
4c5e8c5c
BS		 1265 height = (height + 1) / cheight;
1266 }
1267
1268 *pwidth = width;
1269 *pheight = height;
1270 *pcwidth = cwidth;
1271 *pcheight = cheight;
1272}
1273
7d957bd8
AL		 1274typedef unsigned int rgb_to_pixel_dup_func(unsigned int r, unsigned int g, unsigned b);
1275
68f04a3c 1276static rgb_to_pixel_dup_func * const rgb_to_pixel_dup_table[NB_DEPTHS] = {
bdb19571
AL		 1277 rgb_to_pixel8_dup,
1278 rgb_to_pixel15_dup,
1279 rgb_to_pixel16_dup,
1280 rgb_to_pixel32_dup,
1281 rgb_to_pixel32bgr_dup,
1282 rgb_to_pixel15bgr_dup,
1283 rgb_to_pixel16bgr_dup,
1284};
7d957bd8 1285
5fafdf24
TS		 1286/*
1287 * Text mode update
e89f66ec
FB		 1288 * Missing:
1289 * - double scan
5fafdf24 1290 * - double width
e89f66ec
FB		 1291 * - underline
1292 * - flashing
1293 */
cedd91d2 1294static void vga_draw_text(VGACommonState *s, int full_update)
e89f66ec 1295{
c78f7137 1296 DisplaySurface *surface = qemu_console_surface(s->con);
e89f66ec 1297 int cx, cy, cheight, cw, ch, cattr, height, width, ch_attr;
cae334cd 1298 int cx_min, cx_max, linesize, x_incr, line, line1;
e89f66ec 1299 uint32_t offset, fgcol, bgcol, v, cursor_offset;
d1984194 1300 uint8_t *d1, *d, *src, *dest, *cursor_ptr;
e89f66ec
FB		 1301 const uint8_t *font_ptr, *font_base[2];
1302 int dup9, line_offset, depth_index;
1303 uint32_t *palette;
1304 uint32_t *ch_attr_ptr;
1305 vga_draw_glyph8_func *vga_draw_glyph8;
1306 vga_draw_glyph9_func *vga_draw_glyph9;
9aa0ff0b 1307 int64_t now = qemu_get_clock_ms(vm_clock);
e89f66ec 1308
e89f66ec 1309 /* compute font data address (in plane 2) */
5e55efc9 1310 v = s->sr[VGA_SEQ_CHARACTER_MAP];
1078f663 1311 offset = (((v >> 4) & 1) | ((v << 1) & 6)) * 8192 * 4 + 2;
e89f66ec
FB		 1312 if (offset != s->font_offsets[0]) {
1313 s->font_offsets[0] = offset;
1314 full_update = 1;
1315 }
1316 font_base[0] = s->vram_ptr + offset;
1317
1078f663 1318 offset = (((v >> 5) & 1) | ((v >> 1) & 6)) * 8192 * 4 + 2;
e89f66ec
FB		 1319 font_base[1] = s->vram_ptr + offset;
1320 if (offset != s->font_offsets[1]) {
1321 s->font_offsets[1] = offset;
1322 full_update = 1;
1323 }
80763888 1324 if (s->plane_updated & (1 << 2) || s->chain4_alias) {
546fa6ab
FB		 1325 /* if the plane 2 was modified since the last display, it
1326 indicates the font may have been modified */
1327 s->plane_updated = 0;
1328 full_update = 1;
1329 }
799e709b 1330 full_update |= update_basic_params(s);
e89f66ec
FB		 1331
1332 line_offset = s->line_offset;
e89f66ec 1333
4c5e8c5c 1334 vga_get_text_resolution(s, &width, &height, &cw, &cheight);
1b296044
SW		 1335 if ((height * width) <= 1) {
1336 /* better than nothing: exit if transient size is too small */
1337 return;
1338 }
3294b949
FB		 1339 if ((height * width) > CH_ATTR_SIZE) {
1340 /* better than nothing: exit if transient size is too big */
1341 return;
1342 }
1343
799e709b
AL		 1344 if (width != s->last_width || height != s->last_height ||
1345 cw != s->last_cw || cheight != s->last_ch || s->last_depth) {
1346 s->last_scr_width = width * cw;
1347 s->last_scr_height = height * cheight;
c78f7137
GH		 1348 qemu_console_resize(s->con, s->last_scr_width, s->last_scr_height);
1349 surface = qemu_console_surface(s->con);
1350 dpy_text_resize(s->con, width, height);
799e709b
AL		 1351 s->last_depth = 0;
1352 s->last_width = width;
1353 s->last_height = height;
1354 s->last_ch = cheight;
1355 s->last_cw = cw;
1356 full_update = 1;
1357 }
7d957bd8 1358 s->rgb_to_pixel =
c78f7137 1359 rgb_to_pixel_dup_table[get_depth_index(surface)];
7d957bd8
AL		 1360 full_update |= update_palette16(s);
1361 palette = s->last_palette;
c78f7137 1362 x_incr = cw * surface_bytes_per_pixel(surface);
7d957bd8 1363
9678aedd
GH		 1364 if (full_update) {
1365 s->full_update_text = 1;
1366 }
1367 if (s->full_update_gfx) {
1368 s->full_update_gfx = 0;
1369 full_update |= 1;
1370 }
1371
5e55efc9
BS		 1372 cursor_offset = ((s->cr[VGA_CRTC_CURSOR_HI] << 8) |
1373 s->cr[VGA_CRTC_CURSOR_LO]) - s->start_addr;
e89f66ec 1374 if (cursor_offset != s->cursor_offset ||
5e55efc9
BS		 1375 s->cr[VGA_CRTC_CURSOR_START] != s->cursor_start ||
1376 s->cr[VGA_CRTC_CURSOR_END] != s->cursor_end) {
e89f66ec
FB		 1377 /* if the cursor position changed, we update the old and new
1378 chars */
1379 if (s->cursor_offset < CH_ATTR_SIZE)
1380 s->last_ch_attr[s->cursor_offset] = -1;
1381 if (cursor_offset < CH_ATTR_SIZE)
1382 s->last_ch_attr[cursor_offset] = -1;
1383 s->cursor_offset = cursor_offset;
5e55efc9
BS		 1384 s->cursor_start = s->cr[VGA_CRTC_CURSOR_START];
1385 s->cursor_end = s->cr[VGA_CRTC_CURSOR_END];
e89f66ec 1386 }
39cf7803 1387 cursor_ptr = s->vram_ptr + (s->start_addr + cursor_offset) * 4;
9aa0ff0b
JK		 1388 if (now >= s->cursor_blink_time) {
1389 s->cursor_blink_time = now + VGA_TEXT_CURSOR_PERIOD_MS / 2;
1390 s->cursor_visible_phase = !s->cursor_visible_phase;
1391 }
3b46e624 1392
c78f7137 1393 depth_index = get_depth_index(surface);
17b0018b
FB		 1394 if (cw == 16)
1395 vga_draw_glyph8 = vga_draw_glyph16_table[depth_index];
1396 else
1397 vga_draw_glyph8 = vga_draw_glyph8_table[depth_index];
e89f66ec 1398 vga_draw_glyph9 = vga_draw_glyph9_table[depth_index];
3b46e624 1399
c78f7137
GH		 1400 dest = surface_data(surface);
1401 linesize = surface_stride(surface);
e89f66ec 1402 ch_attr_ptr = s->last_ch_attr;
d1984194 1403 line = 0;
1404 offset = s->start_addr * 4;
e89f66ec
FB		 1405 for(cy = 0; cy < height; cy++) {
1406 d1 = dest;
d1984194 1407 src = s->vram_ptr + offset;
e89f66ec
FB		 1408 cx_min = width;
1409 cx_max = -1;
1410 for(cx = 0; cx < width; cx++) {
1411 ch_attr = *(uint16_t *)src;
9aa0ff0b 1412 if (full_update || ch_attr != *ch_attr_ptr || src == cursor_ptr) {
e89f66ec
FB		 1413 if (cx < cx_min)
1414 cx_min = cx;
1415 if (cx > cx_max)
1416 cx_max = cx;
1417 *ch_attr_ptr = ch_attr;
e2542fe2 1418#ifdef HOST_WORDS_BIGENDIAN
e89f66ec
FB		 1419 ch = ch_attr >> 8;
1420 cattr = ch_attr & 0xff;
1421#else
1422 ch = ch_attr & 0xff;
1423 cattr = ch_attr >> 8;
1424#endif
1425 font_ptr = font_base[(cattr >> 3) & 1];
1426 font_ptr += 32 * 4 * ch;
1427 bgcol = palette[cattr >> 4];
1428 fgcol = palette[cattr & 0x0f];
17b0018b 1429 if (cw != 9) {
5fafdf24 1430 vga_draw_glyph8(d1, linesize,
e89f66ec
FB		 1431 font_ptr, cheight, fgcol, bgcol);
1432 } else {
1433 dup9 = 0;
5e55efc9
BS		 1434 if (ch >= 0xb0 && ch <= 0xdf &&
1435 (s->ar[VGA_ATC_MODE] & 0x04)) {
e89f66ec 1436 dup9 = 1;
5e55efc9 1437 }
5fafdf24 1438 vga_draw_glyph9(d1, linesize,
e89f66ec
FB		 1439 font_ptr, cheight, fgcol, bgcol, dup9);
1440 }
1441 if (src == cursor_ptr &&
9aa0ff0b
JK		 1442 !(s->cr[VGA_CRTC_CURSOR_START] & 0x20) &&
1443 s->cursor_visible_phase) {
e89f66ec
FB		 1444 int line_start, line_last, h;
1445 /* draw the cursor */
5e55efc9
BS		 1446 line_start = s->cr[VGA_CRTC_CURSOR_START] & 0x1f;
1447 line_last = s->cr[VGA_CRTC_CURSOR_END] & 0x1f;
e89f66ec
FB		 1448 /* XXX: check that */
1449 if (line_last > cheight - 1)
1450 line_last = cheight - 1;
1451 if (line_last >= line_start && line_start < cheight) {
1452 h = line_last - line_start + 1;
1453 d = d1 + linesize * line_start;
17b0018b 1454 if (cw != 9) {
5fafdf24 1455 vga_draw_glyph8(d, linesize,
e89f66ec
FB		 1456 cursor_glyph, h, fgcol, bgcol);
1457 } else {
5fafdf24 1458 vga_draw_glyph9(d, linesize,
e89f66ec
FB		 1459 cursor_glyph, h, fgcol, bgcol, 1);
1460 }
1461 }
1462 }
1463 }
1464 d1 += x_incr;
1465 src += 4;
1466 ch_attr_ptr++;
1467 }
1468 if (cx_max != -1) {
c78f7137 1469 dpy_gfx_update(s->con, cx_min * cw, cy * cheight,
a93a4a22 1470 (cx_max - cx_min + 1) * cw, cheight);
e89f66ec
FB		 1471 }
1472 dest += linesize * cheight;
cae334cd 1473 line1 = line + cheight;
1474 offset += line_offset;
1475 if (line < s->line_compare && line1 >= s->line_compare) {
d1984194 1476 offset = 0;
1477 }
cae334cd 1478 line = line1;
e89f66ec
FB		 1479 }
1480}
1481
17b0018b
FB		 1482enum {
1483 VGA_DRAW_LINE2,
1484 VGA_DRAW_LINE2D2,
1485 VGA_DRAW_LINE4,
1486 VGA_DRAW_LINE4D2,
1487 VGA_DRAW_LINE8D2,
1488 VGA_DRAW_LINE8,
1489 VGA_DRAW_LINE15,
1490 VGA_DRAW_LINE16,
4fa0f5d2 1491 VGA_DRAW_LINE24,
17b0018b
FB		 1492 VGA_DRAW_LINE32,
1493 VGA_DRAW_LINE_NB,
1494};
1495
68f04a3c 1496static vga_draw_line_func * const vga_draw_line_table[NB_DEPTHS * VGA_DRAW_LINE_NB] = {
e89f66ec
FB		 1497 vga_draw_line2_8,
1498 vga_draw_line2_16,
1499 vga_draw_line2_16,
1500 vga_draw_line2_32,
d3079cd2 1501 vga_draw_line2_32,
b29169d2
BS		 1502 vga_draw_line2_16,
1503 vga_draw_line2_16,
e89f66ec 1504
17b0018b
FB		 1505 vga_draw_line2d2_8,
1506 vga_draw_line2d2_16,
1507 vga_draw_line2d2_16,
1508 vga_draw_line2d2_32,
d3079cd2 1509 vga_draw_line2d2_32,
b29169d2
BS		 1510 vga_draw_line2d2_16,
1511 vga_draw_line2d2_16,
17b0018b 1512
e89f66ec
FB		 1513 vga_draw_line4_8,
1514 vga_draw_line4_16,
1515 vga_draw_line4_16,
1516 vga_draw_line4_32,
d3079cd2 1517 vga_draw_line4_32,
b29169d2
BS		 1518 vga_draw_line4_16,
1519 vga_draw_line4_16,
e89f66ec 1520
17b0018b
FB		 1521 vga_draw_line4d2_8,
1522 vga_draw_line4d2_16,
1523 vga_draw_line4d2_16,
1524 vga_draw_line4d2_32,
d3079cd2 1525 vga_draw_line4d2_32,
b29169d2
BS		 1526 vga_draw_line4d2_16,
1527 vga_draw_line4d2_16,
17b0018b
FB		 1528
1529 vga_draw_line8d2_8,
1530 vga_draw_line8d2_16,
1531 vga_draw_line8d2_16,
1532 vga_draw_line8d2_32,
d3079cd2 1533 vga_draw_line8d2_32,
b29169d2
BS		 1534 vga_draw_line8d2_16,
1535 vga_draw_line8d2_16,
17b0018b 1536
e89f66ec
FB		 1537 vga_draw_line8_8,
1538 vga_draw_line8_16,
1539 vga_draw_line8_16,
1540 vga_draw_line8_32,
d3079cd2 1541 vga_draw_line8_32,
b29169d2
BS		 1542 vga_draw_line8_16,
1543 vga_draw_line8_16,
e89f66ec
FB		 1544
1545 vga_draw_line15_8,
1546 vga_draw_line15_15,
1547 vga_draw_line15_16,
1548 vga_draw_line15_32,
d3079cd2 1549 vga_draw_line15_32bgr,
b29169d2
BS		 1550 vga_draw_line15_15bgr,
1551 vga_draw_line15_16bgr,
e89f66ec
FB		 1552
1553 vga_draw_line16_8,
1554 vga_draw_line16_15,
1555 vga_draw_line16_16,
1556 vga_draw_line16_32,
d3079cd2 1557 vga_draw_line16_32bgr,
b29169d2
BS		 1558 vga_draw_line16_15bgr,
1559 vga_draw_line16_16bgr,
e89f66ec 1560
4fa0f5d2
FB		 1561 vga_draw_line24_8,
1562 vga_draw_line24_15,
1563 vga_draw_line24_16,
1564 vga_draw_line24_32,
d3079cd2 1565 vga_draw_line24_32bgr,
b29169d2
BS		 1566 vga_draw_line24_15bgr,
1567 vga_draw_line24_16bgr,
4fa0f5d2 1568
e89f66ec
FB		 1569 vga_draw_line32_8,
1570 vga_draw_line32_15,
1571 vga_draw_line32_16,
1572 vga_draw_line32_32,
d3079cd2 1573 vga_draw_line32_32bgr,
b29169d2
BS		 1574 vga_draw_line32_15bgr,
1575 vga_draw_line32_16bgr,
d3079cd2
FB		 1576};
1577
cedd91d2 1578static int vga_get_bpp(VGACommonState *s)
798b0c25
FB		 1579{
1580 int ret;
a96d8bea 1581
798b0c25
FB		 1582 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1583 ret = s->vbe_regs[VBE_DISPI_INDEX_BPP];
a96d8bea 1584 } else {
798b0c25
FB		 1585 ret = 0;
1586 }
1587 return ret;
1588}
1589
cedd91d2 1590static void vga_get_resolution(VGACommonState *s, int *pwidth, int *pheight)
a130a41e
FB		 1591{
1592 int width, height;
3b46e624 1593
8454df8b
FB		 1594 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1595 width = s->vbe_regs[VBE_DISPI_INDEX_XRES];
1596 height = s->vbe_regs[VBE_DISPI_INDEX_YRES];
a96d8bea 1597 } else {
5e55efc9
BS		 1598 width = (s->cr[VGA_CRTC_H_DISP] + 1) * 8;
1599 height = s->cr[VGA_CRTC_V_DISP_END] |
1600 ((s->cr[VGA_CRTC_OVERFLOW] & 0x02) << 7) |
1601 ((s->cr[VGA_CRTC_OVERFLOW] & 0x40) << 3);
8454df8b
FB		 1602 height = (height + 1);
1603 }
a130a41e
FB		 1604 *pwidth = width;
1605 *pheight = height;
1606}
1607
cedd91d2 1608void vga_invalidate_scanlines(VGACommonState *s, int y1, int y2)
a8aa669b
FB		 1609{
1610 int y;
1611 if (y1 >= VGA_MAX_HEIGHT)
1612 return;
1613 if (y2 >= VGA_MAX_HEIGHT)
1614 y2 = VGA_MAX_HEIGHT;
1615 for(y = y1; y < y2; y++) {
1616 s->invalidated_y_table[y >> 5] |= 1 << (y & 0x1f);
1617 }
1618}
1619
b51d7b2e 1620void vga_sync_dirty_bitmap(VGACommonState *s)
2bec46dc 1621{
b1950430 1622 memory_region_sync_dirty_bitmap(&s->vram);
2bec46dc
AL		 1623}
1624
50af3246
JQ		 1625void vga_dirty_log_start(VGACommonState *s)
1626{
b1950430 1627 memory_region_set_log(&s->vram, true, DIRTY_MEMORY_VGA);
b5cc6e32
AL		 1628}
1629
1630void vga_dirty_log_stop(VGACommonState *s)
1631{
b1950430 1632 memory_region_set_log(&s->vram, false, DIRTY_MEMORY_VGA);
b5cc6e32
AL		 1633}
1634
799e709b
AL		 1635/*
1636 * graphic modes
1637 */
cedd91d2 1638static void vga_draw_graphic(VGACommonState *s, int full_update)
e89f66ec 1639{
c78f7137 1640 DisplaySurface *surface = qemu_console_surface(s->con);
12c7e75a
AK		 1641 int y1, y, update, linesize, y_start, double_scan, mask, depth;
1642 int width, height, shift_control, line_offset, bwidth, bits;
c227f099 1643 ram_addr_t page0, page1, page_min, page_max;
a07cf92a 1644 int disp_width, multi_scan, multi_run;
799e709b
AL		 1645 uint8_t *d;
1646 uint32_t v, addr1, addr;
1647 vga_draw_line_func *vga_draw_line;
b1424e03
GH		 1648#if defined(HOST_WORDS_BIGENDIAN) == defined(TARGET_WORDS_BIGENDIAN)
1649 static const bool byteswap = false;
1650#else
1651 static const bool byteswap = true;
1652#endif
799e709b
AL		 1653
1654 full_update |= update_basic_params(s);
1655
1656 if (!full_update)
1657 vga_sync_dirty_bitmap(s);
2bec46dc 1658
a130a41e 1659 s->get_resolution(s, &width, &height);
17b0018b 1660 disp_width = width;
09a79b49 1661
5e55efc9
BS		 1662 shift_control = (s->gr[VGA_GFX_MODE] >> 5) & 3;
1663 double_scan = (s->cr[VGA_CRTC_MAX_SCAN] >> 7);
799e709b 1664 if (shift_control != 1) {
5e55efc9
BS		 1665 multi_scan = (((s->cr[VGA_CRTC_MAX_SCAN] & 0x1f) + 1) << double_scan)
1666 - 1;
799e709b
AL		 1667 } else {
1668 /* in CGA modes, multi_scan is ignored */
1669 /* XXX: is it correct ? */
1670 multi_scan = double_scan;
1671 }
1672 multi_run = multi_scan;
17b0018b
FB		 1673 if (shift_control != s->shift_control ||
1674 double_scan != s->double_scan) {
799e709b 1675 full_update = 1;
e89f66ec 1676 s->shift_control = shift_control;
17b0018b 1677 s->double_scan = double_scan;
e89f66ec 1678 }
3b46e624 1679
aba35a6c 1680 if (shift_control == 0) {
5e55efc9 1681 if (s->sr[VGA_SEQ_CLOCK_MODE] & 8) {
aba35a6c 1682 disp_width <<= 1;
1683 }
1684 } else if (shift_control == 1) {
5e55efc9 1685 if (s->sr[VGA_SEQ_CLOCK_MODE] & 8) {
aba35a6c 1686 disp_width <<= 1;
1687 }
1688 }
1689
799e709b 1690 depth = s->get_bpp(s);
e3697092
AJ		 1691 if (s->line_offset != s->last_line_offset ||
1692 disp_width != s->last_width ||
1693 height != s->last_height ||
799e709b 1694 s->last_depth != depth) {
b1424e03 1695 if (depth == 32 || (depth == 16 && !byteswap)) {
da229ef3
GH		 1696 surface = qemu_create_displaysurface_from(disp_width,
1697 height, depth, s->line_offset,
b1424e03 1698 s->vram_ptr + (s->start_addr * 4), byteswap);
c78f7137 1699 dpy_gfx_replace_surface(s->con, surface);
e3697092 1700 } else {
c78f7137
GH		 1701 qemu_console_resize(s->con, disp_width, height);
1702 surface = qemu_console_surface(s->con);
e3697092
AJ		 1703 }
1704 s->last_scr_width = disp_width;
1705 s->last_scr_height = height;
1706 s->last_width = disp_width;
1707 s->last_height = height;
1708 s->last_line_offset = s->line_offset;
1709 s->last_depth = depth;
799e709b 1710 full_update = 1;
c78f7137
GH		 1711 } else if (is_buffer_shared(surface) &&
1712 (full_update || surface_data(surface) != s->vram_ptr
1fd2510a 1713 + (s->start_addr * 4))) {
da229ef3
GH		 1714 DisplaySurface *surface;
1715 surface = qemu_create_displaysurface_from(disp_width,
1716 height, depth, s->line_offset,
b1424e03 1717 s->vram_ptr + (s->start_addr * 4), byteswap);
c78f7137 1718 dpy_gfx_replace_surface(s->con, surface);
e3697092
AJ		 1719 }
1720
1721 s->rgb_to_pixel =
c78f7137 1722 rgb_to_pixel_dup_table[get_depth_index(surface)];
e3697092 1723
799e709b 1724 if (shift_control == 0) {
17b0018b 1725 full_update |= update_palette16(s);
5e55efc9 1726 if (s->sr[VGA_SEQ_CLOCK_MODE] & 8) {
17b0018b 1727 v = VGA_DRAW_LINE4D2;
17b0018b
FB		 1728 } else {
1729 v = VGA_DRAW_LINE4;
1730 }
15342721 1731 bits = 4;
799e709b 1732 } else if (shift_control == 1) {
17b0018b 1733 full_update |= update_palette16(s);
5e55efc9 1734 if (s->sr[VGA_SEQ_CLOCK_MODE] & 8) {
17b0018b 1735 v = VGA_DRAW_LINE2D2;
17b0018b
FB		 1736 } else {
1737 v = VGA_DRAW_LINE2;
1738 }
15342721 1739 bits = 4;
17b0018b 1740 } else {
798b0c25
FB		 1741 switch(s->get_bpp(s)) {
1742 default:
1743 case 0:
4fa0f5d2
FB		 1744 full_update |= update_palette256(s);
1745 v = VGA_DRAW_LINE8D2;
15342721 1746 bits = 4;
798b0c25
FB		 1747 break;
1748 case 8:
1749 full_update |= update_palette256(s);
1750 v = VGA_DRAW_LINE8;
15342721 1751 bits = 8;
798b0c25
FB		 1752 break;
1753 case 15:
1754 v = VGA_DRAW_LINE15;
15342721 1755 bits = 16;
798b0c25
FB		 1756 break;
1757 case 16:
1758 v = VGA_DRAW_LINE16;
15342721 1759 bits = 16;
798b0c25
FB		 1760 break;
1761 case 24:
1762 v = VGA_DRAW_LINE24;
15342721 1763 bits = 24;
798b0c25
FB		 1764 break;
1765 case 32:
1766 v = VGA_DRAW_LINE32;
15342721 1767 bits = 32;
798b0c25 1768 break;
4fa0f5d2 1769 }
17b0018b 1770 }
c78f7137
GH		 1771 vga_draw_line = vga_draw_line_table[v * NB_DEPTHS +
1772 get_depth_index(surface)];
17b0018b 1773
c78f7137 1774 if (!is_buffer_shared(surface) && s->cursor_invalidate) {
a8aa669b 1775 s->cursor_invalidate(s);
c78f7137 1776 }
3b46e624 1777
e89f66ec 1778 line_offset = s->line_offset;
17b0018b 1779#if 0
f6c958c8 1780 printf("w=%d h=%d v=%d line_offset=%d cr[0x09]=0x%02x cr[0x17]=0x%02x linecmp=%d sr[0x01]=0x%02x\n",
5e55efc9
BS		 1781 width, height, v, line_offset, s->cr[9], s->cr[VGA_CRTC_MODE],
1782 s->line_compare, s->sr[VGA_SEQ_CLOCK_MODE]);
17b0018b 1783#endif
e89f66ec 1784 addr1 = (s->start_addr * 4);
15342721 1785 bwidth = (width * bits + 7) / 8;
39cf7803 1786 y_start = -1;
12c7e75a
AK		 1787 page_min = -1;
1788 page_max = 0;
c78f7137
GH		 1789 d = surface_data(surface);
1790 linesize = surface_stride(surface);
17b0018b 1791 y1 = 0;
e89f66ec
FB		 1792 for(y = 0; y < height; y++) {
1793 addr = addr1;
5e55efc9 1794 if (!(s->cr[VGA_CRTC_MODE] & 1)) {
17b0018b 1795 int shift;
e89f66ec 1796 /* CGA compatibility handling */
5e55efc9 1797 shift = 14 + ((s->cr[VGA_CRTC_MODE] >> 6) & 1);
17b0018b 1798 addr = (addr & ~(1 << shift)) | ((y1 & 1) << shift);
e89f66ec 1799 }
5e55efc9 1800 if (!(s->cr[VGA_CRTC_MODE] & 2)) {
17b0018b 1801 addr = (addr & ~0x8000) | ((y1 & 2) << 14);
e89f66ec 1802 }
734781c9 1803 update = full_update;
cd7a45c9
BS		 1804 page0 = addr;
1805 page1 = addr + bwidth - 1;
734781c9
JK		 1806 update |= memory_region_get_dirty(&s->vram, page0, page1 - page0,
1807 DIRTY_MEMORY_VGA);
a8aa669b
FB		 1808 /* explicit invalidation for the hardware cursor */
1809 update |= (s->invalidated_y_table[y >> 5] >> (y & 0x1f)) & 1;
e89f66ec 1810 if (update) {
39cf7803
FB		 1811 if (y_start < 0)
1812 y_start = y;
e89f66ec
FB		 1813 if (page0 < page_min)
1814 page_min = page0;
1815 if (page1 > page_max)
1816 page_max = page1;
c78f7137 1817 if (!(is_buffer_shared(surface))) {
7d957bd8
AL		 1818 vga_draw_line(s, d, s->vram_ptr + addr, width);
1819 if (s->cursor_draw_line)
1820 s->cursor_draw_line(s, d, y);
1821 }
39cf7803
FB		 1822 } else {
1823 if (y_start >= 0) {
1824 /* flush to display */
c78f7137 1825 dpy_gfx_update(s->con, 0, y_start,
a93a4a22 1826 disp_width, y - y_start);
39cf7803
FB		 1827 y_start = -1;
1828 }
e89f66ec 1829 }
a07cf92a 1830 if (!multi_run) {
5e55efc9 1831 mask = (s->cr[VGA_CRTC_MODE] & 3) ^ 3;
f6c958c8
FB		 1832 if ((y1 & mask) == mask)
1833 addr1 += line_offset;
1834 y1++;
799e709b 1835 multi_run = multi_scan;
a07cf92a
FB		 1836 } else {
1837 multi_run--;
e89f66ec 1838 }
f6c958c8
FB		 1839 /* line compare acts on the displayed lines */
1840 if (y == s->line_compare)
1841 addr1 = 0;
e89f66ec
FB		 1842 d += linesize;
1843 }
39cf7803
FB		 1844 if (y_start >= 0) {
1845 /* flush to display */
c78f7137 1846 dpy_gfx_update(s->con, 0, y_start,
a93a4a22 1847 disp_width, y - y_start);
39cf7803 1848 }
e89f66ec 1849 /* reset modified pages */
12c7e75a 1850 if (page_max >= page_min) {
b1950430
AK		 1851 memory_region_reset_dirty(&s->vram,
1852 page_min,
cd7a45c9 1853 page_max - page_min,
b1950430 1854 DIRTY_MEMORY_VGA);
e89f66ec 1855 }
a8aa669b 1856 memset(s->invalidated_y_table, 0, ((height + 31) >> 5) * 4);
e89f66ec
FB		 1857}
1858
cedd91d2 1859static void vga_draw_blank(VGACommonState *s, int full_update)
2aebb3eb 1860{
c78f7137 1861 DisplaySurface *surface = qemu_console_surface(s->con);
2aebb3eb
FB		 1862 int i, w, val;
1863 uint8_t *d;
1864
1865 if (!full_update)
1866 return;
1867 if (s->last_scr_width <= 0 || s->last_scr_height <= 0)
1868 return;
2bec46dc 1869
7d957bd8 1870 s->rgb_to_pixel =
c78f7137
GH		 1871 rgb_to_pixel_dup_table[get_depth_index(surface)];
1872 if (surface_bits_per_pixel(surface) == 8) {
2aebb3eb 1873 val = s->rgb_to_pixel(0, 0, 0);
c78f7137 1874 } else {
2aebb3eb 1875 val = 0;
c78f7137
GH		 1876 }
1877 w = s->last_scr_width * surface_bytes_per_pixel(surface);
1878 d = surface_data(surface);
2aebb3eb
FB		 1879 for(i = 0; i < s->last_scr_height; i++) {
1880 memset(d, val, w);
c78f7137 1881 d += surface_stride(surface);
2aebb3eb 1882 }
c78f7137 1883 dpy_gfx_update(s->con, 0, 0,
a93a4a22 1884 s->last_scr_width, s->last_scr_height);
2aebb3eb
FB		 1885}
1886
799e709b
AL		 1887#define GMODE_TEXT 0
1888#define GMODE_GRAPH 1
1889#define GMODE_BLANK 2
1890
95219897 1891static void vga_update_display(void *opaque)
e89f66ec 1892{
cedd91d2 1893 VGACommonState *s = opaque;
c78f7137 1894 DisplaySurface *surface = qemu_console_surface(s->con);
799e709b 1895 int full_update, graphic_mode;
e89f66ec 1896
e9a07334
JK		 1897 qemu_flush_coalesced_mmio_buffer();
1898
c78f7137 1899 if (surface_bits_per_pixel(surface) == 0) {
0f35920c 1900 /* nothing to do */
59a983b9 1901 } else {
3098b9fd 1902 full_update = 0;
df800210 1903 if (!(s->ar_index & 0x20)) {
799e709b
AL		 1904 graphic_mode = GMODE_BLANK;
1905 } else {
5e55efc9 1906 graphic_mode = s->gr[VGA_GFX_MISC] & VGA_GR06_GRAPHICS_MODE;
799e709b
AL		 1907 }
1908 if (graphic_mode != s->graphic_mode) {
1909 s->graphic_mode = graphic_mode;
9aa0ff0b 1910 s->cursor_blink_time = qemu_get_clock_ms(vm_clock);
799e709b
AL		 1911 full_update = 1;
1912 }
1913 switch(graphic_mode) {
2aebb3eb 1914 case GMODE_TEXT:
e89f66ec 1915 vga_draw_text(s, full_update);
2aebb3eb
FB		 1916 break;
1917 case GMODE_GRAPH:
1918 vga_draw_graphic(s, full_update);
1919 break;
1920 case GMODE_BLANK:
1921 default:
1922 vga_draw_blank(s, full_update);
1923 break;
1924 }
e89f66ec
FB		 1925 }
1926}
1927
a130a41e 1928/* force a full display refresh */
95219897 1929static void vga_invalidate_display(void *opaque)
a130a41e 1930{
cedd91d2 1931 VGACommonState *s = opaque;
3b46e624 1932
3098b9fd
AJ		 1933 s->last_width = -1;
1934 s->last_height = -1;
a130a41e
FB		 1935}
1936
03a3e7ba 1937void vga_common_reset(VGACommonState *s)
e89f66ec 1938{
6e6b7363
BS		 1939 s->sr_index = 0;
1940 memset(s->sr, '\0', sizeof(s->sr));
1941 s->gr_index = 0;
1942 memset(s->gr, '\0', sizeof(s->gr));
1943 s->ar_index = 0;
1944 memset(s->ar, '\0', sizeof(s->ar));
1945 s->ar_flip_flop = 0;
1946 s->cr_index = 0;
1947 memset(s->cr, '\0', sizeof(s->cr));
1948 s->msr = 0;
1949 s->fcr = 0;
1950 s->st00 = 0;
1951 s->st01 = 0;
1952 s->dac_state = 0;
1953 s->dac_sub_index = 0;
1954 s->dac_read_index = 0;
1955 s->dac_write_index = 0;
1956 memset(s->dac_cache, '\0', sizeof(s->dac_cache));
1957 s->dac_8bit = 0;
1958 memset(s->palette, '\0', sizeof(s->palette));
1959 s->bank_offset = 0;
6e6b7363
BS		 1960 s->vbe_index = 0;
1961 memset(s->vbe_regs, '\0', sizeof(s->vbe_regs));
af92284b 1962 s->vbe_regs[VBE_DISPI_INDEX_ID] = VBE_DISPI_ID5;
6e6b7363
BS		 1963 s->vbe_start_addr = 0;
1964 s->vbe_line_offset = 0;
1965 s->vbe_bank_mask = (s->vram_size >> 16) - 1;
6e6b7363 1966 memset(s->font_offsets, '\0', sizeof(s->font_offsets));
799e709b 1967 s->graphic_mode = -1; /* force full update */
6e6b7363
BS		 1968 s->shift_control = 0;
1969 s->double_scan = 0;
1970 s->line_offset = 0;
1971 s->line_compare = 0;
1972 s->start_addr = 0;
1973 s->plane_updated = 0;
1974 s->last_cw = 0;
1975 s->last_ch = 0;
1976 s->last_width = 0;
1977 s->last_height = 0;
1978 s->last_scr_width = 0;
1979 s->last_scr_height = 0;
1980 s->cursor_start = 0;
1981 s->cursor_end = 0;
1982 s->cursor_offset = 0;
1983 memset(s->invalidated_y_table, '\0', sizeof(s->invalidated_y_table));
1984 memset(s->last_palette, '\0', sizeof(s->last_palette));
1985 memset(s->last_ch_attr, '\0', sizeof(s->last_ch_attr));
1986 switch (vga_retrace_method) {
1987 case VGA_RETRACE_DUMB:
1988 break;
1989 case VGA_RETRACE_PRECISE:
1990 memset(&s->retrace_info, 0, sizeof (s->retrace_info));
1991 break;
1992 }
80763888 1993 vga_update_memory_access(s);
e89f66ec
FB		 1994}
1995
03a3e7ba
JQ		 1996static void vga_reset(void *opaque)
1997{
cedd91d2 1998 VGACommonState *s = opaque;
03a3e7ba
JQ		 1999 vga_common_reset(s);
2000}
2001
4d3b6f6e
AZ		 2002#define TEXTMODE_X(x) ((x) % width)
2003#define TEXTMODE_Y(x) ((x) / width)
2004#define VMEM2CHTYPE(v) ((v & 0xff0007ff) | \
2005 ((v & 0x00000800) << 10) | ((v & 0x00007000) >> 1))
2006/* relay text rendering to the display driver
2007 * instead of doing a full vga_update_display() */
c227f099 2008static void vga_update_text(void *opaque, console_ch_t *chardata)
4d3b6f6e 2009{
cedd91d2 2010 VGACommonState *s = opaque;
799e709b 2011 int graphic_mode, i, cursor_offset, cursor_visible;
4d3b6f6e
AZ		 2012 int cw, cheight, width, height, size, c_min, c_max;
2013 uint32_t *src;
c227f099 2014 console_ch_t *dst, val;
4d3b6f6e 2015 char msg_buffer[80];
799e709b
AL		 2016 int full_update = 0;
2017
e9a07334
JK		 2018 qemu_flush_coalesced_mmio_buffer();
2019
799e709b
AL		 2020 if (!(s->ar_index & 0x20)) {
2021 graphic_mode = GMODE_BLANK;
2022 } else {
5e55efc9 2023 graphic_mode = s->gr[VGA_GFX_MISC] & VGA_GR06_GRAPHICS_MODE;
799e709b
AL		 2024 }
2025 if (graphic_mode != s->graphic_mode) {
2026 s->graphic_mode = graphic_mode;
2027 full_update = 1;
2028 }
2029 if (s->last_width == -1) {
2030 s->last_width = 0;
2031 full_update = 1;
2032 }
4d3b6f6e 2033
799e709b 2034 switch (graphic_mode) {
4d3b6f6e
AZ		 2035 case GMODE_TEXT:
2036 /* TODO: update palette */
799e709b 2037 full_update |= update_basic_params(s);
4d3b6f6e 2038
799e709b 2039 /* total width & height */
5e55efc9 2040 cheight = (s->cr[VGA_CRTC_MAX_SCAN] & 0x1f) + 1;
799e709b 2041 cw = 8;
5e55efc9 2042 if (!(s->sr[VGA_SEQ_CLOCK_MODE] & VGA_SR01_CHAR_CLK_8DOTS)) {
799e709b 2043 cw = 9;
5e55efc9
BS		 2044 }
2045 if (s->sr[VGA_SEQ_CLOCK_MODE] & 0x08) {
799e709b 2046 cw = 16; /* NOTE: no 18 pixel wide */
5e55efc9
BS		 2047 }
2048 width = (s->cr[VGA_CRTC_H_DISP] + 1);
2049 if (s->cr[VGA_CRTC_V_TOTAL] == 100) {
799e709b
AL		 2050 /* ugly hack for CGA 160x100x16 - explain me the logic */
2051 height = 100;
2052 } else {
5e55efc9
BS		 2053 height = s->cr[VGA_CRTC_V_DISP_END] |
2054 ((s->cr[VGA_CRTC_OVERFLOW] & 0x02) << 7) |
2055 ((s->cr[VGA_CRTC_OVERFLOW] & 0x40) << 3);
799e709b 2056 height = (height + 1) / cheight;
4d3b6f6e
AZ		 2057 }
2058
2059 size = (height * width);
2060 if (size > CH_ATTR_SIZE) {
2061 if (!full_update)
2062 return;
2063
363a37d5
BS		 2064 snprintf(msg_buffer, sizeof(msg_buffer), "%i x %i Text mode",
2065 width, height);
4d3b6f6e
AZ		 2066 break;
2067 }
2068
799e709b
AL		 2069 if (width != s->last_width || height != s->last_height ||
2070 cw != s->last_cw || cheight != s->last_ch) {
2071 s->last_scr_width = width * cw;
2072 s->last_scr_height = height * cheight;
c78f7137
GH		 2073 qemu_console_resize(s->con, s->last_scr_width, s->last_scr_height);
2074 dpy_text_resize(s->con, width, height);
9678aedd 2075 s->last_depth = 0;
799e709b
AL		 2076 s->last_width = width;
2077 s->last_height = height;
2078 s->last_ch = cheight;
2079 s->last_cw = cw;
2080 full_update = 1;
2081 }
2082
9678aedd
GH		 2083 if (full_update) {
2084 s->full_update_gfx = 1;
2085 }
2086 if (s->full_update_text) {
2087 s->full_update_text = 0;
2088 full_update |= 1;
2089 }
2090
4d3b6f6e 2091 /* Update "hardware" cursor */
5e55efc9
BS		 2092 cursor_offset = ((s->cr[VGA_CRTC_CURSOR_HI] << 8) |
2093 s->cr[VGA_CRTC_CURSOR_LO]) - s->start_addr;
4d3b6f6e 2094 if (cursor_offset != s->cursor_offset ||
5e55efc9
BS		 2095 s->cr[VGA_CRTC_CURSOR_START] != s->cursor_start ||
2096 s->cr[VGA_CRTC_CURSOR_END] != s->cursor_end || full_update) {
2097 cursor_visible = !(s->cr[VGA_CRTC_CURSOR_START] & 0x20);
4d3b6f6e 2098 if (cursor_visible && cursor_offset < size && cursor_offset >= 0)
c78f7137 2099 dpy_text_cursor(s->con,
bf2fde70
GH		 2100 TEXTMODE_X(cursor_offset),
2101 TEXTMODE_Y(cursor_offset));
4d3b6f6e 2102 else
c78f7137 2103 dpy_text_cursor(s->con, -1, -1);
4d3b6f6e 2104 s->cursor_offset = cursor_offset;
5e55efc9
BS		 2105 s->cursor_start = s->cr[VGA_CRTC_CURSOR_START];
2106 s->cursor_end = s->cr[VGA_CRTC_CURSOR_END];
4d3b6f6e
AZ		 2107 }
2108
2109 src = (uint32_t *) s->vram_ptr + s->start_addr;
2110 dst = chardata;
2111
2112 if (full_update) {
2113 for (i = 0; i < size; src ++, dst ++, i ++)
9ae19b65 2114 console_write_ch(dst, VMEM2CHTYPE(le32_to_cpu(*src)));
4d3b6f6e 2115
c78f7137 2116 dpy_text_update(s->con, 0, 0, width, height);
4d3b6f6e
AZ		 2117 } else {
2118 c_max = 0;
2119
2120 for (i = 0; i < size; src ++, dst ++, i ++) {
9ae19b65 2121 console_write_ch(&val, VMEM2CHTYPE(le32_to_cpu(*src)));
4d3b6f6e
AZ		 2122 if (*dst != val) {
2123 *dst = val;
2124 c_max = i;
2125 break;
2126 }
2127 }
2128 c_min = i;
2129 for (; i < size; src ++, dst ++, i ++) {
9ae19b65 2130 console_write_ch(&val, VMEM2CHTYPE(le32_to_cpu(*src)));
4d3b6f6e
AZ		 2131 if (*dst != val) {
2132 *dst = val;
2133 c_max = i;
2134 }
2135 }
2136
2137 if (c_min <= c_max) {
2138 i = TEXTMODE_Y(c_min);
c78f7137 2139 dpy_text_update(s->con, 0, i, width, TEXTMODE_Y(c_max) - i + 1);
4d3b6f6e
AZ		 2140 }
2141 }
2142
2143 return;
2144 case GMODE_GRAPH:
2145 if (!full_update)
2146 return;
2147
2148 s->get_resolution(s, &width, &height);
363a37d5
BS		 2149 snprintf(msg_buffer, sizeof(msg_buffer), "%i x %i Graphic mode",
2150 width, height);
4d3b6f6e
AZ		 2151 break;
2152 case GMODE_BLANK:
2153 default:
2154 if (!full_update)
2155 return;
2156
363a37d5 2157 snprintf(msg_buffer, sizeof(msg_buffer), "VGA Blank mode");
4d3b6f6e
AZ		 2158 break;
2159 }
2160
2161 /* Display a message */
5228c2d3
AZ		 2162 s->last_width = 60;
2163 s->last_height = height = 3;
c78f7137
GH		 2164 dpy_text_cursor(s->con, -1, -1);
2165 dpy_text_resize(s->con, s->last_width, height);
4d3b6f6e 2166
5228c2d3 2167 for (dst = chardata, i = 0; i < s->last_width * height; i ++)
4d3b6f6e
AZ		 2168 console_write_ch(dst ++, ' ');
2169
2170 size = strlen(msg_buffer);
5228c2d3
AZ		 2171 width = (s->last_width - size) / 2;
2172 dst = chardata + s->last_width + width;
4d3b6f6e
AZ		 2173 for (i = 0; i < size; i ++)
2174 console_write_ch(dst ++, 0x00200100 | msg_buffer[i]);
2175
c78f7137 2176 dpy_text_update(s->con, 0, 0, s->last_width, height);
4d3b6f6e
AZ		 2177}
2178
a8170e5e 2179static uint64_t vga_mem_read(void *opaque, hwaddr addr,
b1950430
AK		 2180 unsigned size)
2181{
2182 VGACommonState *s = opaque;
2183
b2a5e761 2184 return vga_mem_readb(s, addr);
b1950430 2185}
e89f66ec 2186
a8170e5e 2187static void vga_mem_write(void *opaque, hwaddr addr,
b1950430
AK		 2188 uint64_t data, unsigned size)
2189{
2190 VGACommonState *s = opaque;
2191
b2a5e761 2192 return vga_mem_writeb(s, addr, data);
b1950430
AK		 2193}
2194
2195const MemoryRegionOps vga_mem_ops = {
2196 .read = vga_mem_read,
2197 .write = vga_mem_write,
2198 .endianness = DEVICE_LITTLE_ENDIAN,
b2a5e761
AK		 2199 .impl = {
2200 .min_access_size = 1,
2201 .max_access_size = 1,
2202 },
e89f66ec
FB		 2203};
2204
11b6b345 2205static int vga_common_post_load(void *opaque, int version_id)
b0a21b53 2206{
0d65ddc3 2207 VGACommonState *s = opaque;
11b6b345
JQ		 2208
2209 /* force refresh */
2210 s->graphic_mode = -1;
2211 return 0;
2212}
2213
2214const VMStateDescription vmstate_vga_common = {
2215 .name = "vga",
2216 .version_id = 2,
2217 .minimum_version_id = 2,
2218 .minimum_version_id_old = 2,
2219 .post_load = vga_common_post_load,
2220 .fields = (VMStateField []) {
2221 VMSTATE_UINT32(latch, VGACommonState),
2222 VMSTATE_UINT8(sr_index, VGACommonState),
2223 VMSTATE_PARTIAL_BUFFER(sr, VGACommonState, 8),
2224 VMSTATE_UINT8(gr_index, VGACommonState),
2225 VMSTATE_PARTIAL_BUFFER(gr, VGACommonState, 16),
2226 VMSTATE_UINT8(ar_index, VGACommonState),
2227 VMSTATE_BUFFER(ar, VGACommonState),
2228 VMSTATE_INT32(ar_flip_flop, VGACommonState),
2229 VMSTATE_UINT8(cr_index, VGACommonState),
2230 VMSTATE_BUFFER(cr, VGACommonState),
2231 VMSTATE_UINT8(msr, VGACommonState),
2232 VMSTATE_UINT8(fcr, VGACommonState),
2233 VMSTATE_UINT8(st00, VGACommonState),
2234 VMSTATE_UINT8(st01, VGACommonState),
2235
2236 VMSTATE_UINT8(dac_state, VGACommonState),
2237 VMSTATE_UINT8(dac_sub_index, VGACommonState),
2238 VMSTATE_UINT8(dac_read_index, VGACommonState),
2239 VMSTATE_UINT8(dac_write_index, VGACommonState),
2240 VMSTATE_BUFFER(dac_cache, VGACommonState),
2241 VMSTATE_BUFFER(palette, VGACommonState),
2242
2243 VMSTATE_INT32(bank_offset, VGACommonState),
2244 VMSTATE_UINT8_EQUAL(is_vbe_vmstate, VGACommonState),
11b6b345
JQ		 2245 VMSTATE_UINT16(vbe_index, VGACommonState),
2246 VMSTATE_UINT16_ARRAY(vbe_regs, VGACommonState, VBE_DISPI_INDEX_NB),
2247 VMSTATE_UINT32(vbe_start_addr, VGACommonState),
2248 VMSTATE_UINT32(vbe_line_offset, VGACommonState),
2249 VMSTATE_UINT32(vbe_bank_mask, VGACommonState),
11b6b345
JQ		 2250 VMSTATE_END_OF_LIST()
2251 }
2252};
2253
380cd056
GH		 2254static const GraphicHwOps vga_ops = {
2255 .invalidate = vga_invalidate_display,
2256 .gfx_update = vga_update_display,
2257 .text_update = vga_update_text,
2258};
2259
270327fe 2260void vga_common_init(VGACommonState *s, Object *obj)
e89f66ec 2261{
17b0018b 2262 int i, j, v, b;
e89f66ec
FB		 2263
2264 for(i = 0;i < 256; i++) {
2265 v = 0;
2266 for(j = 0; j < 8; j++) {
2267 v |= ((i >> j) & 1) << (j * 4);
2268 }
2269 expand4[i] = v;
2270
2271 v = 0;
2272 for(j = 0; j < 4; j++) {
2273 v |= ((i >> (2 * j)) & 3) << (j * 4);
2274 }
2275 expand2[i] = v;
2276 }
17b0018b
FB		 2277 for(i = 0; i < 16; i++) {
2278 v = 0;
2279 for(j = 0; j < 4; j++) {
2280 b = ((i >> j) & 1);
2281 v |= b << (2 * j);
2282 v |= b << (2 * j + 1);
2283 }
2284 expand4to8[i] = v;
2285 }
e89f66ec 2286
4a1e244e
GH		 2287 /* valid range: 1 MB -> 256 MB */
2288 s->vram_size = 1024 * 1024;
2289 while (s->vram_size < (s->vram_size_mb << 20) &&
2290 s->vram_size < (256 << 20)) {
2291 s->vram_size <<= 1;
2292 }
2293 s->vram_size_mb = s->vram_size >> 20;
2294
2a3138ab 2295 s->is_vbe_vmstate = 1;
270327fe 2296 memory_region_init_ram(&s->vram, obj, "vga.vram", s->vram_size);
c5705a77 2297 vmstate_register_ram_global(&s->vram);
c65adf9b 2298 xen_register_framebuffer(&s->vram);
b1950430 2299 s->vram_ptr = memory_region_get_ram_ptr(&s->vram);
798b0c25
FB		 2300 s->get_bpp = vga_get_bpp;
2301 s->get_offsets = vga_get_offsets;
a130a41e 2302 s->get_resolution = vga_get_resolution;
380cd056 2303 s->hw_ops = &vga_ops;
cb5a7aa8 2304 switch (vga_retrace_method) {
2305 case VGA_RETRACE_DUMB:
2306 s->retrace = vga_dumb_retrace;
2307 s->update_retrace_info = vga_dumb_update_retrace_info;
2308 break;
2309
2310 case VGA_RETRACE_PRECISE:
2311 s->retrace = vga_precise_retrace;
2312 s->update_retrace_info = vga_precise_update_retrace_info;
cb5a7aa8 2313 break;
2314 }
b1950430 2315 vga_dirty_log_start(s);
798b0c25
FB		 2316}
2317
0a039dc7
RH		 2318static const MemoryRegionPortio vga_portio_list[] = {
2319 { 0x04, 2, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3b4 */
2320 { 0x0a, 1, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3ba */
2321 { 0x10, 16, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3c0 */
2322 { 0x24, 2, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3d4 */
2323 { 0x2a, 1, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3da */
2324 PORTIO_END_OF_LIST(),
2325};
e89f66ec 2326
0a039dc7
RH		 2327static const MemoryRegionPortio vbe_portio_list[] = {
2328 { 0, 1, 2, .read = vbe_ioport_read_index, .write = vbe_ioport_write_index },
2329# ifdef TARGET_I386
2330 { 1, 1, 2, .read = vbe_ioport_read_data, .write = vbe_ioport_write_data },
0a039dc7 2331# endif
df9ffb72 2332 { 2, 1, 2, .read = vbe_ioport_read_data, .write = vbe_ioport_write_data },
0a039dc7
RH		 2333 PORTIO_END_OF_LIST(),
2334};
4fa0f5d2 2335
0a039dc7 2336/* Used by both ISA and PCI */
c84b28ee 2337MemoryRegion *vga_init_io(VGACommonState *s, Object *obj,
0a039dc7
RH		 2338 const MemoryRegionPortio **vga_ports,
2339 const MemoryRegionPortio **vbe_ports)
2340{
2341 MemoryRegion *vga_mem;
09a79b49 2342
0a039dc7 2343 *vga_ports = vga_portio_list;
0a039dc7 2344 *vbe_ports = vbe_portio_list;
4fa0f5d2 2345
7267c094 2346 vga_mem = g_malloc(sizeof(*vga_mem));
c84b28ee 2347 memory_region_init_io(vga_mem, obj, &vga_mem_ops, s,
b1950430 2348 "vga-lowmem", 0x20000);
bd8f2f5d 2349 memory_region_set_flush_coalesced(vga_mem);
b1950430
AK		 2350
2351 return vga_mem;
7435b791
BS		 2352}
2353
712f0cc7 2354void vga_init(VGACommonState *s, Object *obj, MemoryRegion *address_space,
0a039dc7 2355 MemoryRegion *address_space_io, bool init_vga_ports)
7435b791 2356{
b1950430 2357 MemoryRegion *vga_io_memory;
0a039dc7
RH		 2358 const MemoryRegionPortio *vga_ports, *vbe_ports;
2359 PortioList *vga_port_list = g_new(PortioList, 1);
2360 PortioList *vbe_port_list = g_new(PortioList, 1);
7435b791
BS		 2361
2362 qemu_register_reset(vga_reset, s);
2363
2364 s->bank_offset = 0;
2365
80763888
JK		 2366 s->legacy_address_space = address_space;
2367
c84b28ee 2368 vga_io_memory = vga_init_io(s, obj, &vga_ports, &vbe_ports);
be20f9e9 2369 memory_region_add_subregion_overlap(address_space,
b1950430
AK		 2370 isa_mem_base + 0x000a0000,
2371 vga_io_memory,
2372 1);
2373 memory_region_set_coalescing(vga_io_memory);
0a039dc7
RH		 2374 if (init_vga_ports) {
2375 portio_list_init(vga_port_list, vga_ports, s, "vga");
2376 portio_list_add(vga_port_list, address_space_io, 0x3b0);
2377 }
2378 if (vbe_ports) {
2379 portio_list_init(vbe_port_list, vbe_ports, s, "vbe");
2380 portio_list_add(vbe_port_list, address_space_io, 0x1ce);
2381 }
d2269f6f
FB		 2382}
2383
83118327 2384void vga_init_vbe(VGACommonState *s, Object *obj, MemoryRegion *system_memory)
f0138a63 2385{
8294a64d
AK		 2386 /* With pc-0.12 and below we map both the PCI BAR and the fixed VBE region,
2387 * so use an alias to avoid double-mapping the same region.
2388 */
83118327 2389 memory_region_init_alias(&s->vram_vbe, obj, "vram.vbe",
8294a64d 2390 &s->vram, 0, memory_region_size(&s->vram));
f0138a63 2391 /* XXX: use optimized standard vga accesses */
be20f9e9 2392 memory_region_add_subregion(system_memory,
b1950430 2393 VBE_DISPI_LFB_PHYSICAL_ADDRESS,
8294a64d 2394 &s->vram_vbe);
f0138a63 2395 s->vbe_mapped = 1;
f0138a63 2396}
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