projects / qemu.git / blame
| Commit | Line | Data |
|---|---|---|
| 2a6a4076 MA |
1 | #ifndef QEMU_MIPS_DEFS_H |
| 2 | #define QEMU_MIPS_DEFS_H | |
| 6af0bf9c | 3 | |
| 6af0bf9c FB |
4 | /* If we want to use host float regs... */ |
| 5 | //#define USE_HOST_FLOAT_REGS | |
| 6 | ||
| e9c71dd1 | 7 | /* Real pages are variable size... */ |
| 6af0bf9c | 8 | #define TARGET_PAGE_BITS 12 |
| 814b9a47 | 9 | #define MIPS_TLB_MAX 128 |
| 6af0bf9c | 10 | |
| d26bc211 | 11 | #if defined(TARGET_MIPS64) |
| c570fd16 | 12 | #define TARGET_LONG_BITS 64 |
| e117f526 | 13 | #define TARGET_PHYS_ADDR_SPACE_BITS 48 |
| 4dc89b78 | 14 | #define TARGET_VIRT_ADDR_SPACE_BITS 48 |
| c570fd16 TS |
15 | #else |
| 16 | #define TARGET_LONG_BITS 32 | |
| e117f526 | 17 | #define TARGET_PHYS_ADDR_SPACE_BITS 40 |
| 30724e75 | 18 | #define TARGET_VIRT_ADDR_SPACE_BITS 32 |
| c570fd16 TS |
19 | #endif |
| 20 | ||
| e189e748 TS |
21 | /* Masks used to mark instructions to indicate which ISA level they |
| 22 | were introduced in. */ | |
| 23 | #define ISA_MIPS1 0x00000001 | |
| 24 | #define ISA_MIPS2 0x00000002 | |
| 25 | #define ISA_MIPS3 0x00000004 | |
| 26 | #define ISA_MIPS4 0x00000008 | |
| 27 | #define ISA_MIPS5 0x00000010 | |
| 28 | #define ISA_MIPS32 0x00000020 | |
| 29 | #define ISA_MIPS32R2 0x00000040 | |
| 30 | #define ISA_MIPS64 0x00000080 | |
| 31 | #define ISA_MIPS64R2 0x00000100 | |
| e527526d | 32 | #define ISA_MIPS32R3 0x00000200 |
| fa0d2f69 LA |
33 | #define ISA_MIPS64R3 0x00000400 |
| 34 | #define ISA_MIPS32R5 0x00000800 | |
| 35 | #define ISA_MIPS64R5 0x00001000 | |
| 36 | #define ISA_MIPS32R6 0x00002000 | |
| 37 | #define ISA_MIPS64R6 0x00004000 | |
| e189e748 | 38 | |
| e9c71dd1 | 39 | /* MIPS ASEs. */ |
| fa0d2f69 LA |
40 | #define ASE_MIPS16 0x00010000 |
| 41 | #define ASE_MIPS3D 0x00020000 | |
| 42 | #define ASE_MDMX 0x00040000 | |
| 43 | #define ASE_DSP 0x00080000 | |
| 44 | #define ASE_DSPR2 0x00100000 | |
| 45 | #define ASE_MT 0x00200000 | |
| 46 | #define ASE_SMARTMIPS 0x00400000 | |
| 47 | #define ASE_MICROMIPS 0x00800000 | |
| e97a391d | 48 | #define ASE_MSA 0x01000000 |
| e189e748 | 49 | |
| e9c71dd1 | 50 | /* Chip specific instructions. */ |
| 5bc6fba8 HC |
51 | #define INSN_LOONGSON2E 0x20000000 |
| 52 | #define INSN_LOONGSON2F 0x40000000 | |
| e9c71dd1 | 53 | #define INSN_VR54XX 0x80000000 |
| e189e748 | 54 | |
| e9c71dd1 | 55 | /* MIPS CPU defines. */ |
| e189e748 TS |
56 | #define CPU_MIPS1 (ISA_MIPS1) |
| 57 | #define CPU_MIPS2 (CPU_MIPS1 | ISA_MIPS2) | |
| 58 | #define CPU_MIPS3 (CPU_MIPS2 | ISA_MIPS3) | |
| 59 | #define CPU_MIPS4 (CPU_MIPS3 | ISA_MIPS4) | |
| e9c71dd1 | 60 | #define CPU_VR54XX (CPU_MIPS4 | INSN_VR54XX) |
| 5bc6fba8 HC |
61 | #define CPU_LOONGSON2E (CPU_MIPS3 | INSN_LOONGSON2E) |
| 62 | #define CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F) | |
| e9c71dd1 | 63 | |
| e189e748 TS |
64 | #define CPU_MIPS5 (CPU_MIPS4 | ISA_MIPS5) |
| 65 | ||
| e9c71dd1 | 66 | /* MIPS Technologies "Release 1" */ |
| e189e748 TS |
67 | #define CPU_MIPS32 (CPU_MIPS2 | ISA_MIPS32) |
| 68 | #define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32 | ISA_MIPS64) | |
| 69 | ||
| e9c71dd1 | 70 | /* MIPS Technologies "Release 2" */ |
| e189e748 TS |
71 | #define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS32R2) |
| 72 | #define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2) | |
| 73 | ||
| e527526d PJ |
74 | /* MIPS Technologies "Release 3" */ |
| 75 | #define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3) | |
| fa0d2f69 | 76 | #define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3 | ISA_MIPS64R3) |
| e527526d PJ |
77 | |
| 78 | /* MIPS Technologies "Release 5" */ | |
| 79 | #define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS32R5) | |
| fa0d2f69 LA |
80 | #define CPU_MIPS64R5 (CPU_MIPS64R3 | CPU_MIPS32R5 | ISA_MIPS64R5) |
| 81 | ||
| 82 | /* MIPS Technologies "Release 6" */ | |
| 83 | #define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS32R6) | |
| 84 | #define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6 | ISA_MIPS64R6) | |
| e527526d | 85 | |
| 19221bda TS |
86 | /* Strictly follow the architecture standard: |
| 87 | - Disallow "special" instruction handling for PMON/SPIM. | |
| 88 | Note that we still maintain Count/Compare to match the host clock. */ | |
| b48cfdff TS |
89 | //#define MIPS_STRICT_STANDARD 1 |
| 90 | ||
| 2a6a4076 | 91 | #endif /* QEMU_MIPS_DEFS_H */ |