[qemu.git] / hw / pxa2xx_dma.c

/*
 * Intel XScale PXA255/270 DMA controller.
 *
 * Copyright (c) 2006 Openedhand Ltd.
 * Copyright (c) 2006 Thorsten Zitterell
 * Written by Andrzej Zaborowski <[email protected]>
 *
 * This code is licensed under the GPL.
 */

#include "hw.h"
#include "pxa.h"
#include "sysbus.h"

#define PXA255_DMA_NUM_CHANNELS 16
#define PXA27X_DMA_NUM_CHANNELS 32

#define PXA2XX_DMA_NUM_REQUESTS 75

typedef struct {
    target_phys_addr_t descr;
    target_phys_addr_t src;
    target_phys_addr_t dest;
    uint32_t cmd;
    uint32_t state;
    int request;
} PXA2xxDMAChannel;

typedef struct PXA2xxDMAState {
    SysBusDevice busdev;
    qemu_irq irq;

    uint32_t stopintr;
    uint32_t eorintr;
    uint32_t rasintr;
    uint32_t startintr;
    uint32_t endintr;

    uint32_t align;
    uint32_t pio;

    int channels;
    PXA2xxDMAChannel *chan;

    uint8_t req[PXA2XX_DMA_NUM_REQUESTS];

    /* Flag to avoid recursive DMA invocations.  */
    int running;
} PXA2xxDMAState;

#define DCSR0	0x0000	/* DMA Control / Status register for Channel 0 */
#define DCSR31	0x007c	/* DMA Control / Status register for Channel 31 */
#define DALGN	0x00a0	/* DMA Alignment register */
#define DPCSR	0x00a4	/* DMA Programmed I/O Control Status register */
#define DRQSR0	0x00e0	/* DMA DREQ<0> Status register */
#define DRQSR1	0x00e4	/* DMA DREQ<1> Status register */
#define DRQSR2	0x00e8	/* DMA DREQ<2> Status register */
#define DINT	0x00f0	/* DMA Interrupt register */
#define DRCMR0	0x0100	/* Request to Channel Map register 0 */
#define DRCMR63	0x01fc	/* Request to Channel Map register 63 */
#define D_CH0	0x0200	/* Channel 0 Descriptor start */
#define DRCMR64	0x1100	/* Request to Channel Map register 64 */
#define DRCMR74	0x1128	/* Request to Channel Map register 74 */

/* Per-channel register */
#define DDADR	0x00
#define DSADR	0x01
#define DTADR	0x02
#define DCMD	0x03

/* Bit-field masks */
#define DRCMR_CHLNUM		0x1f
#define DRCMR_MAPVLD		(1 << 7)
#define DDADR_STOP		(1 << 0)
#define DDADR_BREN		(1 << 1)
#define DCMD_LEN		0x1fff
#define DCMD_WIDTH(x)		(1 << ((((x) >> 14) & 3) - 1))
#define DCMD_SIZE(x)		(4 << (((x) >> 16) & 3))
#define DCMD_FLYBYT		(1 << 19)
#define DCMD_FLYBYS		(1 << 20)
#define DCMD_ENDIRQEN		(1 << 21)
#define DCMD_STARTIRQEN		(1 << 22)
#define DCMD_CMPEN		(1 << 25)
#define DCMD_FLOWTRG		(1 << 28)
#define DCMD_FLOWSRC		(1 << 29)
#define DCMD_INCTRGADDR		(1 << 30)
#define DCMD_INCSRCADDR		(1 << 31)
#define DCSR_BUSERRINTR		(1 << 0)
#define DCSR_STARTINTR		(1 << 1)
#define DCSR_ENDINTR		(1 << 2)
#define DCSR_STOPINTR		(1 << 3)
#define DCSR_RASINTR		(1 << 4)
#define DCSR_REQPEND		(1 << 8)
#define DCSR_EORINT		(1 << 9)
#define DCSR_CMPST		(1 << 10)
#define DCSR_MASKRUN		(1 << 22)
#define DCSR_RASIRQEN		(1 << 23)
#define DCSR_CLRCMPST		(1 << 24)
#define DCSR_SETCMPST		(1 << 25)
#define DCSR_EORSTOPEN		(1 << 26)
#define DCSR_EORJMPEN		(1 << 27)
#define DCSR_EORIRQEN		(1 << 28)
#define DCSR_STOPIRQEN		(1 << 29)
#define DCSR_NODESCFETCH	(1 << 30)
#define DCSR_RUN		(1 << 31)

static inline void pxa2xx_dma_update(PXA2xxDMAState *s, int ch)
{
    if (ch >= 0) {
        if ((s->chan[ch].state & DCSR_STOPIRQEN) &&
                (s->chan[ch].state & DCSR_STOPINTR))
            s->stopintr |= 1 << ch;
        else
            s->stopintr &= ~(1 << ch);

        if ((s->chan[ch].state & DCSR_EORIRQEN) &&
                (s->chan[ch].state & DCSR_EORINT))
            s->eorintr |= 1 << ch;
        else
            s->eorintr &= ~(1 << ch);

        if ((s->chan[ch].state & DCSR_RASIRQEN) &&
                (s->chan[ch].state & DCSR_RASINTR))
            s->rasintr |= 1 << ch;
        else
            s->rasintr &= ~(1 << ch);

        if (s->chan[ch].state & DCSR_STARTINTR)
            s->startintr |= 1 << ch;
        else
            s->startintr &= ~(1 << ch);

        if (s->chan[ch].state & DCSR_ENDINTR)
            s->endintr |= 1 << ch;
        else
            s->endintr &= ~(1 << ch);
    }

    if (s->stopintr | s->eorintr | s->rasintr | s->startintr | s->endintr)
        qemu_irq_raise(s->irq);
    else
        qemu_irq_lower(s->irq);
}

static inline void pxa2xx_dma_descriptor_fetch(
                PXA2xxDMAState *s, int ch)
{
    uint32_t desc[4];
    target_phys_addr_t daddr = s->chan[ch].descr & ~0xf;
    if ((s->chan[ch].descr & DDADR_BREN) && (s->chan[ch].state & DCSR_CMPST))
        daddr += 32;

    cpu_physical_memory_read(daddr, (uint8_t *) desc, 16);
    s->chan[ch].descr = desc[DDADR];
    s->chan[ch].src = desc[DSADR];
    s->chan[ch].dest = desc[DTADR];
    s->chan[ch].cmd = desc[DCMD];

    if (s->chan[ch].cmd & DCMD_FLOWSRC)
        s->chan[ch].src &= ~3;
    if (s->chan[ch].cmd & DCMD_FLOWTRG)
        s->chan[ch].dest &= ~3;

    if (s->chan[ch].cmd & (DCMD_CMPEN | DCMD_FLYBYS | DCMD_FLYBYT))
        printf("%s: unsupported mode in channel %i\n", __FUNCTION__, ch);

    if (s->chan[ch].cmd & DCMD_STARTIRQEN)
        s->chan[ch].state |= DCSR_STARTINTR;
}

static void pxa2xx_dma_run(PXA2xxDMAState *s)
{
    int c, srcinc, destinc;
    uint32_t n, size;
    uint32_t width;
    uint32_t length;
    uint8_t buffer[32];
    PXA2xxDMAChannel *ch;

    if (s->running ++)
        return;

    while (s->running) {
        s->running = 1;
        for (c = 0; c < s->channels; c ++) {
            ch = &s->chan[c];

            while ((ch->state & DCSR_RUN) && !(ch->state & DCSR_STOPINTR)) {
                /* Test for pending requests */
                if ((ch->cmd & (DCMD_FLOWSRC | DCMD_FLOWTRG)) && !ch->request)
                    break;

                length = ch->cmd & DCMD_LEN;
                size = DCMD_SIZE(ch->cmd);
                width = DCMD_WIDTH(ch->cmd);

                srcinc = (ch->cmd & DCMD_INCSRCADDR) ? width : 0;
                destinc = (ch->cmd & DCMD_INCTRGADDR) ? width : 0;

                while (length) {
                    size = MIN(length, size);

                    for (n = 0; n < size; n += width) {
                        cpu_physical_memory_read(ch->src, buffer + n, width);
                        ch->src += srcinc;
                    }

                    for (n = 0; n < size; n += width) {
                        cpu_physical_memory_write(ch->dest, buffer + n, width);
                        ch->dest += destinc;
                    }

                    length -= size;

                    if ((ch->cmd & (DCMD_FLOWSRC | DCMD_FLOWTRG)) &&
                            !ch->request) {
                        ch->state |= DCSR_EORINT;
                        if (ch->state & DCSR_EORSTOPEN)
                            ch->state |= DCSR_STOPINTR;
                        if ((ch->state & DCSR_EORJMPEN) &&
                                        !(ch->state & DCSR_NODESCFETCH))
                            pxa2xx_dma_descriptor_fetch(s, c);
                        break;
		    }
                }

                ch->cmd = (ch->cmd & ~DCMD_LEN) | length;

                /* Is the transfer complete now? */
                if (!length) {
                    if (ch->cmd & DCMD_ENDIRQEN)
                        ch->state |= DCSR_ENDINTR;

                    if ((ch->state & DCSR_NODESCFETCH) ||
                                (ch->descr & DDADR_STOP) ||
                                (ch->state & DCSR_EORSTOPEN)) {
                        ch->state |= DCSR_STOPINTR;
                        ch->state &= ~DCSR_RUN;

                        break;
                    }

                    ch->state |= DCSR_STOPINTR;
                    break;
                }
            }
        }

        s->running --;
    }
}

static uint32_t pxa2xx_dma_read(void *opaque, target_phys_addr_t offset)
{
    PXA2xxDMAState *s = (PXA2xxDMAState *) opaque;
    unsigned int channel;

    switch (offset) {
    case DRCMR64 ... DRCMR74:
        offset -= DRCMR64 - DRCMR0 - (64 << 2);
        /* Fall through */
    case DRCMR0 ... DRCMR63:
        channel = (offset - DRCMR0) >> 2;
        return s->req[channel];

    case DRQSR0:
    case DRQSR1:
    case DRQSR2:
        return 0;

    case DCSR0 ... DCSR31:
        channel = offset >> 2;
	if (s->chan[channel].request)
            return s->chan[channel].state | DCSR_REQPEND;
        return s->chan[channel].state;

    case DINT:
        return s->stopintr | s->eorintr | s->rasintr |
                s->startintr | s->endintr;

    case DALGN:
        return s->align;

    case DPCSR:
        return s->pio;
    }

    if (offset >= D_CH0 && offset < D_CH0 + (s->channels << 4)) {
        channel = (offset - D_CH0) >> 4;
        switch ((offset & 0x0f) >> 2) {
        case DDADR:
            return s->chan[channel].descr;
        case DSADR:
            return s->chan[channel].src;
        case DTADR:
            return s->chan[channel].dest;
        case DCMD:
            return s->chan[channel].cmd;
        }
    }

    hw_error("%s: Bad offset 0x" TARGET_FMT_plx "\n", __FUNCTION__, offset);
    return 7;
}

static void pxa2xx_dma_write(void *opaque,
                 target_phys_addr_t offset, uint32_t value)
{
    PXA2xxDMAState *s = (PXA2xxDMAState *) opaque;
    unsigned int channel;

    switch (offset) {
    case DRCMR64 ... DRCMR74:
        offset -= DRCMR64 - DRCMR0 - (64 << 2);
        /* Fall through */
    case DRCMR0 ... DRCMR63:
        channel = (offset - DRCMR0) >> 2;

        if (value & DRCMR_MAPVLD)
            if ((value & DRCMR_CHLNUM) > s->channels)
                hw_error("%s: Bad DMA channel %i\n",
                         __FUNCTION__, value & DRCMR_CHLNUM);

        s->req[channel] = value;
        break;

    case DRQSR0:
    case DRQSR1:
    case DRQSR2:
        /* Nothing to do */
        break;

    case DCSR0 ... DCSR31:
        channel = offset >> 2;
        s->chan[channel].state &= 0x0000071f & ~(value &
                        (DCSR_EORINT | DCSR_ENDINTR |
                         DCSR_STARTINTR | DCSR_BUSERRINTR));
        s->chan[channel].state |= value & 0xfc800000;

        if (s->chan[channel].state & DCSR_STOPIRQEN)
            s->chan[channel].state &= ~DCSR_STOPINTR;

        if (value & DCSR_NODESCFETCH) {
            /* No-descriptor-fetch mode */
            if (value & DCSR_RUN) {
                s->chan[channel].state &= ~DCSR_STOPINTR;
                pxa2xx_dma_run(s);
            }
        } else {
            /* Descriptor-fetch mode */
            if (value & DCSR_RUN) {
                s->chan[channel].state &= ~DCSR_STOPINTR;
                pxa2xx_dma_descriptor_fetch(s, channel);
                pxa2xx_dma_run(s);
            }
        }

        /* Shouldn't matter as our DMA is synchronous.  */
        if (!(value & (DCSR_RUN | DCSR_MASKRUN)))
            s->chan[channel].state |= DCSR_STOPINTR;

        if (value & DCSR_CLRCMPST)
            s->chan[channel].state &= ~DCSR_CMPST;
        if (value & DCSR_SETCMPST)
            s->chan[channel].state |= DCSR_CMPST;

        pxa2xx_dma_update(s, channel);
        break;

    case DALGN:
        s->align = value;
        break;

    case DPCSR:
        s->pio = value & 0x80000001;
        break;

    default:
        if (offset >= D_CH0 && offset < D_CH0 + (s->channels << 4)) {
            channel = (offset - D_CH0) >> 4;
            switch ((offset & 0x0f) >> 2) {
            case DDADR:
                s->chan[channel].descr = value;
                break;
            case DSADR:
                s->chan[channel].src = value;
                break;
            case DTADR:
                s->chan[channel].dest = value;
                break;
            case DCMD:
                s->chan[channel].cmd = value;
                break;
            default:
                goto fail;
            }

            break;
        }
    fail:
        hw_error("%s: Bad offset " TARGET_FMT_plx "\n", __FUNCTION__, offset);
    }
}

static uint32_t pxa2xx_dma_readbad(void *opaque, target_phys_addr_t offset)
{
    hw_error("%s: Bad access width\n", __FUNCTION__);
    return 5;
}

static void pxa2xx_dma_writebad(void *opaque,
                 target_phys_addr_t offset, uint32_t value)
{
    hw_error("%s: Bad access width\n", __FUNCTION__);
}

static CPUReadMemoryFunc * const pxa2xx_dma_readfn[] = {
    pxa2xx_dma_readbad,
    pxa2xx_dma_readbad,
    pxa2xx_dma_read
};

static CPUWriteMemoryFunc * const pxa2xx_dma_writefn[] = {
    pxa2xx_dma_writebad,
    pxa2xx_dma_writebad,
    pxa2xx_dma_write
};

static void pxa2xx_dma_request(void *opaque, int req_num, int on)
{
    PXA2xxDMAState *s = opaque;
    int ch;
    if (req_num < 0 || req_num >= PXA2XX_DMA_NUM_REQUESTS)
        hw_error("%s: Bad DMA request %i\n", __FUNCTION__, req_num);

    if (!(s->req[req_num] & DRCMR_MAPVLD))
        return;
    ch = s->req[req_num] & DRCMR_CHLNUM;

    if (!s->chan[ch].request && on)
        s->chan[ch].state |= DCSR_RASINTR;
    else
        s->chan[ch].state &= ~DCSR_RASINTR;
    if (s->chan[ch].request && !on)
        s->chan[ch].state |= DCSR_EORINT;

    s->chan[ch].request = on;
    if (on) {
        pxa2xx_dma_run(s);
        pxa2xx_dma_update(s, ch);
    }
}

static int pxa2xx_dma_init(SysBusDevice *dev)
{
    int i, iomemtype;
    PXA2xxDMAState *s;
    s = FROM_SYSBUS(PXA2xxDMAState, dev);

    if (s->channels <= 0) {
        return -1;
    }

    s->chan = g_malloc0(sizeof(PXA2xxDMAChannel) * s->channels);

    memset(s->chan, 0, sizeof(PXA2xxDMAChannel) * s->channels);
    for (i = 0; i < s->channels; i ++)
        s->chan[i].state = DCSR_STOPINTR;

    memset(s->req, 0, sizeof(uint8_t) * PXA2XX_DMA_NUM_REQUESTS);

    qdev_init_gpio_in(&dev->qdev, pxa2xx_dma_request, PXA2XX_DMA_NUM_REQUESTS);

    iomemtype = cpu_register_io_memory(pxa2xx_dma_readfn,
                    pxa2xx_dma_writefn, s, DEVICE_NATIVE_ENDIAN);
    sysbus_init_mmio(dev, 0x00010000, iomemtype);
    sysbus_init_irq(dev, &s->irq);

    return 0;
}

DeviceState *pxa27x_dma_init(target_phys_addr_t base, qemu_irq irq)
{
    DeviceState *dev;

    dev = qdev_create(NULL, "pxa2xx-dma");
    qdev_prop_set_int32(dev, "channels", PXA27X_DMA_NUM_CHANNELS);
    qdev_init_nofail(dev);

    sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
    sysbus_connect_irq(sysbus_from_qdev(dev), 0, irq);

    return dev;
}

DeviceState *pxa255_dma_init(target_phys_addr_t base, qemu_irq irq)
{
    DeviceState *dev;

    dev = qdev_create(NULL, "pxa2xx-dma");
    qdev_prop_set_int32(dev, "channels", PXA27X_DMA_NUM_CHANNELS);
    qdev_init_nofail(dev);

    sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
    sysbus_connect_irq(sysbus_from_qdev(dev), 0, irq);

    return dev;
}

static bool is_version_0(void *opaque, int version_id)
{
    return version_id == 0;
}

static VMStateDescription vmstate_pxa2xx_dma_chan = {
    .name = "pxa2xx_dma_chan",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINTTL(descr, PXA2xxDMAChannel),
        VMSTATE_UINTTL(src, PXA2xxDMAChannel),
        VMSTATE_UINTTL(dest, PXA2xxDMAChannel),
        VMSTATE_UINT32(cmd, PXA2xxDMAChannel),
        VMSTATE_UINT32(state, PXA2xxDMAChannel),
        VMSTATE_INT32(request, PXA2xxDMAChannel),
        VMSTATE_END_OF_LIST(),
    },
};

static VMStateDescription vmstate_pxa2xx_dma = {
    .name = "pxa2xx_dma",
    .version_id = 1,
    .minimum_version_id = 0,
    .minimum_version_id_old = 0,
    .fields = (VMStateField[]) {
        VMSTATE_UNUSED_TEST(is_version_0, 4),
        VMSTATE_UINT32(stopintr, PXA2xxDMAState),
        VMSTATE_UINT32(eorintr, PXA2xxDMAState),
        VMSTATE_UINT32(rasintr, PXA2xxDMAState),
        VMSTATE_UINT32(startintr, PXA2xxDMAState),
        VMSTATE_UINT32(endintr, PXA2xxDMAState),
        VMSTATE_UINT32(align, PXA2xxDMAState),
        VMSTATE_UINT32(pio, PXA2xxDMAState),
        VMSTATE_BUFFER(req, PXA2xxDMAState),
        VMSTATE_STRUCT_VARRAY_POINTER_INT32(chan, PXA2xxDMAState, channels,
                vmstate_pxa2xx_dma_chan, PXA2xxDMAChannel),
        VMSTATE_END_OF_LIST(),
    },
};

static SysBusDeviceInfo pxa2xx_dma_info = {
    .init       = pxa2xx_dma_init,
    .qdev.name  = "pxa2xx-dma",
    .qdev.desc  = "PXA2xx DMA controller",
    .qdev.size  = sizeof(PXA2xxDMAState),
    .qdev.vmsd  = &vmstate_pxa2xx_dma,
    .qdev.props = (Property[]) {
        DEFINE_PROP_INT32("channels", PXA2xxDMAState, channels, -1),
        DEFINE_PROP_END_OF_LIST(),
    },
};

static void pxa2xx_dma_register(void)
{
    sysbus_register_withprop(&pxa2xx_dma_info);
}
device_init(pxa2xx_dma_register);
Commit	Line	Data
c1713132 AZ	1	/*
	2	* Intel XScale PXA255/270 DMA controller.
	3	*
	4	* Copyright (c) 2006 Openedhand Ltd.
	5	* Copyright (c) 2006 Thorsten Zitterell
	6	* Written by Andrzej Zaborowski <[email protected]>
	7	*
8e31bf38	8	* This code is licensed under the GPL.
c1713132 AZ	9	*/
c1713132 AZ	10
87ecb68b PB	11	#include "hw.h"
87ecb68b PB	12	#include "pxa.h"
2115c019 AZ	13	#include "sysbus.h"
	14
	15	#define PXA255_DMA_NUM_CHANNELS 16
	16	#define PXA27X_DMA_NUM_CHANNELS 32
	17
	18	#define PXA2XX_DMA_NUM_REQUESTS 75
c1713132	19
bc24a225	20	typedef struct {
c227f099 AL	21	target_phys_addr_t descr;
	22	target_phys_addr_t src;
	23	target_phys_addr_t dest;
c1713132 AZ	24	uint32_t cmd;
	25	uint32_t state;
	26	int request;
bc24a225	27	} PXA2xxDMAChannel;
c1713132	28
2115c019 AZ	29	typedef struct PXA2xxDMAState {
2115c019 AZ	30	SysBusDevice busdev;
c1713132 AZ	31	qemu_irq irq;
	32
	33	uint32_t stopintr;
	34	uint32_t eorintr;
	35	uint32_t rasintr;
	36	uint32_t startintr;
	37	uint32_t endintr;
	38
	39	uint32_t align;
	40	uint32_t pio;
	41
	42	int channels;
bc24a225	43	PXA2xxDMAChannel *chan;
c1713132	44
2115c019	45	uint8_t req[PXA2XX_DMA_NUM_REQUESTS];
c1713132 AZ	46
	47	/* Flag to avoid recursive DMA invocations. */
	48	int running;
2115c019	49	} PXA2xxDMAState;
c1713132 AZ	50
	51	#define DCSR0 0x0000 /* DMA Control / Status register for Channel 0 */
	52	#define DCSR31 0x007c /* DMA Control / Status register for Channel 31 */
	53	#define DALGN 0x00a0 /* DMA Alignment register */
	54	#define DPCSR 0x00a4 /* DMA Programmed I/O Control Status register */
	55	#define DRQSR0 0x00e0 /* DMA DREQ<0> Status register */
	56	#define DRQSR1 0x00e4 /* DMA DREQ<1> Status register */
	57	#define DRQSR2 0x00e8 /* DMA DREQ<2> Status register */
	58	#define DINT 0x00f0 /* DMA Interrupt register */
	59	#define DRCMR0 0x0100 /* Request to Channel Map register 0 */
	60	#define DRCMR63 0x01fc /* Request to Channel Map register 63 */
	61	#define D_CH0 0x0200 /* Channel 0 Descriptor start */
	62	#define DRCMR64 0x1100 /* Request to Channel Map register 64 */
	63	#define DRCMR74 0x1128 /* Request to Channel Map register 74 */
	64
	65	/* Per-channel register */
	66	#define DDADR 0x00
	67	#define DSADR 0x01
	68	#define DTADR 0x02
	69	#define DCMD 0x03
	70
	71	/* Bit-field masks */
	72	#define DRCMR_CHLNUM 0x1f
	73	#define DRCMR_MAPVLD (1 << 7)
	74	#define DDADR_STOP (1 << 0)
	75	#define DDADR_BREN (1 << 1)
	76	#define DCMD_LEN 0x1fff
	77	#define DCMD_WIDTH(x) (1 << ((((x) >> 14) & 3) - 1))
	78	#define DCMD_SIZE(x) (4 << (((x) >> 16) & 3))
	79	#define DCMD_FLYBYT (1 << 19)
	80	#define DCMD_FLYBYS (1 << 20)
	81	#define DCMD_ENDIRQEN (1 << 21)
	82	#define DCMD_STARTIRQEN (1 << 22)
	83	#define DCMD_CMPEN (1 << 25)
	84	#define DCMD_FLOWTRG (1 << 28)
	85	#define DCMD_FLOWSRC (1 << 29)
	86	#define DCMD_INCTRGADDR (1 << 30)
	87	#define DCMD_INCSRCADDR (1 << 31)
	88	#define DCSR_BUSERRINTR (1 << 0)
	89	#define DCSR_STARTINTR (1 << 1)
	90	#define DCSR_ENDINTR (1 << 2)
	91	#define DCSR_STOPINTR (1 << 3)
	92	#define DCSR_RASINTR (1 << 4)
	93	#define DCSR_REQPEND (1 << 8)
	94	#define DCSR_EORINT (1 << 9)
	95	#define DCSR_CMPST (1 << 10)
	96	#define DCSR_MASKRUN (1 << 22)
	97	#define DCSR_RASIRQEN (1 << 23)
	98	#define DCSR_CLRCMPST (1 << 24)
	99	#define DCSR_SETCMPST (1 << 25)
	100	#define DCSR_EORSTOPEN (1 << 26)
	101	#define DCSR_EORJMPEN (1 << 27)
	102	#define DCSR_EORIRQEN (1 << 28)
	103	#define DCSR_STOPIRQEN (1 << 29)
	104	#define DCSR_NODESCFETCH (1 << 30)
	105	#define DCSR_RUN (1 << 31)
	106
bc24a225	107	static inline void pxa2xx_dma_update(PXA2xxDMAState *s, int ch)
c1713132 AZ	108	{
	109	if (ch >= 0) {
	110	if ((s->chan[ch].state & DCSR_STOPIRQEN) &&
	111	(s->chan[ch].state & DCSR_STOPINTR))
	112	s->stopintr \|= 1 << ch;
	113	else
	114	s->stopintr &= ~(1 << ch);
	115
	116	if ((s->chan[ch].state & DCSR_EORIRQEN) &&
	117	(s->chan[ch].state & DCSR_EORINT))
	118	s->eorintr \|= 1 << ch;
	119	else
	120	s->eorintr &= ~(1 << ch);
	121
	122	if ((s->chan[ch].state & DCSR_RASIRQEN) &&
	123	(s->chan[ch].state & DCSR_RASINTR))
	124	s->rasintr \|= 1 << ch;
	125	else
	126	s->rasintr &= ~(1 << ch);
	127
	128	if (s->chan[ch].state & DCSR_STARTINTR)
	129	s->startintr \|= 1 << ch;
	130	else
	131	s->startintr &= ~(1 << ch);
	132
	133	if (s->chan[ch].state & DCSR_ENDINTR)
	134	s->endintr \|= 1 << ch;
	135	else
	136	s->endintr &= ~(1 << ch);
	137	}
	138
	139	if (s->stopintr \| s->eorintr \| s->rasintr \| s->startintr \| s->endintr)
	140	qemu_irq_raise(s->irq);
	141	else
	142	qemu_irq_lower(s->irq);
	143	}
	144
	145	static inline void pxa2xx_dma_descriptor_fetch(
bc24a225	146	PXA2xxDMAState *s, int ch)
c1713132 AZ	147	{
c1713132 AZ	148	uint32_t desc[4];
c227f099	149	target_phys_addr_t daddr = s->chan[ch].descr & ~0xf;
c1713132 AZ	150	if ((s->chan[ch].descr & DDADR_BREN) && (s->chan[ch].state & DCSR_CMPST))
	151	daddr += 32;
	152
	153	cpu_physical_memory_read(daddr, (uint8_t *) desc, 16);
	154	s->chan[ch].descr = desc[DDADR];
	155	s->chan[ch].src = desc[DSADR];
	156	s->chan[ch].dest = desc[DTADR];
	157	s->chan[ch].cmd = desc[DCMD];
	158
	159	if (s->chan[ch].cmd & DCMD_FLOWSRC)
	160	s->chan[ch].src &= ~3;
	161	if (s->chan[ch].cmd & DCMD_FLOWTRG)
	162	s->chan[ch].dest &= ~3;
	163
	164	if (s->chan[ch].cmd & (DCMD_CMPEN \| DCMD_FLYBYS \| DCMD_FLYBYT))
	165	printf("%s: unsupported mode in channel %i\n", __FUNCTION__, ch);
	166
	167	if (s->chan[ch].cmd & DCMD_STARTIRQEN)
	168	s->chan[ch].state \|= DCSR_STARTINTR;
	169	}
	170
bc24a225	171	static void pxa2xx_dma_run(PXA2xxDMAState *s)
c1713132 AZ	172	{
	173	int c, srcinc, destinc;
	174	uint32_t n, size;
	175	uint32_t width;
	176	uint32_t length;
b55266b5	177	uint8_t buffer[32];
bc24a225	178	PXA2xxDMAChannel *ch;
c1713132 AZ	179
	180	if (s->running ++)
	181	return;
	182
	183	while (s->running) {
	184	s->running = 1;
	185	for (c = 0; c < s->channels; c ++) {
	186	ch = &s->chan[c];
	187
	188	while ((ch->state & DCSR_RUN) && !(ch->state & DCSR_STOPINTR)) {
	189	/* Test for pending requests */
	190	if ((ch->cmd & (DCMD_FLOWSRC \| DCMD_FLOWTRG)) && !ch->request)
	191	break;
	192
	193	length = ch->cmd & DCMD_LEN;
	194	size = DCMD_SIZE(ch->cmd);
	195	width = DCMD_WIDTH(ch->cmd);
	196
	197	srcinc = (ch->cmd & DCMD_INCSRCADDR) ? width : 0;
	198	destinc = (ch->cmd & DCMD_INCTRGADDR) ? width : 0;
	199
	200	while (length) {
	201	size = MIN(length, size);
	202
	203	for (n = 0; n < size; n += width) {
	204	cpu_physical_memory_read(ch->src, buffer + n, width);
	205	ch->src += srcinc;
	206	}
	207
	208	for (n = 0; n < size; n += width) {
	209	cpu_physical_memory_write(ch->dest, buffer + n, width);
	210	ch->dest += destinc;
	211	}
	212
	213	length -= size;
	214
	215	if ((ch->cmd & (DCMD_FLOWSRC \| DCMD_FLOWTRG)) &&
	216	!ch->request) {
	217	ch->state \|= DCSR_EORINT;
	218	if (ch->state & DCSR_EORSTOPEN)
	219	ch->state \|= DCSR_STOPINTR;
	220	if ((ch->state & DCSR_EORJMPEN) &&
	221	!(ch->state & DCSR_NODESCFETCH))
	222	pxa2xx_dma_descriptor_fetch(s, c);
	223	break;
	224	}
	225	}
	226
	227	ch->cmd = (ch->cmd & ~DCMD_LEN) \| length;
	228
	229	/* Is the transfer complete now? */
	230	if (!length) {
	231	if (ch->cmd & DCMD_ENDIRQEN)
	232	ch->state \|= DCSR_ENDINTR;
	233
	234	if ((ch->state & DCSR_NODESCFETCH) \|\|
	235	(ch->descr & DDADR_STOP) \|\|
	236	(ch->state & DCSR_EORSTOPEN)) {
	237	ch->state \|= DCSR_STOPINTR;
	238	ch->state &= ~DCSR_RUN;
	239
	240	break;
	241	}
	242
243	ch->state \|= DCSR_STOPINTR;
244	break;
245	}
246	}
247	}
248
249	s->running --;
250	}
251	}
252
c227f099	253	static uint32_t pxa2xx_dma_read(void *opaque, target_phys_addr_t offset)
c1713132	254	{
bc24a225	255	PXA2xxDMAState s = (PXA2xxDMAState ) opaque;
c1713132	256	unsigned int channel;
c1713132 AZ	257
	258	switch (offset) {
	259	case DRCMR64 ... DRCMR74:
	260	offset -= DRCMR64 - DRCMR0 - (64 << 2);
	261	/* Fall through */
	262	case DRCMR0 ... DRCMR63:
	263	channel = (offset - DRCMR0) >> 2;
	264	return s->req[channel];
	265
	266	case DRQSR0:
	267	case DRQSR1:
	268	case DRQSR2:
	269	return 0;
	270
	271	case DCSR0 ... DCSR31:
	272	channel = offset >> 2;
	273	if (s->chan[channel].request)
	274	return s->chan[channel].state \| DCSR_REQPEND;
	275	return s->chan[channel].state;
	276
	277	case DINT:
	278	return s->stopintr \| s->eorintr \| s->rasintr \|
	279	s->startintr \| s->endintr;
	280
	281	case DALGN:
	282	return s->align;
	283
	284	case DPCSR:
	285	return s->pio;
	286	}
	287
	288	if (offset >= D_CH0 && offset < D_CH0 + (s->channels << 4)) {
	289	channel = (offset - D_CH0) >> 4;
	290	switch ((offset & 0x0f) >> 2) {
	291	case DDADR:
	292	return s->chan[channel].descr;
	293	case DSADR:
	294	return s->chan[channel].src;
	295	case DTADR:
	296	return s->chan[channel].dest;
	297	case DCMD:
	298	return s->chan[channel].cmd;
	299	}
	300	}
	301
2ac71179	302	hw_error("%s: Bad offset 0x" TARGET_FMT_plx "\n", __FUNCTION__, offset);
c1713132 AZ	303	return 7;
	304	}
	305
	306	static void pxa2xx_dma_write(void *opaque,
c227f099	307	target_phys_addr_t offset, uint32_t value)
c1713132	308	{
bc24a225	309	PXA2xxDMAState s = (PXA2xxDMAState ) opaque;
c1713132	310	unsigned int channel;
c1713132 AZ	311
	312	switch (offset) {
	313	case DRCMR64 ... DRCMR74:
	314	offset -= DRCMR64 - DRCMR0 - (64 << 2);
	315	/* Fall through */
	316	case DRCMR0 ... DRCMR63:
	317	channel = (offset - DRCMR0) >> 2;
	318
	319	if (value & DRCMR_MAPVLD)
	320	if ((value & DRCMR_CHLNUM) > s->channels)
2ac71179 PB	321	hw_error("%s: Bad DMA channel %i\n",
2ac71179 PB	322	__FUNCTION__, value & DRCMR_CHLNUM);
c1713132 AZ	323
	324	s->req[channel] = value;
	325	break;
	326
	327	case DRQSR0:
	328	case DRQSR1:
	329	case DRQSR2:
	330	/* Nothing to do */
	331	break;
	332
	333	case DCSR0 ... DCSR31:
	334	channel = offset >> 2;
	335	s->chan[channel].state &= 0x0000071f & ~(value &
	336	(DCSR_EORINT \| DCSR_ENDINTR \|
	337	DCSR_STARTINTR \| DCSR_BUSERRINTR));
	338	s->chan[channel].state \|= value & 0xfc800000;
	339
	340	if (s->chan[channel].state & DCSR_STOPIRQEN)
	341	s->chan[channel].state &= ~DCSR_STOPINTR;
	342
	343	if (value & DCSR_NODESCFETCH) {
	344	/* No-descriptor-fetch mode */
e1dad5a6 AZ	345	if (value & DCSR_RUN) {
e1dad5a6 AZ	346	s->chan[channel].state &= ~DCSR_STOPINTR;
c1713132	347	pxa2xx_dma_run(s);
e1dad5a6	348	}
c1713132 AZ	349	} else {
	350	/* Descriptor-fetch mode */
	351	if (value & DCSR_RUN) {
	352	s->chan[channel].state &= ~DCSR_STOPINTR;
	353	pxa2xx_dma_descriptor_fetch(s, channel);
	354	pxa2xx_dma_run(s);
	355	}
	356	}
	357
	358	/* Shouldn't matter as our DMA is synchronous. */
	359	if (!(value & (DCSR_RUN \| DCSR_MASKRUN)))
	360	s->chan[channel].state \|= DCSR_STOPINTR;
	361
	362	if (value & DCSR_CLRCMPST)
	363	s->chan[channel].state &= ~DCSR_CMPST;
	364	if (value & DCSR_SETCMPST)
	365	s->chan[channel].state \|= DCSR_CMPST;
	366
	367	pxa2xx_dma_update(s, channel);
	368	break;
	369
	370	case DALGN:
	371	s->align = value;
	372	break;
	373
	374	case DPCSR:
	375	s->pio = value & 0x80000001;
	376	break;
	377
	378	default:
	379	if (offset >= D_CH0 && offset < D_CH0 + (s->channels << 4)) {
	380	channel = (offset - D_CH0) >> 4;
	381	switch ((offset & 0x0f) >> 2) {
	382	case DDADR:
	383	s->chan[channel].descr = value;
	384	break;
	385	case DSADR:
	386	s->chan[channel].src = value;
	387	break;
	388	case DTADR:
	389	s->chan[channel].dest = value;
	390	break;
	391	case DCMD:
	392	s->chan[channel].cmd = value;
	393	break;
	394	default:
	395	goto fail;
	396	}
	397
	398	break;
	399	}
	400	fail:
2ac71179	401	hw_error("%s: Bad offset " TARGET_FMT_plx "\n", __FUNCTION__, offset);
c1713132 AZ	402	}
	403	}
	404
c227f099	405	static uint32_t pxa2xx_dma_readbad(void *opaque, target_phys_addr_t offset)
c1713132	406	{
2ac71179	407	hw_error("%s: Bad access width\n", __FUNCTION__);
c1713132 AZ	408	return 5;
	409	}
	410
	411	static void pxa2xx_dma_writebad(void *opaque,
c227f099	412	target_phys_addr_t offset, uint32_t value)
c1713132	413	{
2ac71179	414	hw_error("%s: Bad access width\n", __FUNCTION__);
c1713132 AZ	415	}
c1713132 AZ	416
d60efc6b	417	static CPUReadMemoryFunc * const pxa2xx_dma_readfn[] = {
c1713132 AZ	418	pxa2xx_dma_readbad,
	419	pxa2xx_dma_readbad,
	420	pxa2xx_dma_read
	421	};
	422
d60efc6b	423	static CPUWriteMemoryFunc * const pxa2xx_dma_writefn[] = {
c1713132 AZ	424	pxa2xx_dma_writebad,
	425	pxa2xx_dma_writebad,
	426	pxa2xx_dma_write
	427	};
	428
f114c826 AZ	429	static void pxa2xx_dma_request(void *opaque, int req_num, int on)
	430	{
	431	PXA2xxDMAState *s = opaque;
	432	int ch;
	433	if (req_num < 0 \|\| req_num >= PXA2XX_DMA_NUM_REQUESTS)
	434	hw_error("%s: Bad DMA request %i\n", __FUNCTION__, req_num);
	435
	436	if (!(s->req[req_num] & DRCMR_MAPVLD))
	437	return;
	438	ch = s->req[req_num] & DRCMR_CHLNUM;
	439
	440	if (!s->chan[ch].request && on)
	441	s->chan[ch].state \|= DCSR_RASINTR;
	442	else
	443	s->chan[ch].state &= ~DCSR_RASINTR;
	444	if (s->chan[ch].request && !on)
	445	s->chan[ch].state \|= DCSR_EORINT;
	446
	447	s->chan[ch].request = on;
	448	if (on) {
	449	pxa2xx_dma_run(s);
	450	pxa2xx_dma_update(s, ch);
	451	}
	452	}
aa941b94	453
2115c019	454	static int pxa2xx_dma_init(SysBusDevice *dev)
c1713132 AZ	455	{
c1713132 AZ	456	int i, iomemtype;
bc24a225	457	PXA2xxDMAState *s;
2115c019 AZ	458	s = FROM_SYSBUS(PXA2xxDMAState, dev);
	459
	460	if (s->channels <= 0) {
	461	return -1;
	462	}
c1713132	463
7267c094	464	s->chan = g_malloc0(sizeof(PXA2xxDMAChannel) * s->channels);
c1713132	465
bc24a225	466	memset(s->chan, 0, sizeof(PXA2xxDMAChannel) * s->channels);
c1713132 AZ	467	for (i = 0; i < s->channels; i ++)
	468	s->chan[i].state = DCSR_STOPINTR;
	469
3f582262	470	memset(s->req, 0, sizeof(uint8_t) * PXA2XX_DMA_NUM_REQUESTS);
c1713132	471
2115c019 AZ	472	qdev_init_gpio_in(&dev->qdev, pxa2xx_dma_request, PXA2XX_DMA_NUM_REQUESTS);
2115c019 AZ	473
1eed09cb	474	iomemtype = cpu_register_io_memory(pxa2xx_dma_readfn,
2507c12a	475	pxa2xx_dma_writefn, s, DEVICE_NATIVE_ENDIAN);
2115c019 AZ	476	sysbus_init_mmio(dev, 0x00010000, iomemtype);
2115c019 AZ	477	sysbus_init_irq(dev, &s->irq);
c1713132	478
2115c019	479	return 0;
c1713132 AZ	480	}
c1713132 AZ	481
2115c019	482	DeviceState *pxa27x_dma_init(target_phys_addr_t base, qemu_irq irq)
c1713132	483	{
2115c019 AZ	484	DeviceState *dev;
	485
	486	dev = qdev_create(NULL, "pxa2xx-dma");
	487	qdev_prop_set_int32(dev, "channels", PXA27X_DMA_NUM_CHANNELS);
	488	qdev_init_nofail(dev);
	489
	490	sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
	491	sysbus_connect_irq(sysbus_from_qdev(dev), 0, irq);
	492
	493	return dev;
c1713132 AZ	494	}
c1713132 AZ	495
2115c019	496	DeviceState *pxa255_dma_init(target_phys_addr_t base, qemu_irq irq)
c1713132	497	{
2115c019 AZ	498	DeviceState *dev;
	499
	500	dev = qdev_create(NULL, "pxa2xx-dma");
	501	qdev_prop_set_int32(dev, "channels", PXA27X_DMA_NUM_CHANNELS);
	502	qdev_init_nofail(dev);
	503
	504	sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
	505	sysbus_connect_irq(sysbus_from_qdev(dev), 0, irq);
	506
	507	return dev;
c1713132 AZ	508	}
c1713132 AZ	509
2115c019 AZ	510	static bool is_version_0(void *opaque, int version_id)
	511	{
	512	return version_id == 0;
	513	}
	514
	515	static VMStateDescription vmstate_pxa2xx_dma_chan = {
	516	.name = "pxa2xx_dma_chan",
	517	.version_id = 1,
	518	.minimum_version_id = 1,
	519	.minimum_version_id_old = 1,
	520	.fields = (VMStateField[]) {
	521	VMSTATE_UINTTL(descr, PXA2xxDMAChannel),
	522	VMSTATE_UINTTL(src, PXA2xxDMAChannel),
	523	VMSTATE_UINTTL(dest, PXA2xxDMAChannel),
	524	VMSTATE_UINT32(cmd, PXA2xxDMAChannel),
	525	VMSTATE_UINT32(state, PXA2xxDMAChannel),
	526	VMSTATE_INT32(request, PXA2xxDMAChannel),
	527	VMSTATE_END_OF_LIST(),
	528	},
	529	};
	530
	531	static VMStateDescription vmstate_pxa2xx_dma = {
	532	.name = "pxa2xx_dma",
	533	.version_id = 1,
	534	.minimum_version_id = 0,
	535	.minimum_version_id_old = 0,
	536	.fields = (VMStateField[]) {
	537	VMSTATE_UNUSED_TEST(is_version_0, 4),
	538	VMSTATE_UINT32(stopintr, PXA2xxDMAState),
	539	VMSTATE_UINT32(eorintr, PXA2xxDMAState),
	540	VMSTATE_UINT32(rasintr, PXA2xxDMAState),
	541	VMSTATE_UINT32(startintr, PXA2xxDMAState),
	542	VMSTATE_UINT32(endintr, PXA2xxDMAState),
	543	VMSTATE_UINT32(align, PXA2xxDMAState),
	544	VMSTATE_UINT32(pio, PXA2xxDMAState),
	545	VMSTATE_BUFFER(req, PXA2xxDMAState),
	546	VMSTATE_STRUCT_VARRAY_POINTER_INT32(chan, PXA2xxDMAState, channels,
	547	vmstate_pxa2xx_dma_chan, PXA2xxDMAChannel),
	548	VMSTATE_END_OF_LIST(),
	549	},
	550	};
	551
	552	static SysBusDeviceInfo pxa2xx_dma_info = {
	553	.init = pxa2xx_dma_init,
	554	.qdev.name = "pxa2xx-dma",
	555	.qdev.desc = "PXA2xx DMA controller",
	556	.qdev.size = sizeof(PXA2xxDMAState),
	557	.qdev.vmsd = &vmstate_pxa2xx_dma,
	558	.qdev.props = (Property[]) {
	559	DEFINE_PROP_INT32("channels", PXA2xxDMAState, channels, -1),
	560	DEFINE_PROP_END_OF_LIST(),
	561	},
	562	};
	563
	564	static void pxa2xx_dma_register(void)
	565	{
	566	sysbus_register_withprop(&pxa2xx_dma_info);
	567	}
	568	device_init(pxa2xx_dma_register);