[qemu.git] / target / hppa / gdbstub.c

/*
 * HPPA gdb server stub
 *
 * Copyright (c) 2016 Richard Henderson <[email protected]>
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "qemu-common.h"
#include "cpu.h"
#include "exec/gdbstub.h"

int hppa_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
{
    HPPACPU *cpu = HPPA_CPU(cs);
    CPUHPPAState *env = &cpu->env;
    target_ureg val;

    switch (n) {
    case 0:
        val = cpu_hppa_get_psw(env);
        break;
    case 1 ... 31:
        val = env->gr[n];
        break;
    case 32:
        val = env->cr[CR_SAR];
        break;
    case 33:
        val = env->iaoq_f;
        break;
    case 34:
        val = env->iasq_f >> 32;
        break;
    case 35:
        val = env->iaoq_b;
        break;
    case 36:
        val = env->iasq_b >> 32;
        break;
    case 37:
        val = env->cr[CR_EIEM];
        break;
    case 38:
        val = env->cr[CR_IIR];
        break;
    case 39:
        val = env->cr[CR_ISR];
        break;
    case 40:
        val = env->cr[CR_IOR];
        break;
    case 41:
        val = env->cr[CR_IPSW];
        break;
    case 43:
        val = env->sr[4] >> 32;
        break;
    case 44:
        val = env->sr[0] >> 32;
        break;
    case 45:
        val = env->sr[1] >> 32;
        break;
    case 46:
        val = env->sr[2] >> 32;
        break;
    case 47:
        val = env->sr[3] >> 32;
        break;
    case 48:
        val = env->sr[5] >> 32;
        break;
    case 49:
        val = env->sr[6] >> 32;
        break;
    case 50:
        val = env->sr[7] >> 32;
        break;
    case 51:
        val = env->cr[CR_RC];
        break;
    case 52:
        val = env->cr[8];
        break;
    case 53:
        val = env->cr[9];
        break;
    case 54:
        val = env->cr[CR_SCRCCR];
        break;
    case 55:
        val = env->cr[12];
        break;
    case 56:
        val = env->cr[13];
        break;
    case 57:
        val = env->cr[24];
        break;
    case 58:
        val = env->cr[25];
        break;
    case 59:
        val = env->cr[26];
        break;
    case 60:
        val = env->cr[27];
        break;
    case 61:
        val = env->cr[28];
        break;
    case 62:
        val = env->cr[29];
        break;
    case 63:
        val = env->cr[30];
        break;
    case 64 ... 127:
        val = extract64(env->fr[(n - 64) / 2], (n & 1 ? 0 : 32), 32);
        break;
    default:
        if (n < 128) {
            val = 0;
        } else {
            return 0;
        }
        break;
    }

    if (TARGET_REGISTER_BITS == 64) {
        return gdb_get_reg64(mem_buf, val);
    } else {
        return gdb_get_reg32(mem_buf, val);
    }
}

int hppa_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
{
    HPPACPU *cpu = HPPA_CPU(cs);
    CPUHPPAState *env = &cpu->env;
    target_ureg val;

    if (TARGET_REGISTER_BITS == 64) {
        val = ldq_p(mem_buf);
    } else {
        val = ldl_p(mem_buf);
    }

    switch (n) {
    case 0:
        cpu_hppa_put_psw(env, val);
        break;
    case 1 ... 31:
        env->gr[n] = val;
        break;
    case 32:
        env->cr[CR_SAR] = val;
        break;
    case 33:
        env->iaoq_f = val;
        break;
    case 34:
        env->iasq_f = (uint64_t)val << 32;
        break;
    case 35:
        env->iaoq_b = val;
        break;
    case 36:
        env->iasq_b = (uint64_t)val << 32;
        break;
    case 37:
        env->cr[CR_EIEM] = val;
        break;
    case 38:
        env->cr[CR_IIR] = val;
        break;
    case 39:
        env->cr[CR_ISR] = val;
        break;
    case 40:
        env->cr[CR_IOR] = val;
        break;
    case 41:
        env->cr[CR_IPSW] = val;
        break;
    case 43:
        env->sr[4] = (uint64_t)val << 32;
        break;
    case 44:
        env->sr[0] = (uint64_t)val << 32;
        break;
    case 45:
        env->sr[1] = (uint64_t)val << 32;
        break;
    case 46:
        env->sr[2] = (uint64_t)val << 32;
        break;
    case 47:
        env->sr[3] = (uint64_t)val << 32;
        break;
    case 48:
        env->sr[5] = (uint64_t)val << 32;
        break;
    case 49:
        env->sr[6] = (uint64_t)val << 32;
        break;
    case 50:
        env->sr[7] = (uint64_t)val << 32;
        break;
    case 51:
        env->cr[CR_RC] = val;
        break;
    case 52:
        env->cr[8] = val;
        break;
    case 53:
        env->cr[9] = val;
        break;
    case 54:
        env->cr[CR_SCRCCR] = val;
        break;
    case 55:
        env->cr[12] = val;
        break;
    case 56:
        env->cr[13] = val;
        break;
    case 57:
        env->cr[24] = val;
        break;
    case 58:
        env->cr[25] = val;
        break;
    case 59:
        env->cr[26] = val;
        break;
    case 60:
        env->cr[27] = val;
        break;
    case 61:
        env->cr[28] = val;
        break;
    case 62:
        env->cr[29] = val;
        break;
    case 63:
        env->cr[30] = val;
        break;
    case 64:
        env->fr[0] = deposit64(env->fr[0], 32, 32, val);
        cpu_hppa_loaded_fr0(env);
        break;
    case 65 ... 127:
        {
            uint64_t *fr = &env->fr[(n - 64) / 2];
            *fr = deposit64(*fr, val, (n & 1 ? 0 : 32), 32);
        }
        break;
    default:
        if (n >= 128) {
            return 0;
        }
        break;
    }
    return sizeof(target_ureg);
}
Commit	Line	Data
61766fe9 RH	1	/*
	2	* HPPA gdb server stub
	3	*
	4	* Copyright (c) 2016 Richard Henderson <[email protected]>
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
	20	#include "qemu/osdep.h"
	21	#include "qemu-common.h"
	22	#include "cpu.h"
	23	#include "exec/gdbstub.h"
	24
	25	int hppa_cpu_gdb_read_register(CPUState cs, uint8_t mem_buf, int n)
	26	{
	27	HPPACPU *cpu = HPPA_CPU(cs);
	28	CPUHPPAState *env = &cpu->env;
eaa3783b	29	target_ureg val;
61766fe9 RH	30
	31	switch (n) {
	32	case 0:
	33	val = cpu_hppa_get_psw(env);
	34	break;
	35	case 1 ... 31:
	36	val = env->gr[n];
	37	break;
	38	case 32:
35136a77	39	val = env->cr[CR_SAR];
61766fe9 RH	40	break;
	41	case 33:
	42	val = env->iaoq_f;
	43	break;
e33348a6 RH	44	case 34:
	45	val = env->iasq_f >> 32;
	46	break;
61766fe9 RH	47	case 35:
	48	val = env->iaoq_b;
	49	break;
e33348a6 RH	50	case 36:
	51	val = env->iasq_b >> 32;
	52	break;
	53	case 37:
	54	val = env->cr[CR_EIEM];
	55	break;
	56	case 38:
	57	val = env->cr[CR_IIR];
	58	break;
	59	case 39:
	60	val = env->cr[CR_ISR];
	61	break;
	62	case 40:
	63	val = env->cr[CR_IOR];
	64	break;
	65	case 41:
	66	val = env->cr[CR_IPSW];
	67	break;
	68	case 43:
	69	val = env->sr[4] >> 32;
	70	break;
	71	case 44:
	72	val = env->sr[0] >> 32;
	73	break;
	74	case 45:
	75	val = env->sr[1] >> 32;
	76	break;
	77	case 46:
	78	val = env->sr[2] >> 32;
	79	break;
	80	case 47:
	81	val = env->sr[3] >> 32;
	82	break;
	83	case 48:
	84	val = env->sr[5] >> 32;
	85	break;
	86	case 49:
	87	val = env->sr[6] >> 32;
	88	break;
	89	case 50:
	90	val = env->sr[7] >> 32;
	91	break;
	92	case 51:
	93	val = env->cr[CR_RC];
	94	break;
	95	case 52:
	96	val = env->cr[8];
	97	break;
	98	case 53:
	99	val = env->cr[9];
	100	break;
	101	case 54:
	102	val = env->cr[CR_SCRCCR];
	103	break;
	104	case 55:
	105	val = env->cr[12];
	106	break;
	107	case 56:
	108	val = env->cr[13];
	109	break;
	110	case 57:
	111	val = env->cr[24];
	112	break;
	113	case 58:
114	val = env->cr[25];
115	break;
61766fe9	116	case 59:
35136a77	117	val = env->cr[26];
61766fe9 RH	118	break;
61766fe9 RH	119	case 60:
35136a77	120	val = env->cr[27];
61766fe9	121	break;
e33348a6 RH	122	case 61:
	123	val = env->cr[28];
	124	break;
	125	case 62:
	126	val = env->cr[29];
	127	break;
	128	case 63:
	129	val = env->cr[30];
	130	break;
61766fe9 RH	131	case 64 ... 127:
	132	val = extract64(env->fr[(n - 64) / 2], (n & 1 ? 0 : 32), 32);
	133	break;
	134	default:
	135	if (n < 128) {
	136	val = 0;
	137	} else {
	138	return 0;
	139	}
	140	break;
	141	}
eaa3783b RH	142
	143	if (TARGET_REGISTER_BITS == 64) {
	144	return gdb_get_reg64(mem_buf, val);
	145	} else {
	146	return gdb_get_reg32(mem_buf, val);
	147	}
61766fe9 RH	148	}
	149
	150	int hppa_cpu_gdb_write_register(CPUState cs, uint8_t mem_buf, int n)
	151	{
	152	HPPACPU *cpu = HPPA_CPU(cs);
	153	CPUHPPAState *env = &cpu->env;
eaa3783b RH	154	target_ureg val;
	155
	156	if (TARGET_REGISTER_BITS == 64) {
	157	val = ldq_p(mem_buf);
	158	} else {
	159	val = ldl_p(mem_buf);
	160	}
61766fe9 RH	161
	162	switch (n) {
	163	case 0:
	164	cpu_hppa_put_psw(env, val);
	165	break;
	166	case 1 ... 31:
	167	env->gr[n] = val;
	168	break;
	169	case 32:
35136a77	170	env->cr[CR_SAR] = val;
61766fe9 RH	171	break;
	172	case 33:
	173	env->iaoq_f = val;
	174	break;
e33348a6 RH	175	case 34:
	176	env->iasq_f = (uint64_t)val << 32;
	177	break;
61766fe9 RH	178	case 35:
61766fe9 RH	179	env->iaoq_b = val;
6836a8fb	180	break;
e33348a6 RH	181	case 36:
	182	env->iasq_b = (uint64_t)val << 32;
	183	break;
	184	case 37:
	185	env->cr[CR_EIEM] = val;
	186	break;
	187	case 38:
	188	env->cr[CR_IIR] = val;
	189	break;
	190	case 39:
	191	env->cr[CR_ISR] = val;
	192	break;
	193	case 40:
	194	env->cr[CR_IOR] = val;
	195	break;
	196	case 41:
	197	env->cr[CR_IPSW] = val;
	198	break;
	199	case 43:
	200	env->sr[4] = (uint64_t)val << 32;
	201	break;
	202	case 44:
	203	env->sr[0] = (uint64_t)val << 32;
	204	break;
	205	case 45:
	206	env->sr[1] = (uint64_t)val << 32;
	207	break;
	208	case 46:
	209	env->sr[2] = (uint64_t)val << 32;
	210	break;
	211	case 47:
	212	env->sr[3] = (uint64_t)val << 32;
	213	break;
	214	case 48:
	215	env->sr[5] = (uint64_t)val << 32;
	216	break;
	217	case 49:
	218	env->sr[6] = (uint64_t)val << 32;
	219	break;
	220	case 50:
	221	env->sr[7] = (uint64_t)val << 32;
	222	break;
	223	case 51:
	224	env->cr[CR_RC] = val;
	225	break;
	226	case 52:
	227	env->cr[8] = val;
	228	break;
	229	case 53:
	230	env->cr[9] = val;
	231	break;
	232	case 54:
	233	env->cr[CR_SCRCCR] = val;
	234	break;
	235	case 55:
	236	env->cr[12] = val;
	237	break;
	238	case 56:
	239	env->cr[13] = val;
	240	break;
	241	case 57:
	242	env->cr[24] = val;
	243	break;
	244	case 58:
245	env->cr[25] = val;
246	break;
61766fe9	247	case 59:
35136a77	248	env->cr[26] = val;
61766fe9 RH	249	break;
61766fe9 RH	250	case 60:
35136a77	251	env->cr[27] = val;
61766fe9	252	break;
e33348a6 RH	253	case 61:
	254	env->cr[28] = val;
	255	break;
	256	case 62:
	257	env->cr[29] = val;
	258	break;
	259	case 63:
	260	env->cr[30] = val;
	261	break;
61766fe9 RH	262	case 64:
	263	env->fr[0] = deposit64(env->fr[0], 32, 32, val);
	264	cpu_hppa_loaded_fr0(env);
	265	break;
	266	case 65 ... 127:
	267	{
	268	uint64_t *fr = &env->fr[(n - 64) / 2];
	269	fr = deposit64(fr, val, (n & 1 ? 0 : 32), 32);
	270	}
	271	break;
	272	default:
	273	if (n >= 128) {
	274	return 0;
	275	}
	276	break;
	277	}
eaa3783b	278	return sizeof(target_ureg);
61766fe9	279	}