s390x/cpumodel: "host" and "qemu" as CPU subclasses
[qemu.git] / target-s390x / cpu.h
CommitLineData
10ec5117
AG
1/*
2 * S/390 virtual CPU header
3 *
4 * Copyright (c) 2009 Ulrich Hecht
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
ccb084d3
CB
16 * Contributions after 2012-10-29 are licensed under the terms of the
17 * GNU GPL, version 2 or (at your option) any later version.
18 *
19 * You should have received a copy of the GNU (Lesser) General Public
70539e18 20 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
10ec5117 21 */
07f5a258
MA
22
23#ifndef S390X_CPU_H
24#define S390X_CPU_H
45133b74 25
45133b74 26#include "qemu-common.h"
a4a02f99 27#include "cpu-qom.h"
10ec5117
AG
28
29#define TARGET_LONG_BITS 64
30
4ab23a91 31#define ELF_MACHINE_UNAME "S390X"
10ec5117 32
9349b4f9 33#define CPUArchState struct CPUS390XState
10ec5117 34
022c62cb 35#include "exec/cpu-defs.h"
bcec36ea
AG
36#define TARGET_PAGE_BITS 12
37
5b23fd03 38#define TARGET_PHYS_ADDR_SPACE_BITS 64
bcec36ea
AG
39#define TARGET_VIRT_ADDR_SPACE_BITS 64
40
022c62cb 41#include "exec/cpu-all.h"
10ec5117 42
6b4c305c 43#include "fpu/softfloat.h"
10ec5117 44
bcec36ea 45#define NB_MMU_MODES 3
a3fd5220 46#define TARGET_INSN_START_EXTRA_WORDS 1
10ec5117 47
bcec36ea
AG
48#define MMU_MODE0_SUFFIX _primary
49#define MMU_MODE1_SUFFIX _secondary
50#define MMU_MODE2_SUFFIX _home
51
1f65958d 52#define MMU_USER_IDX 0
bcec36ea
AG
53
54#define MAX_EXT_QUEUE 16
5d69c547
CH
55#define MAX_IO_QUEUE 16
56#define MAX_MCHK_QUEUE 16
57
58#define PSW_MCHK_MASK 0x0004000000000000
59#define PSW_IO_MASK 0x0200000000000000
bcec36ea
AG
60
61typedef struct PSW {
62 uint64_t mask;
63 uint64_t addr;
64} PSW;
65
66typedef struct ExtQueue {
67 uint32_t code;
68 uint32_t param;
69 uint32_t param64;
70} ExtQueue;
10ec5117 71
5d69c547
CH
72typedef struct IOIntQueue {
73 uint16_t id;
74 uint16_t nr;
75 uint32_t parm;
76 uint32_t word;
77} IOIntQueue;
78
79typedef struct MchkQueue {
80 uint16_t type;
81} MchkQueue;
82
10ec5117 83typedef struct CPUS390XState {
1ac5889f 84 uint64_t regs[16]; /* GP registers */
fcb79802
EF
85 /*
86 * The floating point registers are part of the vector registers.
87 * vregs[0][0] -> vregs[15][0] are 16 floating point registers
88 */
89 CPU_DoubleU vregs[32][2]; /* vector registers */
1ac5889f 90 uint32_t aregs[16]; /* access registers */
10ec5117 91
1ac5889f
RH
92 uint32_t fpc; /* floating-point control register */
93 uint32_t cc_op;
10ec5117 94
10ec5117
AG
95 float_status fpu_status; /* passed to softfloat lib */
96
1ac5889f
RH
97 /* The low part of a 128-bit return, or remainder of a divide. */
98 uint64_t retxl;
99
bcec36ea 100 PSW psw;
10ec5117 101
bcec36ea
AG
102 uint64_t cc_src;
103 uint64_t cc_dst;
104 uint64_t cc_vr;
10ec5117
AG
105
106 uint64_t __excp_addr;
bcec36ea
AG
107 uint64_t psa;
108
109 uint32_t int_pgm_code;
d5a103cd 110 uint32_t int_pgm_ilen;
bcec36ea
AG
111
112 uint32_t int_svc_code;
d5a103cd 113 uint32_t int_svc_ilen;
bcec36ea 114
777c98c3
AJ
115 uint64_t per_address;
116 uint16_t per_perc_atmid;
117
bcec36ea
AG
118 uint64_t cregs[16]; /* control registers */
119
bcec36ea 120 ExtQueue ext_queue[MAX_EXT_QUEUE];
5d69c547
CH
121 IOIntQueue io_queue[MAX_IO_QUEUE][8];
122 MchkQueue mchk_queue[MAX_MCHK_QUEUE];
bcec36ea 123
5d69c547 124 int pending_int;
4e836781 125 int ext_index;
5d69c547
CH
126 int io_index[8];
127 int mchk_index;
128
129 uint64_t ckc;
130 uint64_t cputm;
131 uint32_t todpr;
4e836781 132
819bd309
DD
133 uint64_t pfault_token;
134 uint64_t pfault_compare;
135 uint64_t pfault_select;
136
44b0c0bb
CB
137 uint64_t gbea;
138 uint64_t pp;
139
9700230b
FZ
140 uint8_t riccb[64];
141
4e836781
AG
142 CPU_COMMON
143
bcec36ea
AG
144 /* reset does memset(0) up to here */
145
7f745b31
RH
146 uint32_t cpu_num;
147 uint32_t machine_type;
148
bcec36ea
AG
149 uint64_t tod_offset;
150 uint64_t tod_basetime;
151 QEMUTimer *tod_timer;
152
153 QEMUTimer *cpu_timer;
75973bfe
DH
154
155 /*
156 * The cpu state represents the logical state of a cpu. In contrast to other
157 * architectures, there is a difference between a halt and a stop on s390.
158 * If all cpus are either stopped (including check stop) or in the disabled
159 * wait state, the vm can be shut down.
160 */
161#define CPU_STATE_UNINITIALIZED 0x00
162#define CPU_STATE_STOPPED 0x01
163#define CPU_STATE_CHECK_STOP 0x02
164#define CPU_STATE_OPERATING 0x03
165#define CPU_STATE_LOAD 0x04
166 uint8_t cpu_state;
167
18ff9494
DH
168 /* currently processed sigp order */
169 uint8_t sigp_order;
170
10ec5117
AG
171} CPUS390XState;
172
c498d8e3
EF
173static inline CPU_DoubleU *get_freg(CPUS390XState *cs, int nr)
174{
fcb79802 175 return &cs->vregs[nr][0];
c498d8e3
EF
176}
177
a4a02f99
PB
178/**
179 * S390CPU:
180 * @env: #CPUS390XState.
181 *
182 * An S/390 CPU.
183 */
184struct S390CPU {
185 /*< private >*/
186 CPUState parent_obj;
187 /*< public >*/
188
189 CPUS390XState env;
190 int64_t id;
191 /* needed for live migration */
192 void *irqstate;
193 uint32_t irqstate_saved_size;
194};
195
196static inline S390CPU *s390_env_get_cpu(CPUS390XState *env)
197{
198 return container_of(env, S390CPU, env);
199}
200
201#define ENV_GET_CPU(e) CPU(s390_env_get_cpu(e))
202
203#define ENV_OFFSET offsetof(S390CPU, env)
204
205#ifndef CONFIG_USER_ONLY
206extern const struct VMStateDescription vmstate_s390_cpu;
207#endif
208
209void s390_cpu_do_interrupt(CPUState *cpu);
210bool s390_cpu_exec_interrupt(CPUState *cpu, int int_req);
211void s390_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
212 int flags);
213int s390_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
214 int cpuid, void *opaque);
215
216hwaddr s390_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
217hwaddr s390_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr);
218int s390_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
219int s390_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
220void s390_cpu_gdb_init(CPUState *cs);
221void s390x_cpu_debug_excp_handler(CPUState *cs);
222
a9c94277 223#include "sysemu/kvm.h"
564b863d 224
7b18aad5
CH
225/* distinguish between 24 bit and 31 bit addressing */
226#define HIGH_ORDER_BIT 0x80000000
227
bcec36ea
AG
228/* Interrupt Codes */
229/* Program Interrupts */
230#define PGM_OPERATION 0x0001
231#define PGM_PRIVILEGED 0x0002
232#define PGM_EXECUTE 0x0003
233#define PGM_PROTECTION 0x0004
234#define PGM_ADDRESSING 0x0005
235#define PGM_SPECIFICATION 0x0006
236#define PGM_DATA 0x0007
237#define PGM_FIXPT_OVERFLOW 0x0008
238#define PGM_FIXPT_DIVIDE 0x0009
239#define PGM_DEC_OVERFLOW 0x000a
240#define PGM_DEC_DIVIDE 0x000b
241#define PGM_HFP_EXP_OVERFLOW 0x000c
242#define PGM_HFP_EXP_UNDERFLOW 0x000d
243#define PGM_HFP_SIGNIFICANCE 0x000e
244#define PGM_HFP_DIVIDE 0x000f
245#define PGM_SEGMENT_TRANS 0x0010
246#define PGM_PAGE_TRANS 0x0011
247#define PGM_TRANS_SPEC 0x0012
248#define PGM_SPECIAL_OP 0x0013
249#define PGM_OPERAND 0x0015
250#define PGM_TRACE_TABLE 0x0016
251#define PGM_SPACE_SWITCH 0x001c
252#define PGM_HFP_SQRT 0x001d
253#define PGM_PC_TRANS_SPEC 0x001f
254#define PGM_AFX_TRANS 0x0020
255#define PGM_ASX_TRANS 0x0021
256#define PGM_LX_TRANS 0x0022
257#define PGM_EX_TRANS 0x0023
258#define PGM_PRIM_AUTH 0x0024
259#define PGM_SEC_AUTH 0x0025
260#define PGM_ALET_SPEC 0x0028
261#define PGM_ALEN_SPEC 0x0029
262#define PGM_ALE_SEQ 0x002a
263#define PGM_ASTE_VALID 0x002b
264#define PGM_ASTE_SEQ 0x002c
265#define PGM_EXT_AUTH 0x002d
266#define PGM_STACK_FULL 0x0030
267#define PGM_STACK_EMPTY 0x0031
268#define PGM_STACK_SPEC 0x0032
269#define PGM_STACK_TYPE 0x0033
270#define PGM_STACK_OP 0x0034
271#define PGM_ASCE_TYPE 0x0038
272#define PGM_REG_FIRST_TRANS 0x0039
273#define PGM_REG_SEC_TRANS 0x003a
274#define PGM_REG_THIRD_TRANS 0x003b
275#define PGM_MONITOR 0x0040
276#define PGM_PER 0x0080
277#define PGM_CRYPTO 0x0119
278
279/* External Interrupts */
280#define EXT_INTERRUPT_KEY 0x0040
281#define EXT_CLOCK_COMP 0x1004
282#define EXT_CPU_TIMER 0x1005
283#define EXT_MALFUNCTION 0x1200
284#define EXT_EMERGENCY 0x1201
285#define EXT_EXTERNAL_CALL 0x1202
286#define EXT_ETR 0x1406
287#define EXT_SERVICE 0x2401
288#define EXT_VIRTIO 0x2603
289
290/* PSW defines */
291#undef PSW_MASK_PER
292#undef PSW_MASK_DAT
293#undef PSW_MASK_IO
294#undef PSW_MASK_EXT
295#undef PSW_MASK_KEY
296#undef PSW_SHIFT_KEY
297#undef PSW_MASK_MCHECK
298#undef PSW_MASK_WAIT
299#undef PSW_MASK_PSTATE
300#undef PSW_MASK_ASC
301#undef PSW_MASK_CC
302#undef PSW_MASK_PM
303#undef PSW_MASK_64
29c6157c
CB
304#undef PSW_MASK_32
305#undef PSW_MASK_ESA_ADDR
bcec36ea
AG
306
307#define PSW_MASK_PER 0x4000000000000000ULL
308#define PSW_MASK_DAT 0x0400000000000000ULL
309#define PSW_MASK_IO 0x0200000000000000ULL
310#define PSW_MASK_EXT 0x0100000000000000ULL
311#define PSW_MASK_KEY 0x00F0000000000000ULL
312#define PSW_SHIFT_KEY 56
313#define PSW_MASK_MCHECK 0x0004000000000000ULL
314#define PSW_MASK_WAIT 0x0002000000000000ULL
315#define PSW_MASK_PSTATE 0x0001000000000000ULL
316#define PSW_MASK_ASC 0x0000C00000000000ULL
317#define PSW_MASK_CC 0x0000300000000000ULL
318#define PSW_MASK_PM 0x00000F0000000000ULL
319#define PSW_MASK_64 0x0000000100000000ULL
320#define PSW_MASK_32 0x0000000080000000ULL
29c6157c 321#define PSW_MASK_ESA_ADDR 0x000000007fffffffULL
bcec36ea
AG
322
323#undef PSW_ASC_PRIMARY
324#undef PSW_ASC_ACCREG
325#undef PSW_ASC_SECONDARY
326#undef PSW_ASC_HOME
327
328#define PSW_ASC_PRIMARY 0x0000000000000000ULL
329#define PSW_ASC_ACCREG 0x0000400000000000ULL
330#define PSW_ASC_SECONDARY 0x0000800000000000ULL
331#define PSW_ASC_HOME 0x0000C00000000000ULL
332
333/* tb flags */
334
335#define FLAG_MASK_PER (PSW_MASK_PER >> 32)
336#define FLAG_MASK_DAT (PSW_MASK_DAT >> 32)
337#define FLAG_MASK_IO (PSW_MASK_IO >> 32)
338#define FLAG_MASK_EXT (PSW_MASK_EXT >> 32)
339#define FLAG_MASK_KEY (PSW_MASK_KEY >> 32)
340#define FLAG_MASK_MCHECK (PSW_MASK_MCHECK >> 32)
341#define FLAG_MASK_WAIT (PSW_MASK_WAIT >> 32)
342#define FLAG_MASK_PSTATE (PSW_MASK_PSTATE >> 32)
343#define FLAG_MASK_ASC (PSW_MASK_ASC >> 32)
344#define FLAG_MASK_CC (PSW_MASK_CC >> 32)
345#define FLAG_MASK_PM (PSW_MASK_PM >> 32)
346#define FLAG_MASK_64 (PSW_MASK_64 >> 32)
347#define FLAG_MASK_32 0x00001000
348
c4400206 349/* Control register 0 bits */
c3edd628 350#define CR0_LOWPROT 0x0000000010000000ULL
c4400206
TH
351#define CR0_EDAT 0x0000000000800000ULL
352
4decd76d
AJ
353/* MMU */
354#define MMU_PRIMARY_IDX 0
355#define MMU_SECONDARY_IDX 1
356#define MMU_HOME_IDX 2
357
97ed5ccd 358static inline int cpu_mmu_index (CPUS390XState *env, bool ifetch)
10c339a0 359{
1f65958d
AJ
360 switch (env->psw.mask & PSW_MASK_ASC) {
361 case PSW_ASC_PRIMARY:
4decd76d 362 return MMU_PRIMARY_IDX;
1f65958d 363 case PSW_ASC_SECONDARY:
4decd76d 364 return MMU_SECONDARY_IDX;
1f65958d 365 case PSW_ASC_HOME:
4decd76d 366 return MMU_HOME_IDX;
1f65958d
AJ
367 case PSW_ASC_ACCREG:
368 /* Fallthrough: access register mode is not yet supported */
369 default:
370 abort();
bcec36ea 371 }
10c339a0
AG
372}
373
4decd76d
AJ
374static inline uint64_t cpu_mmu_idx_to_asc(int mmu_idx)
375{
376 switch (mmu_idx) {
377 case MMU_PRIMARY_IDX:
378 return PSW_ASC_PRIMARY;
379 case MMU_SECONDARY_IDX:
380 return PSW_ASC_SECONDARY;
381 case MMU_HOME_IDX:
382 return PSW_ASC_HOME;
383 default:
384 abort();
385 }
386}
387
a4e3ad19 388static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
89fee74a 389 target_ulong *cs_base, uint32_t *flags)
bcec36ea
AG
390{
391 *pc = env->psw.addr;
392 *cs_base = 0;
393 *flags = ((env->psw.mask >> 32) & ~FLAG_MASK_CC) |
394 ((env->psw.mask & PSW_MASK_32) ? FLAG_MASK_32 : 0);
395}
396
b60fae32
DH
397#define MAX_ILEN 6
398
d5a103cd
RH
399/* While the PoO talks about ILC (a number between 1-3) what is actually
400 stored in LowCore is shifted left one bit (an even between 2-6). As
401 this is the actual length of the insn and therefore more useful, that
402 is what we want to pass around and manipulate. To make sure that we
403 have applied this distinction universally, rename the "ILC" to "ILEN". */
404static inline int get_ilen(uint8_t opc)
bcec36ea
AG
405{
406 switch (opc >> 6) {
407 case 0:
d5a103cd 408 return 2;
bcec36ea
AG
409 case 1:
410 case 2:
d5a103cd
RH
411 return 4;
412 default:
413 return 6;
bcec36ea 414 }
bcec36ea
AG
415}
416
fb01bf4c
AJ
417/* PER bits from control register 9 */
418#define PER_CR9_EVENT_BRANCH 0x80000000
419#define PER_CR9_EVENT_IFETCH 0x40000000
420#define PER_CR9_EVENT_STORE 0x20000000
421#define PER_CR9_EVENT_STORE_REAL 0x08000000
422#define PER_CR9_EVENT_NULLIFICATION 0x01000000
423#define PER_CR9_CONTROL_BRANCH_ADDRESS 0x00800000
424#define PER_CR9_CONTROL_ALTERATION 0x00200000
425
426/* PER bits from the PER CODE/ATMID/AI in lowcore */
427#define PER_CODE_EVENT_BRANCH 0x8000
428#define PER_CODE_EVENT_IFETCH 0x4000
429#define PER_CODE_EVENT_STORE 0x2000
430#define PER_CODE_EVENT_STORE_REAL 0x0800
431#define PER_CODE_EVENT_NULLIFICATION 0x0100
432
a8f931a9
AJ
433/* Compute the ATMID field that is stored in the per_perc_atmid lowcore
434 entry when a PER exception is triggered. */
435static inline uint8_t get_per_atmid(CPUS390XState *env)
436{
437 return ((env->psw.mask & PSW_MASK_64) ? (1 << 7) : 0) |
438 ( (1 << 6) ) |
439 ((env->psw.mask & PSW_MASK_32) ? (1 << 5) : 0) |
440 ((env->psw.mask & PSW_MASK_DAT)? (1 << 4) : 0) |
441 ((env->psw.mask & PSW_ASC_SECONDARY)? (1 << 3) : 0) |
442 ((env->psw.mask & PSW_ASC_ACCREG)? (1 << 2) : 0);
443}
444
d453d103
AJ
445/* Check if an address is within the PER starting address and the PER
446 ending address. The address range might loop. */
447static inline bool get_per_in_range(CPUS390XState *env, uint64_t addr)
448{
449 if (env->cregs[10] <= env->cregs[11]) {
450 return env->cregs[10] <= addr && addr <= env->cregs[11];
451 } else {
452 return env->cregs[10] <= addr || addr <= env->cregs[11];
453 }
454}
455
d5a103cd
RH
456#ifndef CONFIG_USER_ONLY
457/* In several cases of runtime exceptions, we havn't recorded the true
458 instruction length. Use these codes when raising exceptions in order
459 to re-compute the length by examining the insn in memory. */
460#define ILEN_LATER 0x20
461#define ILEN_LATER_INC 0x21
dfebd7a7 462void trigger_pgm_exception(CPUS390XState *env, uint32_t code, uint32_t ilen);
d5a103cd 463#endif
bcec36ea 464
564b863d 465S390CPU *cpu_s390x_init(const char *cpu_model);
96b1a8bb
MR
466S390CPU *s390x_new_cpu(const char *cpu_model, int64_t id, Error **errp);
467S390CPU *cpu_s390x_create(const char *cpu_model, Error **errp);
bcec36ea 468void s390x_translate_init(void);
10ec5117
AG
469
470/* you can call this signal handler from your SIGBUS and SIGSEGV
471 signal handlers to inform the virtual CPU of exceptions. non zero
472 is returned if the signal was handled by the virtual CPU. */
473int cpu_s390x_signal_handler(int host_signum, void *pinfo,
474 void *puc);
7510454e
AF
475int s390_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
476 int mmu_idx);
10ec5117 477
3f10341f 478
10c339a0 479#ifndef CONFIG_USER_ONLY
3f10341f
DH
480void do_restart_interrupt(CPUS390XState *env);
481
6cb1e49d
AY
482static inline hwaddr decode_basedisp_s(CPUS390XState *env, uint32_t ipb,
483 uint8_t *ar)
7b18aad5
CH
484{
485 hwaddr addr = 0;
486 uint8_t reg;
487
488 reg = ipb >> 28;
489 if (reg > 0) {
490 addr = env->regs[reg];
491 }
492 addr += (ipb >> 16) & 0xfff;
6cb1e49d
AY
493 if (ar) {
494 *ar = reg;
495 }
7b18aad5
CH
496
497 return addr;
498}
499
638129ff
CH
500/* Base/displacement are at the same locations. */
501#define decode_basedisp_rs decode_basedisp_s
502
85ca3371
DH
503/* helper functions for run_on_cpu() */
504static inline void s390_do_cpu_reset(void *arg)
505{
506 CPUState *cs = arg;
507 S390CPUClass *scc = S390_CPU_GET_CLASS(cs);
508
509 scc->cpu_reset(cs);
510}
511static inline void s390_do_cpu_full_reset(void *arg)
512{
513 CPUState *cs = arg;
514
515 cpu_reset(cs);
516}
517
8f22e0df
AF
518void s390x_tod_timer(void *opaque);
519void s390x_cpu_timer(void *opaque);
520
28e942f8 521int s390_virtio_hypercall(CPUS390XState *env);
bcec36ea 522
1f206266 523#ifdef CONFIG_KVM
de13d216 524void kvm_s390_service_interrupt(uint32_t parm);
66ad0893
CH
525void kvm_s390_vcpu_interrupt(S390CPU *cpu, struct kvm_s390_irq *irq);
526void kvm_s390_floating_interrupt(struct kvm_s390_irq *irq);
bbd8bb8e 527int kvm_s390_inject_flic(struct kvm_s390_irq *irq);
801cdd35 528void kvm_s390_access_exception(S390CPU *cpu, uint16_t code, uint64_t te_code);
6cb1e49d
AY
529int kvm_s390_mem_op(S390CPU *cpu, vaddr addr, uint8_t ar, void *hostbuf,
530 int len, bool is_write);
3f9e59bb
JH
531int kvm_s390_get_clock(uint8_t *tod_high, uint64_t *tod_clock);
532int kvm_s390_set_clock(uint8_t *tod_high, uint64_t *tod_clock);
1f206266 533#else
de13d216 534static inline void kvm_s390_service_interrupt(uint32_t parm)
79afc36d
CH
535{
536}
3f9e59bb
JH
537static inline int kvm_s390_get_clock(uint8_t *tod_high, uint64_t *tod_low)
538{
539 return -ENOSYS;
540}
541static inline int kvm_s390_set_clock(uint8_t *tod_high, uint64_t *tod_low)
542{
543 return -ENOSYS;
544}
6cb1e49d
AY
545static inline int kvm_s390_mem_op(S390CPU *cpu, vaddr addr, uint8_t ar,
546 void *hostbuf, int len, bool is_write)
a9bcd1b8
TH
547{
548 return -ENOSYS;
549}
801cdd35
TH
550static inline void kvm_s390_access_exception(S390CPU *cpu, uint16_t code,
551 uint64_t te_code)
552{
553}
1f206266 554#endif
3f9e59bb
JH
555
556static inline int s390_get_clock(uint8_t *tod_high, uint64_t *tod_low)
557{
558 if (kvm_enabled()) {
559 return kvm_s390_get_clock(tod_high, tod_low);
560 }
561 /* Fixme TCG */
562 *tod_high = 0;
563 *tod_low = 0;
564 return 0;
565}
566
567static inline int s390_set_clock(uint8_t *tod_high, uint64_t *tod_low)
568{
569 if (kvm_enabled()) {
570 return kvm_s390_set_clock(tod_high, tod_low);
571 }
572 /* Fixme TCG */
573 return 0;
574}
575
45fa769b 576S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
eb24f7c6
DH
577unsigned int s390_cpu_halt(S390CPU *cpu);
578void s390_cpu_unhalt(S390CPU *cpu);
579unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu);
18ff9494
DH
580static inline uint8_t s390_cpu_get_state(S390CPU *cpu)
581{
582 return cpu->env.cpu_state;
583}
bcec36ea 584
3f9e59bb
JH
585void gtod_save(QEMUFile *f, void *opaque);
586int gtod_load(QEMUFile *f, void *opaque, int version_id);
587
bd3f16ac
PB
588void cpu_inject_ext(S390CPU *cpu, uint32_t code, uint32_t param,
589 uint64_t param64);
590
591/* ioinst.c */
592void ioinst_handle_xsch(S390CPU *cpu, uint64_t reg1);
593void ioinst_handle_csch(S390CPU *cpu, uint64_t reg1);
594void ioinst_handle_hsch(S390CPU *cpu, uint64_t reg1);
595void ioinst_handle_msch(S390CPU *cpu, uint64_t reg1, uint32_t ipb);
596void ioinst_handle_ssch(S390CPU *cpu, uint64_t reg1, uint32_t ipb);
597void ioinst_handle_stcrw(S390CPU *cpu, uint32_t ipb);
598void ioinst_handle_stsch(S390CPU *cpu, uint64_t reg1, uint32_t ipb);
599int ioinst_handle_tsch(S390CPU *cpu, uint64_t reg1, uint32_t ipb);
600void ioinst_handle_chsc(S390CPU *cpu, uint32_t ipb);
601int ioinst_handle_tpi(S390CPU *cpu, uint32_t ipb);
602void ioinst_handle_schm(S390CPU *cpu, uint64_t reg1, uint64_t reg2,
603 uint32_t ipb);
604void ioinst_handle_rsch(S390CPU *cpu, uint64_t reg1);
605void ioinst_handle_rchp(S390CPU *cpu, uint64_t reg1);
606void ioinst_handle_sal(S390CPU *cpu, uint64_t reg1);
607
000a1a38
CB
608/* service interrupts are floating therefore we must not pass an cpustate */
609void s390_sclp_extint(uint32_t parm);
610
ef81522b 611#else
eb24f7c6
DH
612static inline unsigned int s390_cpu_halt(S390CPU *cpu)
613{
614 return 0;
615}
616
617static inline void s390_cpu_unhalt(S390CPU *cpu)
ef81522b
AG
618{
619}
620
eb24f7c6 621static inline unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu)
ef81522b
AG
622{
623 return 0;
624}
10c339a0 625#endif
bcec36ea
AG
626void cpu_lock(void);
627void cpu_unlock(void);
10c339a0 628
d9f090ec 629extern void subsystem_reset(void);
7b18aad5 630
2994fd96 631#define cpu_init(model) CPU(cpu_s390x_init(model))
bcec36ea 632#define cpu_signal_handler cpu_s390x_signal_handler
10ec5117 633
904e5fd5
VM
634void s390_cpu_list(FILE *f, fprintf_function cpu_fprintf);
635#define cpu_list s390_cpu_list
41868f84
DH
636void s390_realize_cpu_model(CPUState *cs, Error **errp);
637ObjectClass *s390_cpu_class_by_name(const char *name);
904e5fd5 638
bcec36ea
AG
639#define EXCP_EXT 1 /* external interrupt */
640#define EXCP_SVC 2 /* supervisor call (syscall) */
641#define EXCP_PGM 3 /* program interruption */
5d69c547
CH
642#define EXCP_IO 7 /* I/O interrupt */
643#define EXCP_MCHK 8 /* machine check */
bcec36ea 644
bcec36ea
AG
645#define INTERRUPT_EXT (1 << 0)
646#define INTERRUPT_TOD (1 << 1)
647#define INTERRUPT_CPUTIMER (1 << 2)
5d69c547
CH
648#define INTERRUPT_IO (1 << 3)
649#define INTERRUPT_MCHK (1 << 4)
10c339a0
AG
650
651/* Program Status Word. */
652#define S390_PSWM_REGNUM 0
653#define S390_PSWA_REGNUM 1
654/* General Purpose Registers. */
655#define S390_R0_REGNUM 2
656#define S390_R1_REGNUM 3
657#define S390_R2_REGNUM 4
658#define S390_R3_REGNUM 5
659#define S390_R4_REGNUM 6
660#define S390_R5_REGNUM 7
661#define S390_R6_REGNUM 8
662#define S390_R7_REGNUM 9
663#define S390_R8_REGNUM 10
664#define S390_R9_REGNUM 11
665#define S390_R10_REGNUM 12
666#define S390_R11_REGNUM 13
667#define S390_R12_REGNUM 14
668#define S390_R13_REGNUM 15
669#define S390_R14_REGNUM 16
670#define S390_R15_REGNUM 17
73d510c9
DH
671/* Total Core Registers. */
672#define S390_NUM_CORE_REGS 18
10c339a0 673
bcec36ea
AG
674/* CC optimization */
675
676enum cc_op {
677 CC_OP_CONST0 = 0, /* CC is 0 */
678 CC_OP_CONST1, /* CC is 1 */
679 CC_OP_CONST2, /* CC is 2 */
680 CC_OP_CONST3, /* CC is 3 */
681
682 CC_OP_DYNAMIC, /* CC calculation defined by env->cc_op */
683 CC_OP_STATIC, /* CC value is env->cc_op */
684
685 CC_OP_NZ, /* env->cc_dst != 0 */
686 CC_OP_LTGT_32, /* signed less/greater than (32bit) */
687 CC_OP_LTGT_64, /* signed less/greater than (64bit) */
688 CC_OP_LTUGTU_32, /* unsigned less/greater than (32bit) */
689 CC_OP_LTUGTU_64, /* unsigned less/greater than (64bit) */
690 CC_OP_LTGT0_32, /* signed less/greater than 0 (32bit) */
691 CC_OP_LTGT0_64, /* signed less/greater than 0 (64bit) */
692
693 CC_OP_ADD_64, /* overflow on add (64bit) */
694 CC_OP_ADDU_64, /* overflow on unsigned add (64bit) */
4e4bb438 695 CC_OP_ADDC_64, /* overflow on unsigned add-carry (64bit) */
e7d81004
SW
696 CC_OP_SUB_64, /* overflow on subtraction (64bit) */
697 CC_OP_SUBU_64, /* overflow on unsigned subtraction (64bit) */
4e4bb438 698 CC_OP_SUBB_64, /* overflow on unsigned sub-borrow (64bit) */
bcec36ea
AG
699 CC_OP_ABS_64, /* sign eval on abs (64bit) */
700 CC_OP_NABS_64, /* sign eval on nabs (64bit) */
701
702 CC_OP_ADD_32, /* overflow on add (32bit) */
703 CC_OP_ADDU_32, /* overflow on unsigned add (32bit) */
4e4bb438 704 CC_OP_ADDC_32, /* overflow on unsigned add-carry (32bit) */
e7d81004
SW
705 CC_OP_SUB_32, /* overflow on subtraction (32bit) */
706 CC_OP_SUBU_32, /* overflow on unsigned subtraction (32bit) */
4e4bb438 707 CC_OP_SUBB_32, /* overflow on unsigned sub-borrow (32bit) */
bcec36ea
AG
708 CC_OP_ABS_32, /* sign eval on abs (64bit) */
709 CC_OP_NABS_32, /* sign eval on nabs (64bit) */
710
711 CC_OP_COMP_32, /* complement */
712 CC_OP_COMP_64, /* complement */
713
714 CC_OP_TM_32, /* test under mask (32bit) */
715 CC_OP_TM_64, /* test under mask (64bit) */
716
bcec36ea
AG
717 CC_OP_NZ_F32, /* FP dst != 0 (32bit) */
718 CC_OP_NZ_F64, /* FP dst != 0 (64bit) */
587626f8 719 CC_OP_NZ_F128, /* FP dst != 0 (128bit) */
bcec36ea
AG
720
721 CC_OP_ICM, /* insert characters under mask */
cbe24bfa
RH
722 CC_OP_SLA_32, /* Calculate shift left signed (32bit) */
723 CC_OP_SLA_64, /* Calculate shift left signed (64bit) */
102bf2c6 724 CC_OP_FLOGR, /* find leftmost one */
bcec36ea
AG
725 CC_OP_MAX
726};
727
728static const char *cc_names[] = {
729 [CC_OP_CONST0] = "CC_OP_CONST0",
730 [CC_OP_CONST1] = "CC_OP_CONST1",
731 [CC_OP_CONST2] = "CC_OP_CONST2",
732 [CC_OP_CONST3] = "CC_OP_CONST3",
733 [CC_OP_DYNAMIC] = "CC_OP_DYNAMIC",
734 [CC_OP_STATIC] = "CC_OP_STATIC",
735 [CC_OP_NZ] = "CC_OP_NZ",
736 [CC_OP_LTGT_32] = "CC_OP_LTGT_32",
737 [CC_OP_LTGT_64] = "CC_OP_LTGT_64",
738 [CC_OP_LTUGTU_32] = "CC_OP_LTUGTU_32",
739 [CC_OP_LTUGTU_64] = "CC_OP_LTUGTU_64",
740 [CC_OP_LTGT0_32] = "CC_OP_LTGT0_32",
741 [CC_OP_LTGT0_64] = "CC_OP_LTGT0_64",
742 [CC_OP_ADD_64] = "CC_OP_ADD_64",
743 [CC_OP_ADDU_64] = "CC_OP_ADDU_64",
4e4bb438 744 [CC_OP_ADDC_64] = "CC_OP_ADDC_64",
bcec36ea
AG
745 [CC_OP_SUB_64] = "CC_OP_SUB_64",
746 [CC_OP_SUBU_64] = "CC_OP_SUBU_64",
4e4bb438 747 [CC_OP_SUBB_64] = "CC_OP_SUBB_64",
bcec36ea
AG
748 [CC_OP_ABS_64] = "CC_OP_ABS_64",
749 [CC_OP_NABS_64] = "CC_OP_NABS_64",
750 [CC_OP_ADD_32] = "CC_OP_ADD_32",
751 [CC_OP_ADDU_32] = "CC_OP_ADDU_32",
4e4bb438 752 [CC_OP_ADDC_32] = "CC_OP_ADDC_32",
bcec36ea
AG
753 [CC_OP_SUB_32] = "CC_OP_SUB_32",
754 [CC_OP_SUBU_32] = "CC_OP_SUBU_32",
4e4bb438 755 [CC_OP_SUBB_32] = "CC_OP_SUBB_32",
bcec36ea
AG
756 [CC_OP_ABS_32] = "CC_OP_ABS_32",
757 [CC_OP_NABS_32] = "CC_OP_NABS_32",
758 [CC_OP_COMP_32] = "CC_OP_COMP_32",
759 [CC_OP_COMP_64] = "CC_OP_COMP_64",
760 [CC_OP_TM_32] = "CC_OP_TM_32",
761 [CC_OP_TM_64] = "CC_OP_TM_64",
bcec36ea
AG
762 [CC_OP_NZ_F32] = "CC_OP_NZ_F32",
763 [CC_OP_NZ_F64] = "CC_OP_NZ_F64",
587626f8 764 [CC_OP_NZ_F128] = "CC_OP_NZ_F128",
bcec36ea 765 [CC_OP_ICM] = "CC_OP_ICM",
cbe24bfa
RH
766 [CC_OP_SLA_32] = "CC_OP_SLA_32",
767 [CC_OP_SLA_64] = "CC_OP_SLA_64",
102bf2c6 768 [CC_OP_FLOGR] = "CC_OP_FLOGR",
bcec36ea
AG
769};
770
771static inline const char *cc_name(int cc_op)
772{
773 return cc_names[cc_op];
774}
775
3d0a615f
TH
776static inline void setcc(S390CPU *cpu, uint64_t cc)
777{
778 CPUS390XState *env = &cpu->env;
779
780 env->psw.mask &= ~(3ull << 44);
781 env->psw.mask |= (cc & 3) << 44;
06e3c077 782 env->cc_op = cc;
3d0a615f
TH
783}
784
bcec36ea
AG
785typedef struct LowCore
786{
787 /* prefix area: defined by architecture */
788 uint32_t ccw1[2]; /* 0x000 */
789 uint32_t ccw2[4]; /* 0x008 */
790 uint8_t pad1[0x80-0x18]; /* 0x018 */
791 uint32_t ext_params; /* 0x080 */
792 uint16_t cpu_addr; /* 0x084 */
793 uint16_t ext_int_code; /* 0x086 */
d5a103cd 794 uint16_t svc_ilen; /* 0x088 */
bcec36ea 795 uint16_t svc_code; /* 0x08a */
d5a103cd 796 uint16_t pgm_ilen; /* 0x08c */
bcec36ea
AG
797 uint16_t pgm_code; /* 0x08e */
798 uint32_t data_exc_code; /* 0x090 */
799 uint16_t mon_class_num; /* 0x094 */
800 uint16_t per_perc_atmid; /* 0x096 */
801 uint64_t per_address; /* 0x098 */
802 uint8_t exc_access_id; /* 0x0a0 */
803 uint8_t per_access_id; /* 0x0a1 */
804 uint8_t op_access_id; /* 0x0a2 */
805 uint8_t ar_access_id; /* 0x0a3 */
806 uint8_t pad2[0xA8-0xA4]; /* 0x0a4 */
807 uint64_t trans_exc_code; /* 0x0a8 */
808 uint64_t monitor_code; /* 0x0b0 */
809 uint16_t subchannel_id; /* 0x0b8 */
810 uint16_t subchannel_nr; /* 0x0ba */
811 uint32_t io_int_parm; /* 0x0bc */
812 uint32_t io_int_word; /* 0x0c0 */
813 uint8_t pad3[0xc8-0xc4]; /* 0x0c4 */
814 uint32_t stfl_fac_list; /* 0x0c8 */
815 uint8_t pad4[0xe8-0xcc]; /* 0x0cc */
816 uint32_t mcck_interruption_code[2]; /* 0x0e8 */
817 uint8_t pad5[0xf4-0xf0]; /* 0x0f0 */
818 uint32_t external_damage_code; /* 0x0f4 */
819 uint64_t failing_storage_address; /* 0x0f8 */
3da0ab35
AJ
820 uint8_t pad6[0x110-0x100]; /* 0x100 */
821 uint64_t per_breaking_event_addr; /* 0x110 */
822 uint8_t pad7[0x120-0x118]; /* 0x118 */
bcec36ea
AG
823 PSW restart_old_psw; /* 0x120 */
824 PSW external_old_psw; /* 0x130 */
825 PSW svc_old_psw; /* 0x140 */
826 PSW program_old_psw; /* 0x150 */
827 PSW mcck_old_psw; /* 0x160 */
828 PSW io_old_psw; /* 0x170 */
3da0ab35 829 uint8_t pad8[0x1a0-0x180]; /* 0x180 */
3f10341f 830 PSW restart_new_psw; /* 0x1a0 */
bcec36ea
AG
831 PSW external_new_psw; /* 0x1b0 */
832 PSW svc_new_psw; /* 0x1c0 */
833 PSW program_new_psw; /* 0x1d0 */
834 PSW mcck_new_psw; /* 0x1e0 */
835 PSW io_new_psw; /* 0x1f0 */
836 PSW return_psw; /* 0x200 */
837 uint8_t irb[64]; /* 0x210 */
838 uint64_t sync_enter_timer; /* 0x250 */
839 uint64_t async_enter_timer; /* 0x258 */
840 uint64_t exit_timer; /* 0x260 */
841 uint64_t last_update_timer; /* 0x268 */
842 uint64_t user_timer; /* 0x270 */
843 uint64_t system_timer; /* 0x278 */
844 uint64_t last_update_clock; /* 0x280 */
845 uint64_t steal_clock; /* 0x288 */
846 PSW return_mcck_psw; /* 0x290 */
3da0ab35 847 uint8_t pad9[0xc00-0x2a0]; /* 0x2a0 */
bcec36ea
AG
848 /* System info area */
849 uint64_t save_area[16]; /* 0xc00 */
3da0ab35 850 uint8_t pad10[0xd40-0xc80]; /* 0xc80 */
bcec36ea
AG
851 uint64_t kernel_stack; /* 0xd40 */
852 uint64_t thread_info; /* 0xd48 */
853 uint64_t async_stack; /* 0xd50 */
854 uint64_t kernel_asce; /* 0xd58 */
855 uint64_t user_asce; /* 0xd60 */
856 uint64_t panic_stack; /* 0xd68 */
857 uint64_t user_exec_asce; /* 0xd70 */
3da0ab35 858 uint8_t pad11[0xdc0-0xd78]; /* 0xd78 */
bcec36ea
AG
859
860 /* SMP info area: defined by DJB */
861 uint64_t clock_comparator; /* 0xdc0 */
862 uint64_t ext_call_fast; /* 0xdc8 */
863 uint64_t percpu_offset; /* 0xdd0 */
864 uint64_t current_task; /* 0xdd8 */
865 uint32_t softirq_pending; /* 0xde0 */
866 uint32_t pad_0x0de4; /* 0xde4 */
867 uint64_t int_clock; /* 0xde8 */
868 uint8_t pad12[0xe00-0xdf0]; /* 0xdf0 */
869
870 /* 0xe00 is used as indicator for dump tools */
871 /* whether the kernel died with panic() or not */
872 uint32_t panic_magic; /* 0xe00 */
873
874 uint8_t pad13[0x11b8-0xe04]; /* 0xe04 */
875
876 /* 64 bit extparam used for pfault, diag 250 etc */
877 uint64_t ext_params2; /* 0x11B8 */
878
879 uint8_t pad14[0x1200-0x11C0]; /* 0x11C0 */
880
881 /* System info area */
882
883 uint64_t floating_pt_save_area[16]; /* 0x1200 */
884 uint64_t gpregs_save_area[16]; /* 0x1280 */
885 uint32_t st_status_fixed_logout[4]; /* 0x1300 */
886 uint8_t pad15[0x1318-0x1310]; /* 0x1310 */
887 uint32_t prefixreg_save_area; /* 0x1318 */
888 uint32_t fpt_creg_save_area; /* 0x131c */
889 uint8_t pad16[0x1324-0x1320]; /* 0x1320 */
890 uint32_t tod_progreg_save_area; /* 0x1324 */
891 uint32_t cpu_timer_save_area[2]; /* 0x1328 */
892 uint32_t clock_comp_save_area[2]; /* 0x1330 */
893 uint8_t pad17[0x1340-0x1338]; /* 0x1338 */
894 uint32_t access_regs_save_area[16]; /* 0x1340 */
895 uint64_t cregs_save_area[16]; /* 0x1380 */
896
897 /* align to the top of the prefix area */
898
899 uint8_t pad18[0x2000-0x1400]; /* 0x1400 */
541dc0d4 900} QEMU_PACKED LowCore;
bcec36ea
AG
901
902/* STSI */
903#define STSI_LEVEL_MASK 0x00000000f0000000ULL
904#define STSI_LEVEL_CURRENT 0x0000000000000000ULL
905#define STSI_LEVEL_1 0x0000000010000000ULL
906#define STSI_LEVEL_2 0x0000000020000000ULL
907#define STSI_LEVEL_3 0x0000000030000000ULL
908#define STSI_R0_RESERVED_MASK 0x000000000fffff00ULL
909#define STSI_R0_SEL1_MASK 0x00000000000000ffULL
910#define STSI_R1_RESERVED_MASK 0x00000000ffff0000ULL
911#define STSI_R1_SEL2_MASK 0x000000000000ffffULL
912
913/* Basic Machine Configuration */
914struct sysib_111 {
915 uint32_t res1[8];
916 uint8_t manuf[16];
917 uint8_t type[4];
918 uint8_t res2[12];
919 uint8_t model[16];
920 uint8_t sequence[16];
921 uint8_t plant[4];
922 uint8_t res3[156];
923};
924
925/* Basic Machine CPU */
926struct sysib_121 {
927 uint32_t res1[80];
928 uint8_t sequence[16];
929 uint8_t plant[4];
930 uint8_t res2[2];
931 uint16_t cpu_addr;
932 uint8_t res3[152];
933};
934
935/* Basic Machine CPUs */
936struct sysib_122 {
937 uint8_t res1[32];
938 uint32_t capability;
939 uint16_t total_cpus;
940 uint16_t active_cpus;
941 uint16_t standby_cpus;
942 uint16_t reserved_cpus;
943 uint16_t adjustments[2026];
944};
945
946/* LPAR CPU */
947struct sysib_221 {
948 uint32_t res1[80];
949 uint8_t sequence[16];
950 uint8_t plant[4];
951 uint16_t cpu_id;
952 uint16_t cpu_addr;
953 uint8_t res3[152];
954};
955
956/* LPAR CPUs */
957struct sysib_222 {
958 uint32_t res1[32];
959 uint16_t lpar_num;
960 uint8_t res2;
961 uint8_t lcpuc;
962 uint16_t total_cpus;
963 uint16_t conf_cpus;
964 uint16_t standby_cpus;
965 uint16_t reserved_cpus;
966 uint8_t name[8];
967 uint32_t caf;
968 uint8_t res3[16];
969 uint16_t dedicated_cpus;
970 uint16_t shared_cpus;
971 uint8_t res4[180];
972};
973
974/* VM CPUs */
975struct sysib_322 {
976 uint8_t res1[31];
977 uint8_t count;
978 struct {
979 uint8_t res2[4];
980 uint16_t total_cpus;
981 uint16_t conf_cpus;
982 uint16_t standby_cpus;
983 uint16_t reserved_cpus;
984 uint8_t name[8];
985 uint32_t caf;
986 uint8_t cpi[16];
f07177a5
ET
987 uint8_t res5[3];
988 uint8_t ext_name_encoding;
989 uint32_t res3;
990 uint8_t uuid[16];
bcec36ea 991 } vm[8];
f07177a5
ET
992 uint8_t res4[1504];
993 uint8_t ext_names[8][256];
bcec36ea
AG
994};
995
996/* MMU defines */
997#define _ASCE_ORIGIN ~0xfffULL /* segment table origin */
998#define _ASCE_SUBSPACE 0x200 /* subspace group control */
999#define _ASCE_PRIVATE_SPACE 0x100 /* private space control */
1000#define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */
1001#define _ASCE_SPACE_SWITCH 0x40 /* space switch event */
1002#define _ASCE_REAL_SPACE 0x20 /* real space control */
1003#define _ASCE_TYPE_MASK 0x0c /* asce table type mask */
1004#define _ASCE_TYPE_REGION1 0x0c /* region first table type */
1005#define _ASCE_TYPE_REGION2 0x08 /* region second table type */
1006#define _ASCE_TYPE_REGION3 0x04 /* region third table type */
1007#define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */
1008#define _ASCE_TABLE_LENGTH 0x03 /* region table length */
1009
1010#define _REGION_ENTRY_ORIGIN ~0xfffULL /* region/segment table origin */
43d49b01 1011#define _REGION_ENTRY_RO 0x200 /* region/segment protection bit */
5d180439 1012#define _REGION_ENTRY_TF 0xc0 /* region/segment table offset */
bcec36ea
AG
1013#define _REGION_ENTRY_INV 0x20 /* invalid region table entry */
1014#define _REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */
1015#define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */
1016#define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */
1017#define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */
1018#define _REGION_ENTRY_LENGTH 0x03 /* region third length */
1019
1020#define _SEGMENT_ENTRY_ORIGIN ~0x7ffULL /* segment table origin */
c4400206 1021#define _SEGMENT_ENTRY_FC 0x400 /* format control */
bcec36ea
AG
1022#define _SEGMENT_ENTRY_RO 0x200 /* page protection bit */
1023#define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */
1024
1025#define _PAGE_RO 0x200 /* HW read-only bit */
1026#define _PAGE_INVALID 0x400 /* HW invalid bit */
b4ecbf80 1027#define _PAGE_RES0 0x800 /* bit must be zero */
bcec36ea 1028
b9959138
AG
1029#define SK_C (0x1 << 1)
1030#define SK_R (0x1 << 2)
1031#define SK_F (0x1 << 3)
1032#define SK_ACC_MASK (0xf << 4)
bcec36ea 1033
5172b780 1034/* SIGP order codes */
bcec36ea
AG
1035#define SIGP_SENSE 0x01
1036#define SIGP_EXTERNAL_CALL 0x02
1037#define SIGP_EMERGENCY 0x03
1038#define SIGP_START 0x04
1039#define SIGP_STOP 0x05
1040#define SIGP_RESTART 0x06
1041#define SIGP_STOP_STORE_STATUS 0x09
1042#define SIGP_INITIAL_CPU_RESET 0x0b
1043#define SIGP_CPU_RESET 0x0c
1044#define SIGP_SET_PREFIX 0x0d
1045#define SIGP_STORE_STATUS_ADDR 0x0e
1046#define SIGP_SET_ARCH 0x12
abec5356 1047#define SIGP_STORE_ADTL_STATUS 0x17
bcec36ea 1048
5172b780
DH
1049/* SIGP condition codes */
1050#define SIGP_CC_ORDER_CODE_ACCEPTED 0
1051#define SIGP_CC_STATUS_STORED 1
1052#define SIGP_CC_BUSY 2
1053#define SIGP_CC_NOT_OPERATIONAL 3
1054
1055/* SIGP status bits */
bcec36ea
AG
1056#define SIGP_STAT_EQUIPMENT_CHECK 0x80000000UL
1057#define SIGP_STAT_INCORRECT_STATE 0x00000200UL
1058#define SIGP_STAT_INVALID_PARAMETER 0x00000100UL
1059#define SIGP_STAT_EXT_CALL_PENDING 0x00000080UL
1060#define SIGP_STAT_STOPPED 0x00000040UL
1061#define SIGP_STAT_OPERATOR_INTERV 0x00000020UL
1062#define SIGP_STAT_CHECK_STOP 0x00000010UL
1063#define SIGP_STAT_INOPERATIVE 0x00000004UL
1064#define SIGP_STAT_INVALID_ORDER 0x00000002UL
1065#define SIGP_STAT_RECEIVER_CHECK 0x00000001UL
1066
18ff9494
DH
1067/* SIGP SET ARCHITECTURE modes */
1068#define SIGP_MODE_ESA_S390 0
1069#define SIGP_MODE_Z_ARCH_TRANS_ALL_PSW 1
1070#define SIGP_MODE_Z_ARCH_TRANS_CUR_PSW 2
1071
a4e3ad19
AF
1072void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr);
1073int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
e3e09d87 1074 target_ulong *raddr, int *flags, bool exc);
6e252802 1075int sclp_service_call(CPUS390XState *env, uint64_t sccb, uint32_t code);
a4e3ad19 1076uint32_t calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t src, uint64_t dst,
bcec36ea 1077 uint64_t vr);
311918b9 1078void s390_cpu_recompute_watchpoints(CPUState *cs);
bcec36ea 1079
6cb1e49d
AY
1080int s390_cpu_virt_mem_rw(S390CPU *cpu, vaddr laddr, uint8_t ar, void *hostbuf,
1081 int len, bool is_write);
c3edd628 1082
6cb1e49d
AY
1083#define s390_cpu_virt_mem_read(cpu, laddr, ar, dest, len) \
1084 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, false)
1085#define s390_cpu_virt_mem_write(cpu, laddr, ar, dest, len) \
1086 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, true)
1087#define s390_cpu_virt_mem_check_write(cpu, laddr, ar, len) \
1088 s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, true)
c3edd628 1089
bcec36ea
AG
1090/* The value of the TOD clock for 1.1.1970. */
1091#define TOD_UNIX_EPOCH 0x7d91048bca000000ULL
1092
1093/* Converts ns to s390's clock format */
1094static inline uint64_t time2tod(uint64_t ns) {
1095 return (ns << 9) / 125;
1096}
1097
9cb32c44
AJ
1098/* Converts s390's clock format to ns */
1099static inline uint64_t tod2time(uint64_t t) {
1100 return (t * 125) >> 9;
1101}
1102
b6fe0124
MR
1103/* from s390-virtio-ccw */
1104#define MEM_SECTION_SIZE 0x10000000UL
1def6656 1105#define MAX_AVAIL_SLOTS 32
b6fe0124 1106
e72ca652 1107/* fpu_helper.c */
e72ca652
BS
1108uint32_t set_cc_nz_f32(float32 v);
1109uint32_t set_cc_nz_f64(float64 v);
587626f8 1110uint32_t set_cc_nz_f128(float128 v);
e72ca652 1111
aea1e885 1112/* misc_helper.c */
268846ba 1113#ifndef CONFIG_USER_ONLY
8fc639af 1114int handle_diag_288(CPUS390XState *env, uint64_t r1, uint64_t r3);
268846ba
ED
1115void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3);
1116#endif
d5a103cd 1117void program_interrupt(CPUS390XState *env, uint32_t code, int ilen);
b4e2bd35
RH
1118void QEMU_NORETURN runtime_exception(CPUS390XState *env, int excp,
1119 uintptr_t retaddr);
a78b0504 1120
09b99878 1121#ifdef CONFIG_KVM
de13d216 1122void kvm_s390_io_interrupt(uint16_t subchannel_id,
09b99878
CH
1123 uint16_t subchannel_nr, uint32_t io_int_parm,
1124 uint32_t io_int_word);
de13d216 1125void kvm_s390_crw_mchk(void);
09b99878 1126void kvm_s390_enable_css_support(S390CPU *cpu);
cc3ac9c4
CH
1127int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch,
1128 int vq, bool assign);
7f7f9752 1129int kvm_s390_cpu_restart(S390CPU *cpu);
1def6656 1130int kvm_s390_get_memslot_count(KVMState *s);
1cd4e0f6 1131void kvm_s390_cmma_reset(void);
c9e659c9 1132int kvm_s390_set_cpu_state(S390CPU *cpu, uint8_t cpu_state);
99607144 1133void kvm_s390_reset_vcpu(S390CPU *cpu);
a310b283 1134int kvm_s390_set_mem_limit(KVMState *s, uint64_t new_limit, uint64_t *hw_limit);
3cda44f7
JF
1135void kvm_s390_vcpu_interrupt_pre_save(S390CPU *cpu);
1136int kvm_s390_vcpu_interrupt_post_load(S390CPU *cpu);
9700230b 1137int kvm_s390_get_ri(void);
4ab72920 1138void kvm_s390_crypto_reset(void);
09b99878 1139#else
de13d216 1140static inline void kvm_s390_io_interrupt(uint16_t subchannel_id,
df1fe5bb
CH
1141 uint16_t subchannel_nr,
1142 uint32_t io_int_parm,
1143 uint32_t io_int_word)
1144{
1145}
de13d216 1146static inline void kvm_s390_crw_mchk(void)
df1fe5bb
CH
1147{
1148}
09b99878
CH
1149static inline void kvm_s390_enable_css_support(S390CPU *cpu)
1150{
1151}
cc3ac9c4
CH
1152static inline int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier,
1153 uint32_t sch, int vq,
b4436a0b
CH
1154 bool assign)
1155{
1156 return -ENOSYS;
1157}
7f7f9752
ED
1158static inline int kvm_s390_cpu_restart(S390CPU *cpu)
1159{
1160 return -ENOSYS;
1161}
1cd4e0f6 1162static inline void kvm_s390_cmma_reset(void)
4cb88c3c
DD
1163{
1164}
1def6656
MR
1165static inline int kvm_s390_get_memslot_count(KVMState *s)
1166{
1167 return MAX_AVAIL_SLOTS;
1168}
c9e659c9
DH
1169static inline int kvm_s390_set_cpu_state(S390CPU *cpu, uint8_t cpu_state)
1170{
1171 return -ENOSYS;
1172}
99607144
DH
1173static inline void kvm_s390_reset_vcpu(S390CPU *cpu)
1174{
1175}
a310b283
DD
1176static inline int kvm_s390_set_mem_limit(KVMState *s, uint64_t new_limit,
1177 uint64_t *hw_limit)
1178{
1179 return 0;
1180}
3cda44f7
JF
1181static inline void kvm_s390_vcpu_interrupt_pre_save(S390CPU *cpu)
1182{
1183}
1184static inline int kvm_s390_vcpu_interrupt_post_load(S390CPU *cpu)
1185{
1186 return 0;
1187}
9700230b
FZ
1188static inline int kvm_s390_get_ri(void)
1189{
1190 return 0;
1191}
4ab72920
DH
1192static inline void kvm_s390_crypto_reset(void)
1193{
1194}
09b99878 1195#endif
df1fe5bb 1196
a310b283
DD
1197static inline int s390_set_memory_limit(uint64_t new_limit, uint64_t *hw_limit)
1198{
1199 if (kvm_enabled()) {
1200 return kvm_s390_set_mem_limit(kvm_state, new_limit, hw_limit);
1201 }
1202 return 0;
1203}
1204
1cd4e0f6 1205static inline void s390_cmma_reset(void)
4cb88c3c
DD
1206{
1207 if (kvm_enabled()) {
1cd4e0f6 1208 kvm_s390_cmma_reset();
4cb88c3c
DD
1209 }
1210}
1211
7f7f9752
ED
1212static inline int s390_cpu_restart(S390CPU *cpu)
1213{
1214 if (kvm_enabled()) {
1215 return kvm_s390_cpu_restart(cpu);
1216 }
1217 return -ENOSYS;
1218}
1219
1def6656
MR
1220static inline int s390_get_memslot_count(KVMState *s)
1221{
1222 if (kvm_enabled()) {
1223 return kvm_s390_get_memslot_count(s);
1224 } else {
1225 return MAX_AVAIL_SLOTS;
1226 }
1227}
1228
de13d216
CH
1229void s390_io_interrupt(uint16_t subchannel_id, uint16_t subchannel_nr,
1230 uint32_t io_int_parm, uint32_t io_int_word);
1231void s390_crw_mchk(void);
df1fe5bb 1232
cc3ac9c4
CH
1233static inline int s390_assign_subch_ioeventfd(EventNotifier *notifier,
1234 uint32_t sch_id, int vq,
b4436a0b
CH
1235 bool assign)
1236{
a499973f 1237 return kvm_s390_assign_subch_ioeventfd(notifier, sch_id, vq, assign);
b4436a0b
CH
1238}
1239
4ab72920
DH
1240static inline void s390_crypto_reset(void)
1241{
1242 if (kvm_enabled()) {
1243 kvm_s390_crypto_reset();
1244 }
1245}
1246
b080364a
CH
1247/* machine check interruption code */
1248
1249/* subclasses */
1250#define MCIC_SC_SD 0x8000000000000000ULL
1251#define MCIC_SC_PD 0x4000000000000000ULL
1252#define MCIC_SC_SR 0x2000000000000000ULL
1253#define MCIC_SC_CD 0x0800000000000000ULL
1254#define MCIC_SC_ED 0x0400000000000000ULL
1255#define MCIC_SC_DG 0x0100000000000000ULL
1256#define MCIC_SC_W 0x0080000000000000ULL
1257#define MCIC_SC_CP 0x0040000000000000ULL
1258#define MCIC_SC_SP 0x0020000000000000ULL
1259#define MCIC_SC_CK 0x0010000000000000ULL
1260
1261/* subclass modifiers */
1262#define MCIC_SCM_B 0x0002000000000000ULL
1263#define MCIC_SCM_DA 0x0000000020000000ULL
1264#define MCIC_SCM_AP 0x0000000000080000ULL
1265
1266/* storage errors */
1267#define MCIC_SE_SE 0x0000800000000000ULL
1268#define MCIC_SE_SC 0x0000400000000000ULL
1269#define MCIC_SE_KE 0x0000200000000000ULL
1270#define MCIC_SE_DS 0x0000100000000000ULL
1271#define MCIC_SE_IE 0x0000000080000000ULL
1272
1273/* validity bits */
1274#define MCIC_VB_WP 0x0000080000000000ULL
1275#define MCIC_VB_MS 0x0000040000000000ULL
1276#define MCIC_VB_PM 0x0000020000000000ULL
1277#define MCIC_VB_IA 0x0000010000000000ULL
1278#define MCIC_VB_FA 0x0000008000000000ULL
1279#define MCIC_VB_VR 0x0000004000000000ULL
1280#define MCIC_VB_EC 0x0000002000000000ULL
1281#define MCIC_VB_FP 0x0000001000000000ULL
1282#define MCIC_VB_GR 0x0000000800000000ULL
1283#define MCIC_VB_CR 0x0000000400000000ULL
1284#define MCIC_VB_ST 0x0000000100000000ULL
1285#define MCIC_VB_AR 0x0000000040000000ULL
1286#define MCIC_VB_PR 0x0000000000200000ULL
1287#define MCIC_VB_FC 0x0000000000100000ULL
1288#define MCIC_VB_CT 0x0000000000020000ULL
1289#define MCIC_VB_CC 0x0000000000010000ULL
1290
10ec5117 1291#endif
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