]>
Commit | Line | Data |
---|---|---|
cb9c377f PB |
1 | #ifndef HW_PCNET_H |
2 | #define HW_PCNET_H 1 | |
3 | ||
94e1a912 GH |
4 | #define PCNET_IOPORT_SIZE 0x20 |
5 | #define PCNET_PNPMMIO_SIZE 0x20 | |
6 | ||
7 | #define PCNET_LOOPTEST_CRC 1 | |
8 | #define PCNET_LOOPTEST_NOCRC 2 | |
9 | ||
022c62cb | 10 | #include "exec/memory.h" |
94e1a912 | 11 | |
488a1a5d JK |
12 | /* BUS CONFIGURATION REGISTERS */ |
13 | #define BCR_MSRDA 0 | |
14 | #define BCR_MSWRA 1 | |
15 | #define BCR_MC 2 | |
16 | #define BCR_LNKST 4 | |
17 | #define BCR_LED1 5 | |
18 | #define BCR_LED2 6 | |
19 | #define BCR_LED3 7 | |
20 | #define BCR_FDC 9 | |
21 | #define BCR_BSBC 18 | |
22 | #define BCR_EECAS 19 | |
23 | #define BCR_SWS 20 | |
24 | #define BCR_PLAT 22 | |
25 | ||
ef45c914 | 26 | #define BCR_TMAULOOP(S) !!((S)->bcr[BCR_MC ] & 0x4000) |
488a1a5d JK |
27 | #define BCR_APROMWE(S) !!((S)->bcr[BCR_MC ] & 0x0100) |
28 | #define BCR_DWIO(S) !!((S)->bcr[BCR_BSBC] & 0x0080) | |
29 | #define BCR_SSIZE32(S) !!((S)->bcr[BCR_SWS ] & 0x0100) | |
30 | #define BCR_SWSTYLE(S) ((S)->bcr[BCR_SWS ] & 0x00FF) | |
31 | ||
94e1a912 GH |
32 | typedef struct PCNetState_st PCNetState; |
33 | ||
34 | struct PCNetState_st { | |
1fa51482 | 35 | NICState *nic; |
94e1a912 GH |
36 | NICConf conf; |
37 | QEMUTimer *poll_timer; | |
38 | int rap, isr, lnkst; | |
39 | uint32_t rdra, tdra; | |
40 | uint8_t prom[16]; | |
41 | uint16_t csr[128]; | |
42 | uint16_t bcr[32]; | |
fe87aa83 | 43 | int xmit_pos; |
94e1a912 | 44 | uint64_t timer; |
bd8d6f7c | 45 | MemoryRegion mmio; |
94e1a912 | 46 | uint8_t buffer[4096]; |
94e1a912 | 47 | qemu_irq irq; |
a8170e5e | 48 | void (*phys_mem_read)(void *dma_opaque, hwaddr addr, |
94e1a912 | 49 | uint8_t *buf, int len, int do_bswap); |
a8170e5e | 50 | void (*phys_mem_write)(void *dma_opaque, hwaddr addr, |
94e1a912 GH |
51 | uint8_t *buf, int len, int do_bswap); |
52 | void *dma_opaque; | |
fe87aa83 | 53 | int tx_busy; |
94e1a912 GH |
54 | int looptest; |
55 | }; | |
56 | ||
57 | void pcnet_h_reset(void *opaque); | |
58 | void pcnet_ioport_writew(void *opaque, uint32_t addr, uint32_t val); | |
59 | uint32_t pcnet_ioport_readw(void *opaque, uint32_t addr); | |
a4c75a21 PB |
60 | void pcnet_ioport_writel(void *opaque, uint32_t addr, uint32_t val); |
61 | uint32_t pcnet_ioport_readl(void *opaque, uint32_t addr); | |
62 | uint32_t pcnet_bcr_readw(PCNetState *s, uint32_t rap); | |
4e68f7a0 SH |
63 | int pcnet_can_receive(NetClientState *nc); |
64 | ssize_t pcnet_receive(NetClientState *nc, const uint8_t *buf, size_t size_); | |
65 | void pcnet_set_link_status(NetClientState *nc); | |
94e1a912 | 66 | void pcnet_common_cleanup(PCNetState *d); |
1fa51482 | 67 | int pcnet_common_init(DeviceState *dev, PCNetState *s, NetClientInfo *info); |
3d865059 | 68 | extern const VMStateDescription vmstate_pcnet; |
cb9c377f PB |
69 | |
70 | #endif |