[qemu.git] / hw / ppc / ppc_booke.c

/*
 * QEMU PowerPC Booke hardware System Emulator
 *
 * Copyright (c) 2011 AdaCore
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "hw/hw.h"
#include "hw/ppc/ppc.h"
#include "qemu/timer.h"
#include "sysemu/sysemu.h"
#include "hw/timer/m48t59.h"
#include "qemu/log.h"
#include "hw/loader.h"
#include "kvm_ppc.h"


/* Timer Control Register */

#define TCR_WP_SHIFT  30        /* Watchdog Timer Period */
#define TCR_WP_MASK   (0x3 << TCR_WP_SHIFT)
#define TCR_WRC_SHIFT 28        /* Watchdog Timer Reset Control */
#define TCR_WRC_MASK  (0x3 << TCR_WRC_SHIFT)
#define TCR_WIE       (1 << 27) /* Watchdog Timer Interrupt Enable */
#define TCR_DIE       (1 << 26) /* Decrementer Interrupt Enable */
#define TCR_FP_SHIFT  24        /* Fixed-Interval Timer Period */
#define TCR_FP_MASK   (0x3 << TCR_FP_SHIFT)
#define TCR_FIE       (1 << 23) /* Fixed-Interval Timer Interrupt Enable */
#define TCR_ARE       (1 << 22) /* Auto-Reload Enable */

/* Timer Control Register (e500 specific fields) */

#define TCR_E500_FPEXT_SHIFT 13 /* Fixed-Interval Timer Period Extension */
#define TCR_E500_FPEXT_MASK  (0xf << TCR_E500_FPEXT_SHIFT)
#define TCR_E500_WPEXT_SHIFT 17 /* Watchdog Timer Period Extension */
#define TCR_E500_WPEXT_MASK  (0xf << TCR_E500_WPEXT_SHIFT)

/* Timer Status Register  */

#define TSR_FIS       (1 << 26) /* Fixed-Interval Timer Interrupt Status */
#define TSR_DIS       (1 << 27) /* Decrementer Interrupt Status */
#define TSR_WRS_SHIFT 28        /* Watchdog Timer Reset Status */
#define TSR_WRS_MASK  (0x3 << TSR_WRS_SHIFT)
#define TSR_WIS       (1 << 30) /* Watchdog Timer Interrupt Status */
#define TSR_ENW       (1 << 31) /* Enable Next Watchdog Timer */

typedef struct booke_timer_t booke_timer_t;
struct booke_timer_t {

    uint64_t fit_next;
    struct QEMUTimer *fit_timer;

    uint64_t wdt_next;
    struct QEMUTimer *wdt_timer;

    uint32_t flags;
};

static void booke_update_irq(PowerPCCPU *cpu)
{
    CPUPPCState *env = &cpu->env;

    ppc_set_irq(cpu, PPC_INTERRUPT_DECR,
                (env->spr[SPR_BOOKE_TSR] & TSR_DIS
                 && env->spr[SPR_BOOKE_TCR] & TCR_DIE));

    ppc_set_irq(cpu, PPC_INTERRUPT_WDT,
                (env->spr[SPR_BOOKE_TSR] & TSR_WIS
                 && env->spr[SPR_BOOKE_TCR] & TCR_WIE));

    ppc_set_irq(cpu, PPC_INTERRUPT_FIT,
                (env->spr[SPR_BOOKE_TSR] & TSR_FIS
                 && env->spr[SPR_BOOKE_TCR] & TCR_FIE));
}

/* Return the location of the bit of time base at which the FIT will raise an
   interrupt */
static uint8_t booke_get_fit_target(CPUPPCState *env, ppc_tb_t *tb_env)
{
    uint8_t fp = (env->spr[SPR_BOOKE_TCR] & TCR_FP_MASK) >> TCR_FP_SHIFT;

    if (tb_env->flags & PPC_TIMER_E500) {
        /* e500 Fixed-interval timer period extension */
        uint32_t fpext = (env->spr[SPR_BOOKE_TCR] & TCR_E500_FPEXT_MASK)
            >> TCR_E500_FPEXT_SHIFT;
        fp = 63 - (fp | fpext << 2);
    } else {
        fp = env->fit_period[fp];
    }

    return fp;
}

/* Return the location of the bit of time base at which the WDT will raise an
   interrupt */
static uint8_t booke_get_wdt_target(CPUPPCState *env, ppc_tb_t *tb_env)
{
    uint8_t wp = (env->spr[SPR_BOOKE_TCR] & TCR_WP_MASK) >> TCR_WP_SHIFT;

    if (tb_env->flags & PPC_TIMER_E500) {
        /* e500 Watchdog timer period extension */
        uint32_t wpext = (env->spr[SPR_BOOKE_TCR] & TCR_E500_WPEXT_MASK)
            >> TCR_E500_WPEXT_SHIFT;
        wp = 63 - (wp | wpext << 2);
    } else {
        wp = env->wdt_period[wp];
    }

    return wp;
}

static void booke_update_fixed_timer(CPUPPCState         *env,
                                     uint8_t           target_bit,
                                     uint64_t          *next,
                                     struct QEMUTimer *timer)
{
    ppc_tb_t *tb_env = env->tb_env;
    uint64_t lapse;
    uint64_t tb;
    uint64_t period = 1 << (target_bit + 1);
    uint64_t now;

    now = qemu_get_clock_ns(vm_clock);
    tb  = cpu_ppc_get_tb(tb_env, now, tb_env->tb_offset);

    lapse = period - ((tb - (1 << target_bit)) & (period - 1));

    *next = now + muldiv64(lapse, get_ticks_per_sec(), tb_env->tb_freq);

    /* XXX: If expire time is now. We can't run the callback because we don't
     * have access to it. So we just set the timer one nanosecond later.
     */

    if (*next == now) {
        (*next)++;
    }

    qemu_mod_timer(timer, *next);
}

static void booke_decr_cb(void *opaque)
{
    PowerPCCPU *cpu = opaque;
    CPUPPCState *env = &cpu->env;

    env->spr[SPR_BOOKE_TSR] |= TSR_DIS;
    booke_update_irq(cpu);

    if (env->spr[SPR_BOOKE_TCR] & TCR_ARE) {
        /* Auto Reload */
        cpu_ppc_store_decr(env, env->spr[SPR_BOOKE_DECAR]);
    }
}

static void booke_fit_cb(void *opaque)
{
    PowerPCCPU *cpu = opaque;
    CPUPPCState *env = &cpu->env;
    ppc_tb_t *tb_env;
    booke_timer_t *booke_timer;

    tb_env = env->tb_env;
    booke_timer = tb_env->opaque;
    env->spr[SPR_BOOKE_TSR] |= TSR_FIS;

    booke_update_irq(cpu);

    booke_update_fixed_timer(env,
                             booke_get_fit_target(env, tb_env),
                             &booke_timer->fit_next,
                             booke_timer->fit_timer);
}

static void booke_wdt_cb(void *opaque)
{
    PowerPCCPU *cpu = opaque;
    CPUPPCState *env = &cpu->env;
    ppc_tb_t *tb_env;
    booke_timer_t *booke_timer;

    tb_env = env->tb_env;
    booke_timer = tb_env->opaque;

    /* TODO: There's lots of complicated stuff to do here */

    booke_update_irq(cpu);

    booke_update_fixed_timer(env,
                             booke_get_wdt_target(env, tb_env),
                             &booke_timer->wdt_next,
                             booke_timer->wdt_timer);
}

void store_booke_tsr(CPUPPCState *env, target_ulong val)
{
    PowerPCCPU *cpu = ppc_env_get_cpu(env);

    env->spr[SPR_BOOKE_TSR] &= ~val;
    kvmppc_clear_tsr_bits(cpu, val);
    booke_update_irq(cpu);
}

void store_booke_tcr(CPUPPCState *env, target_ulong val)
{
    PowerPCCPU *cpu = ppc_env_get_cpu(env);
    ppc_tb_t *tb_env = env->tb_env;
    booke_timer_t *booke_timer = tb_env->opaque;

    tb_env = env->tb_env;
    env->spr[SPR_BOOKE_TCR] = val;
    kvmppc_set_tcr(cpu);

    booke_update_irq(cpu);

    booke_update_fixed_timer(env,
                             booke_get_fit_target(env, tb_env),
                             &booke_timer->fit_next,
                             booke_timer->fit_timer);

    booke_update_fixed_timer(env,
                             booke_get_wdt_target(env, tb_env),
                             &booke_timer->wdt_next,
                             booke_timer->wdt_timer);
}

static void ppc_booke_timer_reset_handle(void *opaque)
{
    PowerPCCPU *cpu = opaque;
    CPUPPCState *env = &cpu->env;

    store_booke_tcr(env, 0);
    store_booke_tsr(env, -1);
}

/*
 * This function will be called whenever the CPU state changes.
 * CPU states are defined "typedef enum RunState".
 * Regarding timer, When CPU state changes to running after debug halt
 * or similar cases which takes time then in between final watchdog
 * expiry happenes. This will cause exit to QEMU and configured watchdog
 * action will be taken. To avoid this we always clear the watchdog state when
 * state changes to running.
 */
static void cpu_state_change_handler(void *opaque, int running, RunState state)
{
    PowerPCCPU *cpu = opaque;
    CPUPPCState *env = &cpu->env;

    if (!running) {
        return;
    }

    /*
     * Clear watchdog interrupt condition by clearing TSR.
     */
    store_booke_tsr(env, TSR_ENW | TSR_WIS | TSR_WRS_MASK);
}

void ppc_booke_timers_init(PowerPCCPU *cpu, uint32_t freq, uint32_t flags)
{
    ppc_tb_t *tb_env;
    booke_timer_t *booke_timer;
    int ret = 0;

    tb_env      = g_malloc0(sizeof(ppc_tb_t));
    booke_timer = g_malloc0(sizeof(booke_timer_t));

    cpu->env.tb_env = tb_env;
    tb_env->flags = flags | PPC_TIMER_BOOKE | PPC_DECR_ZERO_TRIGGERED;

    tb_env->tb_freq    = freq;
    tb_env->decr_freq  = freq;
    tb_env->opaque     = booke_timer;
    tb_env->decr_timer = qemu_new_timer_ns(vm_clock, &booke_decr_cb, cpu);

    booke_timer->fit_timer =
        qemu_new_timer_ns(vm_clock, &booke_fit_cb, cpu);
    booke_timer->wdt_timer =
        qemu_new_timer_ns(vm_clock, &booke_wdt_cb, cpu);

    ret = kvmppc_booke_watchdog_enable(cpu);

    if (ret) {
        /* TODO: Start the QEMU emulated watchdog if not running on KVM.
         * Also start the QEMU emulated watchdog if KVM does not support
         * emulated watchdog or somehow it is not enabled (supported but
         * not enabled is though some bug and requires debugging :)).
         */
    }

    qemu_add_vm_change_state_handler(cpu_state_change_handler, cpu);

    qemu_register_reset(ppc_booke_timer_reset_handle, cpu);
}
Commit	Line	Data
ddd1055b FC	1	/*
	2	* QEMU PowerPC Booke hardware System Emulator
	3	*
	4	* Copyright (c) 2011 AdaCore
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
83c9f4ca	24	#include "hw/hw.h"
0d09e41a	25	#include "hw/ppc/ppc.h"
1de7afc9	26	#include "qemu/timer.h"
9c17d615	27	#include "sysemu/sysemu.h"
0d09e41a	28	#include "hw/timer/m48t59.h"
1de7afc9	29	#include "qemu/log.h"
83c9f4ca	30	#include "hw/loader.h"
31f2cb8f	31	#include "kvm_ppc.h"
ddd1055b FC	32
	33
	34	/* Timer Control Register */
	35
	36	#define TCR_WP_SHIFT 30 /* Watchdog Timer Period */
	37	#define TCR_WP_MASK (0x3 << TCR_WP_SHIFT)
	38	#define TCR_WRC_SHIFT 28 /* Watchdog Timer Reset Control */
	39	#define TCR_WRC_MASK (0x3 << TCR_WRC_SHIFT)
	40	#define TCR_WIE (1 << 27) /* Watchdog Timer Interrupt Enable */
	41	#define TCR_DIE (1 << 26) /* Decrementer Interrupt Enable */
	42	#define TCR_FP_SHIFT 24 /* Fixed-Interval Timer Period */
	43	#define TCR_FP_MASK (0x3 << TCR_FP_SHIFT)
	44	#define TCR_FIE (1 << 23) /* Fixed-Interval Timer Interrupt Enable */
	45	#define TCR_ARE (1 << 22) /* Auto-Reload Enable */
	46
	47	/* Timer Control Register (e500 specific fields) */
	48
	49	#define TCR_E500_FPEXT_SHIFT 13 /* Fixed-Interval Timer Period Extension */
	50	#define TCR_E500_FPEXT_MASK (0xf << TCR_E500_FPEXT_SHIFT)
	51	#define TCR_E500_WPEXT_SHIFT 17 /* Watchdog Timer Period Extension */
	52	#define TCR_E500_WPEXT_MASK (0xf << TCR_E500_WPEXT_SHIFT)
	53
	54	/* Timer Status Register */
	55
	56	#define TSR_FIS (1 << 26) /* Fixed-Interval Timer Interrupt Status */
	57	#define TSR_DIS (1 << 27) /* Decrementer Interrupt Status */
	58	#define TSR_WRS_SHIFT 28 /* Watchdog Timer Reset Status */
	59	#define TSR_WRS_MASK (0x3 << TSR_WRS_SHIFT)
	60	#define TSR_WIS (1 << 30) /* Watchdog Timer Interrupt Status */
	61	#define TSR_ENW (1 << 31) /* Enable Next Watchdog Timer */
	62
	63	typedef struct booke_timer_t booke_timer_t;
	64	struct booke_timer_t {
	65
	66	uint64_t fit_next;
	67	struct QEMUTimer *fit_timer;
	68
	69	uint64_t wdt_next;
	70	struct QEMUTimer *wdt_timer;
	71
	72	uint32_t flags;
	73	};
	74
7058581a	75	static void booke_update_irq(PowerPCCPU *cpu)
ddd1055b	76	{
7058581a AF	77	CPUPPCState *env = &cpu->env;
	78
	79	ppc_set_irq(cpu, PPC_INTERRUPT_DECR,
ddd1055b FC	80	(env->spr[SPR_BOOKE_TSR] & TSR_DIS
	81	&& env->spr[SPR_BOOKE_TCR] & TCR_DIE));
	82
7058581a	83	ppc_set_irq(cpu, PPC_INTERRUPT_WDT,
ddd1055b FC	84	(env->spr[SPR_BOOKE_TSR] & TSR_WIS
	85	&& env->spr[SPR_BOOKE_TCR] & TCR_WIE));
	86
7058581a	87	ppc_set_irq(cpu, PPC_INTERRUPT_FIT,
ddd1055b FC	88	(env->spr[SPR_BOOKE_TSR] & TSR_FIS
	89	&& env->spr[SPR_BOOKE_TCR] & TCR_FIE));
	90	}
	91
	92	/* Return the location of the bit of time base at which the FIT will raise an
	93	interrupt */
e2684c0b	94	static uint8_t booke_get_fit_target(CPUPPCState env, ppc_tb_t tb_env)
ddd1055b FC	95	{
	96	uint8_t fp = (env->spr[SPR_BOOKE_TCR] & TCR_FP_MASK) >> TCR_FP_SHIFT;
	97
	98	if (tb_env->flags & PPC_TIMER_E500) {
	99	/* e500 Fixed-interval timer period extension */
	100	uint32_t fpext = (env->spr[SPR_BOOKE_TCR] & TCR_E500_FPEXT_MASK)
	101	>> TCR_E500_FPEXT_SHIFT;
	102	fp = 63 - (fp \| fpext << 2);
	103	} else {
	104	fp = env->fit_period[fp];
	105	}
	106
	107	return fp;
	108	}
	109
	110	/* Return the location of the bit of time base at which the WDT will raise an
	111	interrupt */
e2684c0b	112	static uint8_t booke_get_wdt_target(CPUPPCState env, ppc_tb_t tb_env)
ddd1055b FC	113	{
	114	uint8_t wp = (env->spr[SPR_BOOKE_TCR] & TCR_WP_MASK) >> TCR_WP_SHIFT;
	115
	116	if (tb_env->flags & PPC_TIMER_E500) {
	117	/* e500 Watchdog timer period extension */
	118	uint32_t wpext = (env->spr[SPR_BOOKE_TCR] & TCR_E500_WPEXT_MASK)
	119	>> TCR_E500_WPEXT_SHIFT;
	120	wp = 63 - (wp \| wpext << 2);
	121	} else {
	122	wp = env->wdt_period[wp];
	123	}
	124
	125	return wp;
	126	}
	127
e2684c0b	128	static void booke_update_fixed_timer(CPUPPCState *env,
ddd1055b FC	129	uint8_t target_bit,
	130	uint64_t *next,
	131	struct QEMUTimer *timer)
	132	{
	133	ppc_tb_t *tb_env = env->tb_env;
	134	uint64_t lapse;
	135	uint64_t tb;
	136	uint64_t period = 1 << (target_bit + 1);
	137	uint64_t now;
	138
	139	now = qemu_get_clock_ns(vm_clock);
	140	tb = cpu_ppc_get_tb(tb_env, now, tb_env->tb_offset);
	141
	142	lapse = period - ((tb - (1 << target_bit)) & (period - 1));
	143
	144	*next = now + muldiv64(lapse, get_ticks_per_sec(), tb_env->tb_freq);
	145
	146	/* XXX: If expire time is now. We can't run the callback because we don't
	147	* have access to it. So we just set the timer one nanosecond later.
	148	*/
	149
	150	if (*next == now) {
	151	(*next)++;
	152	}
	153
	154	qemu_mod_timer(timer, *next);
	155	}
	156
	157	static void booke_decr_cb(void *opaque)
	158	{
ee0c98e6 AF	159	PowerPCCPU *cpu = opaque;
ee0c98e6 AF	160	CPUPPCState *env = &cpu->env;
ddd1055b	161
ddd1055b	162	env->spr[SPR_BOOKE_TSR] \|= TSR_DIS;
7058581a	163	booke_update_irq(cpu);
ddd1055b FC	164
	165	if (env->spr[SPR_BOOKE_TCR] & TCR_ARE) {
	166	/* Auto Reload */
	167	cpu_ppc_store_decr(env, env->spr[SPR_BOOKE_DECAR]);
	168	}
	169	}
	170
	171	static void booke_fit_cb(void *opaque)
	172	{
ee0c98e6 AF	173	PowerPCCPU *cpu = opaque;
ee0c98e6 AF	174	CPUPPCState *env = &cpu->env;
ddd1055b FC	175	ppc_tb_t *tb_env;
	176	booke_timer_t *booke_timer;
	177
ddd1055b FC	178	tb_env = env->tb_env;
	179	booke_timer = tb_env->opaque;
	180	env->spr[SPR_BOOKE_TSR] \|= TSR_FIS;
	181
7058581a	182	booke_update_irq(cpu);
ddd1055b FC	183
	184	booke_update_fixed_timer(env,
	185	booke_get_fit_target(env, tb_env),
	186	&booke_timer->fit_next,
	187	booke_timer->fit_timer);
	188	}
	189
	190	static void booke_wdt_cb(void *opaque)
	191	{
ee0c98e6 AF	192	PowerPCCPU *cpu = opaque;
ee0c98e6 AF	193	CPUPPCState *env = &cpu->env;
ddd1055b FC	194	ppc_tb_t *tb_env;
	195	booke_timer_t *booke_timer;
	196
ddd1055b FC	197	tb_env = env->tb_env;
	198	booke_timer = tb_env->opaque;
	199
	200	/* TODO: There's lots of complicated stuff to do here */
	201
7058581a	202	booke_update_irq(cpu);
ddd1055b FC	203
	204	booke_update_fixed_timer(env,
	205	booke_get_wdt_target(env, tb_env),
	206	&booke_timer->wdt_next,
	207	booke_timer->wdt_timer);
	208	}
	209
e2684c0b	210	void store_booke_tsr(CPUPPCState *env, target_ulong val)
ddd1055b	211	{
7058581a AF	212	PowerPCCPU *cpu = ppc_env_get_cpu(env);
7058581a AF	213
ddd1055b	214	env->spr[SPR_BOOKE_TSR] &= ~val;
31f2cb8f	215	kvmppc_clear_tsr_bits(cpu, val);
7058581a	216	booke_update_irq(cpu);
ddd1055b FC	217	}
ddd1055b FC	218
e2684c0b	219	void store_booke_tcr(CPUPPCState *env, target_ulong val)
ddd1055b	220	{
7058581a	221	PowerPCCPU *cpu = ppc_env_get_cpu(env);
ddd1055b FC	222	ppc_tb_t *tb_env = env->tb_env;
	223	booke_timer_t *booke_timer = tb_env->opaque;
	224
	225	tb_env = env->tb_env;
	226	env->spr[SPR_BOOKE_TCR] = val;
31f2cb8f	227	kvmppc_set_tcr(cpu);
ddd1055b	228
7058581a	229	booke_update_irq(cpu);
ddd1055b FC	230
	231	booke_update_fixed_timer(env,
	232	booke_get_fit_target(env, tb_env),
	233	&booke_timer->fit_next,
	234	booke_timer->fit_timer);
	235
	236	booke_update_fixed_timer(env,
	237	booke_get_wdt_target(env, tb_env),
	238	&booke_timer->wdt_next,
	239	booke_timer->wdt_timer);
ddd1055b FC	240	}
ddd1055b FC	241
88a78d90 BB	242	static void ppc_booke_timer_reset_handle(void *opaque)
	243	{
	244	PowerPCCPU *cpu = opaque;
	245	CPUPPCState *env = &cpu->env;
	246
31f2cb8f BB	247	store_booke_tcr(env, 0);
	248	store_booke_tsr(env, -1);
	249	}
88a78d90	250
31f2cb8f BB	251	/*
	252	* This function will be called whenever the CPU state changes.
	253	* CPU states are defined "typedef enum RunState".
	254	* Regarding timer, When CPU state changes to running after debug halt
	255	* or similar cases which takes time then in between final watchdog
	256	* expiry happenes. This will cause exit to QEMU and configured watchdog
	257	* action will be taken. To avoid this we always clear the watchdog state when
	258	* state changes to running.
	259	*/
	260	static void cpu_state_change_handler(void *opaque, int running, RunState state)
	261	{
	262	PowerPCCPU *cpu = opaque;
	263	CPUPPCState *env = &cpu->env;
	264
	265	if (!running) {
	266	return;
	267	}
	268
	269	/*
	270	* Clear watchdog interrupt condition by clearing TSR.
	271	*/
	272	store_booke_tsr(env, TSR_ENW \| TSR_WIS \| TSR_WRS_MASK);
88a78d90 BB	273	}
88a78d90 BB	274
a34a92b9	275	void ppc_booke_timers_init(PowerPCCPU *cpu, uint32_t freq, uint32_t flags)
ddd1055b FC	276	{
	277	ppc_tb_t *tb_env;
	278	booke_timer_t *booke_timer;
31f2cb8f	279	int ret = 0;
ddd1055b FC	280
	281	tb_env = g_malloc0(sizeof(ppc_tb_t));
	282	booke_timer = g_malloc0(sizeof(booke_timer_t));
	283
a34a92b9	284	cpu->env.tb_env = tb_env;
ddd1055b FC	285	tb_env->flags = flags \| PPC_TIMER_BOOKE \| PPC_DECR_ZERO_TRIGGERED;
	286
	287	tb_env->tb_freq = freq;
	288	tb_env->decr_freq = freq;
	289	tb_env->opaque = booke_timer;
ee0c98e6	290	tb_env->decr_timer = qemu_new_timer_ns(vm_clock, &booke_decr_cb, cpu);
ddd1055b FC	291
ddd1055b FC	292	booke_timer->fit_timer =
ee0c98e6	293	qemu_new_timer_ns(vm_clock, &booke_fit_cb, cpu);
ddd1055b	294	booke_timer->wdt_timer =
ee0c98e6	295	qemu_new_timer_ns(vm_clock, &booke_wdt_cb, cpu);
88a78d90	296
31f2cb8f BB	297	ret = kvmppc_booke_watchdog_enable(cpu);
	298
	299	if (ret) {
	300	/* TODO: Start the QEMU emulated watchdog if not running on KVM.
	301	* Also start the QEMU emulated watchdog if KVM does not support
	302	* emulated watchdog or somehow it is not enabled (supported but
	303	* not enabled is though some bug and requires debugging :)).
	304	*/
	305	}
	306
	307	qemu_add_vm_change_state_handler(cpu_state_change_handler, cpu);
	308
88a78d90	309	qemu_register_reset(ppc_booke_timer_reset_handle, cpu);
ddd1055b	310	}