[qemu.git] / hw / ppc / ppc_booke.c

/*
 * QEMU PowerPC Booke hardware System Emulator
 *
 * Copyright (c) 2011 AdaCore
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "qemu/osdep.h"
#include "hw/hw.h"
#include "hw/ppc/ppc.h"
#include "qemu/timer.h"
#include "sysemu/sysemu.h"
#include "hw/timer/m48t59.h"
#include "qemu/log.h"
#include "hw/loader.h"
#include "kvm_ppc.h"


/* Timer Control Register */

#define TCR_WP_SHIFT  30        /* Watchdog Timer Period */
#define TCR_WP_MASK   (0x3U << TCR_WP_SHIFT)
#define TCR_WRC_SHIFT 28        /* Watchdog Timer Reset Control */
#define TCR_WRC_MASK  (0x3U << TCR_WRC_SHIFT)
#define TCR_WIE       (1U << 27) /* Watchdog Timer Interrupt Enable */
#define TCR_DIE       (1U << 26) /* Decrementer Interrupt Enable */
#define TCR_FP_SHIFT  24        /* Fixed-Interval Timer Period */
#define TCR_FP_MASK   (0x3U << TCR_FP_SHIFT)
#define TCR_FIE       (1U << 23) /* Fixed-Interval Timer Interrupt Enable */
#define TCR_ARE       (1U << 22) /* Auto-Reload Enable */

/* Timer Control Register (e500 specific fields) */

#define TCR_E500_FPEXT_SHIFT 13 /* Fixed-Interval Timer Period Extension */
#define TCR_E500_FPEXT_MASK  (0xf << TCR_E500_FPEXT_SHIFT)
#define TCR_E500_WPEXT_SHIFT 17 /* Watchdog Timer Period Extension */
#define TCR_E500_WPEXT_MASK  (0xf << TCR_E500_WPEXT_SHIFT)

/* Timer Status Register  */

#define TSR_FIS       (1U << 26) /* Fixed-Interval Timer Interrupt Status */
#define TSR_DIS       (1U << 27) /* Decrementer Interrupt Status */
#define TSR_WRS_SHIFT 28        /* Watchdog Timer Reset Status */
#define TSR_WRS_MASK  (0x3U << TSR_WRS_SHIFT)
#define TSR_WIS       (1U << 30) /* Watchdog Timer Interrupt Status */
#define TSR_ENW       (1U << 31) /* Enable Next Watchdog Timer */

typedef struct booke_timer_t booke_timer_t;
struct booke_timer_t {

    uint64_t fit_next;
    QEMUTimer *fit_timer;

    uint64_t wdt_next;
    QEMUTimer *wdt_timer;

    uint32_t flags;
};

static void booke_update_irq(PowerPCCPU *cpu)
{
    CPUPPCState *env = &cpu->env;

    ppc_set_irq(cpu, PPC_INTERRUPT_DECR,
                (env->spr[SPR_BOOKE_TSR] & TSR_DIS
                 && env->spr[SPR_BOOKE_TCR] & TCR_DIE));

    ppc_set_irq(cpu, PPC_INTERRUPT_WDT,
                (env->spr[SPR_BOOKE_TSR] & TSR_WIS
                 && env->spr[SPR_BOOKE_TCR] & TCR_WIE));

    ppc_set_irq(cpu, PPC_INTERRUPT_FIT,
                (env->spr[SPR_BOOKE_TSR] & TSR_FIS
                 && env->spr[SPR_BOOKE_TCR] & TCR_FIE));
}

/* Return the location of the bit of time base at which the FIT will raise an
   interrupt */
static uint8_t booke_get_fit_target(CPUPPCState *env, ppc_tb_t *tb_env)
{
    uint8_t fp = (env->spr[SPR_BOOKE_TCR] & TCR_FP_MASK) >> TCR_FP_SHIFT;

    if (tb_env->flags & PPC_TIMER_E500) {
        /* e500 Fixed-interval timer period extension */
        uint32_t fpext = (env->spr[SPR_BOOKE_TCR] & TCR_E500_FPEXT_MASK)
            >> TCR_E500_FPEXT_SHIFT;
        fp = 63 - (fp | fpext << 2);
    } else {
        fp = env->fit_period[fp];
    }

    return fp;
}

/* Return the location of the bit of time base at which the WDT will raise an
   interrupt */
static uint8_t booke_get_wdt_target(CPUPPCState *env, ppc_tb_t *tb_env)
{
    uint8_t wp = (env->spr[SPR_BOOKE_TCR] & TCR_WP_MASK) >> TCR_WP_SHIFT;

    if (tb_env->flags & PPC_TIMER_E500) {
        /* e500 Watchdog timer period extension */
        uint32_t wpext = (env->spr[SPR_BOOKE_TCR] & TCR_E500_WPEXT_MASK)
            >> TCR_E500_WPEXT_SHIFT;
        wp = 63 - (wp | wpext << 2);
    } else {
        wp = env->wdt_period[wp];
    }

    return wp;
}

static void booke_update_fixed_timer(CPUPPCState         *env,
                                     uint8_t           target_bit,
                                     uint64_t          *next,
                                     QEMUTimer         *timer,
                                     int               tsr_bit)
{
    ppc_tb_t *tb_env = env->tb_env;
    uint64_t delta_tick, ticks = 0;
    uint64_t tb;
    uint64_t period;
    uint64_t now;

    if (!(env->spr[SPR_BOOKE_TSR] & tsr_bit)) {
        /*
         * Don't arm the timer again when the guest has the current
         * interrupt still pending. Wait for it to ack it.
         */
        return;
    }

    now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
    tb  = cpu_ppc_get_tb(tb_env, now, tb_env->tb_offset);
    period = 1ULL << target_bit;
    delta_tick = period - (tb & (period - 1));

    /* the timer triggers only when the selected bit toggles from 0 to 1 */
    if (tb & period) {
        ticks = period;
    }

    if (ticks + delta_tick < ticks) {
        /* Overflow, so assume the biggest number we can express. */
        ticks = UINT64_MAX;
    } else {
        ticks += delta_tick;
    }

    *next = now + muldiv64(ticks, get_ticks_per_sec(), tb_env->tb_freq);
    if ((*next < now) || (*next > INT64_MAX)) {
        /* Overflow, so assume the biggest number the qemu timer supports. */
        *next = INT64_MAX;
    }

    /* XXX: If expire time is now. We can't run the callback because we don't
     * have access to it. So we just set the timer one nanosecond later.
     */

    if (*next == now) {
        (*next)++;
    } else {
        /*
         * There's no point to fake any granularity that's more fine grained
         * than milliseconds. Anything beyond that just overloads the system.
         */
        *next = MAX(*next, now + SCALE_MS);
    }

    /* Fire the next timer */
    timer_mod(timer, *next);
}

static void booke_decr_cb(void *opaque)
{
    PowerPCCPU *cpu = opaque;
    CPUPPCState *env = &cpu->env;

    env->spr[SPR_BOOKE_TSR] |= TSR_DIS;
    booke_update_irq(cpu);

    if (env->spr[SPR_BOOKE_TCR] & TCR_ARE) {
        /* Auto Reload */
        cpu_ppc_store_decr(env, env->spr[SPR_BOOKE_DECAR]);
    }
}

static void booke_fit_cb(void *opaque)
{
    PowerPCCPU *cpu = opaque;
    CPUPPCState *env = &cpu->env;
    ppc_tb_t *tb_env;
    booke_timer_t *booke_timer;

    tb_env = env->tb_env;
    booke_timer = tb_env->opaque;
    env->spr[SPR_BOOKE_TSR] |= TSR_FIS;

    booke_update_irq(cpu);

    booke_update_fixed_timer(env,
                             booke_get_fit_target(env, tb_env),
                             &booke_timer->fit_next,
                             booke_timer->fit_timer,
                             TSR_FIS);
}

static void booke_wdt_cb(void *opaque)
{
    PowerPCCPU *cpu = opaque;
    CPUPPCState *env = &cpu->env;
    ppc_tb_t *tb_env;
    booke_timer_t *booke_timer;

    tb_env = env->tb_env;
    booke_timer = tb_env->opaque;

    /* TODO: There's lots of complicated stuff to do here */

    booke_update_irq(cpu);

    booke_update_fixed_timer(env,
                             booke_get_wdt_target(env, tb_env),
                             &booke_timer->wdt_next,
                             booke_timer->wdt_timer,
                             TSR_WIS);
}

void store_booke_tsr(CPUPPCState *env, target_ulong val)
{
    PowerPCCPU *cpu = ppc_env_get_cpu(env);
    ppc_tb_t *tb_env = env->tb_env;
    booke_timer_t *booke_timer = tb_env->opaque;

    env->spr[SPR_BOOKE_TSR] &= ~val;
    kvmppc_clear_tsr_bits(cpu, val);

    if (val & TSR_FIS) {
        booke_update_fixed_timer(env,
                                 booke_get_fit_target(env, tb_env),
                                 &booke_timer->fit_next,
                                 booke_timer->fit_timer,
                                 TSR_FIS);
    }

    if (val & TSR_WIS) {
        booke_update_fixed_timer(env,
                                 booke_get_wdt_target(env, tb_env),
                                 &booke_timer->wdt_next,
                                 booke_timer->wdt_timer,
                                 TSR_WIS);
    }

    booke_update_irq(cpu);
}

void store_booke_tcr(CPUPPCState *env, target_ulong val)
{
    PowerPCCPU *cpu = ppc_env_get_cpu(env);
    ppc_tb_t *tb_env = env->tb_env;
    booke_timer_t *booke_timer = tb_env->opaque;

    tb_env = env->tb_env;
    env->spr[SPR_BOOKE_TCR] = val;
    kvmppc_set_tcr(cpu);

    booke_update_irq(cpu);

    booke_update_fixed_timer(env,
                             booke_get_fit_target(env, tb_env),
                             &booke_timer->fit_next,
                             booke_timer->fit_timer,
                             TSR_FIS);

    booke_update_fixed_timer(env,
                             booke_get_wdt_target(env, tb_env),
                             &booke_timer->wdt_next,
                             booke_timer->wdt_timer,
                             TSR_WIS);
}

static void ppc_booke_timer_reset_handle(void *opaque)
{
    PowerPCCPU *cpu = opaque;
    CPUPPCState *env = &cpu->env;

    store_booke_tcr(env, 0);
    store_booke_tsr(env, -1);
}

/*
 * This function will be called whenever the CPU state changes.
 * CPU states are defined "typedef enum RunState".
 * Regarding timer, When CPU state changes to running after debug halt
 * or similar cases which takes time then in between final watchdog
 * expiry happenes. This will cause exit to QEMU and configured watchdog
 * action will be taken. To avoid this we always clear the watchdog state when
 * state changes to running.
 */
static void cpu_state_change_handler(void *opaque, int running, RunState state)
{
    PowerPCCPU *cpu = opaque;
    CPUPPCState *env = &cpu->env;

    if (!running) {
        return;
    }

    /*
     * Clear watchdog interrupt condition by clearing TSR.
     */
    store_booke_tsr(env, TSR_ENW | TSR_WIS | TSR_WRS_MASK);
}

void ppc_booke_timers_init(PowerPCCPU *cpu, uint32_t freq, uint32_t flags)
{
    ppc_tb_t *tb_env;
    booke_timer_t *booke_timer;
    int ret = 0;

    tb_env      = g_malloc0(sizeof(ppc_tb_t));
    booke_timer = g_malloc0(sizeof(booke_timer_t));

    cpu->env.tb_env = tb_env;
    tb_env->flags = flags | PPC_TIMER_BOOKE | PPC_DECR_ZERO_TRIGGERED;

    tb_env->tb_freq    = freq;
    tb_env->decr_freq  = freq;
    tb_env->opaque     = booke_timer;
    tb_env->decr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &booke_decr_cb, cpu);

    booke_timer->fit_timer =
        timer_new_ns(QEMU_CLOCK_VIRTUAL, &booke_fit_cb, cpu);
    booke_timer->wdt_timer =
        timer_new_ns(QEMU_CLOCK_VIRTUAL, &booke_wdt_cb, cpu);

    ret = kvmppc_booke_watchdog_enable(cpu);

    if (ret) {
        /* TODO: Start the QEMU emulated watchdog if not running on KVM.
         * Also start the QEMU emulated watchdog if KVM does not support
         * emulated watchdog or somehow it is not enabled (supported but
         * not enabled is though some bug and requires debugging :)).
         */
    }

    qemu_add_vm_change_state_handler(cpu_state_change_handler, cpu);

    qemu_register_reset(ppc_booke_timer_reset_handle, cpu);
}
Commit	Line	Data
ddd1055b FC	1	/*
	2	* QEMU PowerPC Booke hardware System Emulator
	3	*
	4	* Copyright (c) 2011 AdaCore
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
0d75590d	24	#include "qemu/osdep.h"
83c9f4ca	25	#include "hw/hw.h"
0d09e41a	26	#include "hw/ppc/ppc.h"
1de7afc9	27	#include "qemu/timer.h"
9c17d615	28	#include "sysemu/sysemu.h"
0d09e41a	29	#include "hw/timer/m48t59.h"
1de7afc9	30	#include "qemu/log.h"
83c9f4ca	31	#include "hw/loader.h"
31f2cb8f	32	#include "kvm_ppc.h"
ddd1055b FC	33
	34
	35	/* Timer Control Register */
	36
	37	#define TCR_WP_SHIFT 30 /* Watchdog Timer Period */
a1f7f97b	38	#define TCR_WP_MASK (0x3U << TCR_WP_SHIFT)
ddd1055b	39	#define TCR_WRC_SHIFT 28 /* Watchdog Timer Reset Control */
a1f7f97b PM	40	#define TCR_WRC_MASK (0x3U << TCR_WRC_SHIFT)
	41	#define TCR_WIE (1U << 27) /* Watchdog Timer Interrupt Enable */
	42	#define TCR_DIE (1U << 26) /* Decrementer Interrupt Enable */
ddd1055b	43	#define TCR_FP_SHIFT 24 /* Fixed-Interval Timer Period */
a1f7f97b PM	44	#define TCR_FP_MASK (0x3U << TCR_FP_SHIFT)
	45	#define TCR_FIE (1U << 23) /* Fixed-Interval Timer Interrupt Enable */
	46	#define TCR_ARE (1U << 22) /* Auto-Reload Enable */
ddd1055b FC	47
	48	/* Timer Control Register (e500 specific fields) */
	49
	50	#define TCR_E500_FPEXT_SHIFT 13 /* Fixed-Interval Timer Period Extension */
	51	#define TCR_E500_FPEXT_MASK (0xf << TCR_E500_FPEXT_SHIFT)
	52	#define TCR_E500_WPEXT_SHIFT 17 /* Watchdog Timer Period Extension */
	53	#define TCR_E500_WPEXT_MASK (0xf << TCR_E500_WPEXT_SHIFT)
	54
	55	/* Timer Status Register */
	56
a1f7f97b PM	57	#define TSR_FIS (1U << 26) /* Fixed-Interval Timer Interrupt Status */
a1f7f97b PM	58	#define TSR_DIS (1U << 27) /* Decrementer Interrupt Status */
ddd1055b	59	#define TSR_WRS_SHIFT 28 /* Watchdog Timer Reset Status */
a1f7f97b PM	60	#define TSR_WRS_MASK (0x3U << TSR_WRS_SHIFT)
	61	#define TSR_WIS (1U << 30) /* Watchdog Timer Interrupt Status */
	62	#define TSR_ENW (1U << 31) /* Enable Next Watchdog Timer */
ddd1055b FC	63
	64	typedef struct booke_timer_t booke_timer_t;
	65	struct booke_timer_t {
	66
	67	uint64_t fit_next;
1246b259	68	QEMUTimer *fit_timer;
ddd1055b FC	69
ddd1055b FC	70	uint64_t wdt_next;
1246b259	71	QEMUTimer *wdt_timer;
ddd1055b FC	72
	73	uint32_t flags;
	74	};
	75
7058581a	76	static void booke_update_irq(PowerPCCPU *cpu)
ddd1055b	77	{
7058581a AF	78	CPUPPCState *env = &cpu->env;
	79
	80	ppc_set_irq(cpu, PPC_INTERRUPT_DECR,
ddd1055b FC	81	(env->spr[SPR_BOOKE_TSR] & TSR_DIS
	82	&& env->spr[SPR_BOOKE_TCR] & TCR_DIE));
	83
7058581a	84	ppc_set_irq(cpu, PPC_INTERRUPT_WDT,
ddd1055b FC	85	(env->spr[SPR_BOOKE_TSR] & TSR_WIS
	86	&& env->spr[SPR_BOOKE_TCR] & TCR_WIE));
	87
7058581a	88	ppc_set_irq(cpu, PPC_INTERRUPT_FIT,
ddd1055b FC	89	(env->spr[SPR_BOOKE_TSR] & TSR_FIS
	90	&& env->spr[SPR_BOOKE_TCR] & TCR_FIE));
	91	}
	92
	93	/* Return the location of the bit of time base at which the FIT will raise an
	94	interrupt */
e2684c0b	95	static uint8_t booke_get_fit_target(CPUPPCState env, ppc_tb_t tb_env)
ddd1055b FC	96	{
	97	uint8_t fp = (env->spr[SPR_BOOKE_TCR] & TCR_FP_MASK) >> TCR_FP_SHIFT;
	98
	99	if (tb_env->flags & PPC_TIMER_E500) {
	100	/* e500 Fixed-interval timer period extension */
	101	uint32_t fpext = (env->spr[SPR_BOOKE_TCR] & TCR_E500_FPEXT_MASK)
	102	>> TCR_E500_FPEXT_SHIFT;
	103	fp = 63 - (fp \| fpext << 2);
	104	} else {
	105	fp = env->fit_period[fp];
	106	}
	107
	108	return fp;
	109	}
	110
	111	/* Return the location of the bit of time base at which the WDT will raise an
	112	interrupt */
e2684c0b	113	static uint8_t booke_get_wdt_target(CPUPPCState env, ppc_tb_t tb_env)
ddd1055b FC	114	{
	115	uint8_t wp = (env->spr[SPR_BOOKE_TCR] & TCR_WP_MASK) >> TCR_WP_SHIFT;
	116
	117	if (tb_env->flags & PPC_TIMER_E500) {
	118	/* e500 Watchdog timer period extension */
	119	uint32_t wpext = (env->spr[SPR_BOOKE_TCR] & TCR_E500_WPEXT_MASK)
	120	>> TCR_E500_WPEXT_SHIFT;
	121	wp = 63 - (wp \| wpext << 2);
	122	} else {
	123	wp = env->wdt_period[wp];
	124	}
	125
	126	return wp;
	127	}
	128
e2684c0b	129	static void booke_update_fixed_timer(CPUPPCState *env,
ddd1055b FC	130	uint8_t target_bit,
ddd1055b FC	131	uint64_t *next,
455df3f3 AG	132	QEMUTimer *timer,
455df3f3 AG	133	int tsr_bit)
ddd1055b FC	134	{
ddd1055b FC	135	ppc_tb_t *tb_env = env->tb_env;
ab8131af	136	uint64_t delta_tick, ticks = 0;
ddd1055b	137	uint64_t tb;
ab8131af	138	uint64_t period;
ddd1055b FC	139	uint64_t now;
ddd1055b FC	140
455df3f3 AG	141	if (!(env->spr[SPR_BOOKE_TSR] & tsr_bit)) {
	142	/*
	143	* Don't arm the timer again when the guest has the current
	144	* interrupt still pending. Wait for it to ack it.
	145	*/
	146	return;
	147	}
	148
bc72ad67	149	now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
ddd1055b	150	tb = cpu_ppc_get_tb(tb_env, now, tb_env->tb_offset);
ab8131af BB	151	period = 1ULL << target_bit;
ab8131af BB	152	delta_tick = period - (tb & (period - 1));
ddd1055b	153
ab8131af BB	154	/* the timer triggers only when the selected bit toggles from 0 to 1 */
	155	if (tb & period) {
	156	ticks = period;
	157	}
ddd1055b	158
ab8131af BB	159	if (ticks + delta_tick < ticks) {
	160	/* Overflow, so assume the biggest number we can express. */
	161	ticks = UINT64_MAX;
	162	} else {
	163	ticks += delta_tick;
	164	}
	165
	166	*next = now + muldiv64(ticks, get_ticks_per_sec(), tb_env->tb_freq);
	167	if ((next < now) \|\| (next > INT64_MAX)) {
	168	/* Overflow, so assume the biggest number the qemu timer supports. */
	169	*next = INT64_MAX;
	170	}
ddd1055b FC	171
	172	/* XXX: If expire time is now. We can't run the callback because we don't
	173	* have access to it. So we just set the timer one nanosecond later.
	174	*/
	175
	176	if (*next == now) {
	177	(*next)++;
84dc96e1 AG	178	} else {
	179	/*
	180	* There's no point to fake any granularity that's more fine grained
	181	* than milliseconds. Anything beyond that just overloads the system.
	182	*/
	183	next = MAX(next, now + SCALE_MS);
ddd1055b FC	184	}
ddd1055b FC	185
455df3f3	186	/* Fire the next timer */
bc72ad67	187	timer_mod(timer, *next);
ddd1055b FC	188	}
	189
	190	static void booke_decr_cb(void *opaque)
	191	{
ee0c98e6 AF	192	PowerPCCPU *cpu = opaque;
ee0c98e6 AF	193	CPUPPCState *env = &cpu->env;
ddd1055b	194
ddd1055b	195	env->spr[SPR_BOOKE_TSR] \|= TSR_DIS;
7058581a	196	booke_update_irq(cpu);
ddd1055b FC	197
	198	if (env->spr[SPR_BOOKE_TCR] & TCR_ARE) {
	199	/* Auto Reload */
	200	cpu_ppc_store_decr(env, env->spr[SPR_BOOKE_DECAR]);
	201	}
	202	}
	203
	204	static void booke_fit_cb(void *opaque)
	205	{
ee0c98e6 AF	206	PowerPCCPU *cpu = opaque;
ee0c98e6 AF	207	CPUPPCState *env = &cpu->env;
ddd1055b FC	208	ppc_tb_t *tb_env;
	209	booke_timer_t *booke_timer;
	210
ddd1055b FC	211	tb_env = env->tb_env;
	212	booke_timer = tb_env->opaque;
	213	env->spr[SPR_BOOKE_TSR] \|= TSR_FIS;
	214
7058581a	215	booke_update_irq(cpu);
ddd1055b FC	216
	217	booke_update_fixed_timer(env,
	218	booke_get_fit_target(env, tb_env),
	219	&booke_timer->fit_next,
455df3f3 AG	220	booke_timer->fit_timer,
455df3f3 AG	221	TSR_FIS);
ddd1055b FC	222	}
	223
	224	static void booke_wdt_cb(void *opaque)
	225	{
ee0c98e6 AF	226	PowerPCCPU *cpu = opaque;
ee0c98e6 AF	227	CPUPPCState *env = &cpu->env;
ddd1055b FC	228	ppc_tb_t *tb_env;
	229	booke_timer_t *booke_timer;
	230
ddd1055b FC	231	tb_env = env->tb_env;
	232	booke_timer = tb_env->opaque;
	233
	234	/* TODO: There's lots of complicated stuff to do here */
	235
7058581a	236	booke_update_irq(cpu);
ddd1055b FC	237
	238	booke_update_fixed_timer(env,
	239	booke_get_wdt_target(env, tb_env),
	240	&booke_timer->wdt_next,
455df3f3 AG	241	booke_timer->wdt_timer,
455df3f3 AG	242	TSR_WIS);
ddd1055b FC	243	}
ddd1055b FC	244
e2684c0b	245	void store_booke_tsr(CPUPPCState *env, target_ulong val)
ddd1055b	246	{
7058581a	247	PowerPCCPU *cpu = ppc_env_get_cpu(env);
455df3f3 AG	248	ppc_tb_t *tb_env = env->tb_env;
455df3f3 AG	249	booke_timer_t *booke_timer = tb_env->opaque;
7058581a	250
ddd1055b	251	env->spr[SPR_BOOKE_TSR] &= ~val;
31f2cb8f	252	kvmppc_clear_tsr_bits(cpu, val);
455df3f3 AG	253
	254	if (val & TSR_FIS) {
	255	booke_update_fixed_timer(env,
	256	booke_get_fit_target(env, tb_env),
	257	&booke_timer->fit_next,
	258	booke_timer->fit_timer,
	259	TSR_FIS);
	260	}
	261
	262	if (val & TSR_WIS) {
	263	booke_update_fixed_timer(env,
	264	booke_get_wdt_target(env, tb_env),
	265	&booke_timer->wdt_next,
	266	booke_timer->wdt_timer,
	267	TSR_WIS);
	268	}
	269
7058581a	270	booke_update_irq(cpu);
ddd1055b FC	271	}
ddd1055b FC	272
e2684c0b	273	void store_booke_tcr(CPUPPCState *env, target_ulong val)
ddd1055b	274	{
7058581a	275	PowerPCCPU *cpu = ppc_env_get_cpu(env);
ddd1055b FC	276	ppc_tb_t *tb_env = env->tb_env;
	277	booke_timer_t *booke_timer = tb_env->opaque;
	278
	279	tb_env = env->tb_env;
	280	env->spr[SPR_BOOKE_TCR] = val;
31f2cb8f	281	kvmppc_set_tcr(cpu);
ddd1055b	282
7058581a	283	booke_update_irq(cpu);
ddd1055b FC	284
	285	booke_update_fixed_timer(env,
	286	booke_get_fit_target(env, tb_env),
	287	&booke_timer->fit_next,
455df3f3 AG	288	booke_timer->fit_timer,
455df3f3 AG	289	TSR_FIS);
ddd1055b FC	290
	291	booke_update_fixed_timer(env,
	292	booke_get_wdt_target(env, tb_env),
	293	&booke_timer->wdt_next,
455df3f3 AG	294	booke_timer->wdt_timer,
455df3f3 AG	295	TSR_WIS);
ddd1055b FC	296	}
ddd1055b FC	297
88a78d90 BB	298	static void ppc_booke_timer_reset_handle(void *opaque)
	299	{
	300	PowerPCCPU *cpu = opaque;
	301	CPUPPCState *env = &cpu->env;
	302
31f2cb8f BB	303	store_booke_tcr(env, 0);
	304	store_booke_tsr(env, -1);
	305	}
88a78d90	306
31f2cb8f BB	307	/*
	308	* This function will be called whenever the CPU state changes.
	309	* CPU states are defined "typedef enum RunState".
	310	* Regarding timer, When CPU state changes to running after debug halt
	311	* or similar cases which takes time then in between final watchdog
	312	* expiry happenes. This will cause exit to QEMU and configured watchdog
	313	* action will be taken. To avoid this we always clear the watchdog state when
	314	* state changes to running.
	315	*/
	316	static void cpu_state_change_handler(void *opaque, int running, RunState state)
	317	{
	318	PowerPCCPU *cpu = opaque;
	319	CPUPPCState *env = &cpu->env;
	320
	321	if (!running) {
	322	return;
	323	}
	324
	325	/*
	326	* Clear watchdog interrupt condition by clearing TSR.
	327	*/
	328	store_booke_tsr(env, TSR_ENW \| TSR_WIS \| TSR_WRS_MASK);
88a78d90 BB	329	}
88a78d90 BB	330
a34a92b9	331	void ppc_booke_timers_init(PowerPCCPU *cpu, uint32_t freq, uint32_t flags)
ddd1055b FC	332	{
	333	ppc_tb_t *tb_env;
	334	booke_timer_t *booke_timer;
31f2cb8f	335	int ret = 0;
ddd1055b FC	336
	337	tb_env = g_malloc0(sizeof(ppc_tb_t));
	338	booke_timer = g_malloc0(sizeof(booke_timer_t));
	339
a34a92b9	340	cpu->env.tb_env = tb_env;
ddd1055b FC	341	tb_env->flags = flags \| PPC_TIMER_BOOKE \| PPC_DECR_ZERO_TRIGGERED;
	342
	343	tb_env->tb_freq = freq;
	344	tb_env->decr_freq = freq;
	345	tb_env->opaque = booke_timer;
bc72ad67	346	tb_env->decr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &booke_decr_cb, cpu);
ddd1055b FC	347
ddd1055b FC	348	booke_timer->fit_timer =
bc72ad67	349	timer_new_ns(QEMU_CLOCK_VIRTUAL, &booke_fit_cb, cpu);
ddd1055b	350	booke_timer->wdt_timer =
bc72ad67	351	timer_new_ns(QEMU_CLOCK_VIRTUAL, &booke_wdt_cb, cpu);
88a78d90	352
31f2cb8f BB	353	ret = kvmppc_booke_watchdog_enable(cpu);
	354
	355	if (ret) {
	356	/* TODO: Start the QEMU emulated watchdog if not running on KVM.
	357	* Also start the QEMU emulated watchdog if KVM does not support
	358	* emulated watchdog or somehow it is not enabled (supported but
	359	* not enabled is though some bug and requires debugging :)).
	360	*/
	361	}
	362
	363	qemu_add_vm_change_state_handler(cpu_state_change_handler, cpu);
	364
88a78d90	365	qemu_register_reset(ppc_booke_timer_reset_handle, cpu);
ddd1055b	366	}