[qemu.git] / hw / s390x / s390-pci-bus.h

/*
 * s390 PCI BUS definitions
 *
 * Copyright 2014 IBM Corp.
 * Author(s): Frank Blaschka <[email protected]>
 *            Hong Bo Li <[email protected]>
 *            Yi Min Zhao <[email protected]>
 *
 * This work is licensed under the terms of the GNU GPL, version 2 or (at
 * your option) any later version. See the COPYING file in the top-level
 * directory.
 */

#ifndef HW_S390_PCI_BUS_H
#define HW_S390_PCI_BUS_H

#include "hw/pci/pci.h"
#include "hw/pci/pci_host.h"
#include "hw/s390x/sclp.h"
#include "hw/s390x/s390_flic.h"
#include "hw/s390x/css.h"

#define TYPE_S390_PCI_HOST_BRIDGE "s390-pcihost"
#define TYPE_S390_PCI_BUS "s390-pcibus"
#define TYPE_S390_PCI_DEVICE "zpci"
#define TYPE_S390_PCI_IOMMU "s390-pci-iommu"
#define FH_MASK_ENABLE   0x80000000
#define FH_MASK_INSTANCE 0x7f000000
#define FH_MASK_SHM      0x00ff0000
#define FH_MASK_INDEX    0x0000ffff
#define FH_SHM_VFIO      0x00010000
#define FH_SHM_EMUL      0x00020000
#define ZPCI_MAX_FID 0xffffffff
#define ZPCI_MAX_UID 0xffff
#define UID_UNDEFINED 0
#define UID_CHECKING_ENABLED 0x01
#define HOT_UNPLUG_TIMEOUT (NANOSECONDS_PER_SECOND * 60 * 5)

#define S390_PCI_HOST_BRIDGE(obj) \
    OBJECT_CHECK(S390pciState, (obj), TYPE_S390_PCI_HOST_BRIDGE)
#define S390_PCI_BUS(obj) \
    OBJECT_CHECK(S390PCIBus, (obj), TYPE_S390_PCI_BUS)
#define S390_PCI_DEVICE(obj) \
    OBJECT_CHECK(S390PCIBusDevice, (obj), TYPE_S390_PCI_DEVICE)
#define S390_PCI_IOMMU(obj) \
    OBJECT_CHECK(S390PCIIOMMU, (obj), TYPE_S390_PCI_IOMMU)

#define HP_EVENT_TO_CONFIGURED        0x0301
#define HP_EVENT_RESERVED_TO_STANDBY  0x0302
#define HP_EVENT_DECONFIGURE_REQUEST  0x0303
#define HP_EVENT_CONFIGURED_TO_STBRES 0x0304
#define HP_EVENT_STANDBY_TO_RESERVED  0x0308

#define ERR_EVENT_INVALAS 0x1
#define ERR_EVENT_OORANGE 0x2
#define ERR_EVENT_INVALTF 0x3
#define ERR_EVENT_TPROTE  0x4
#define ERR_EVENT_APROTE  0x5
#define ERR_EVENT_KEYE    0x6
#define ERR_EVENT_INVALTE 0x7
#define ERR_EVENT_INVALTL 0x8
#define ERR_EVENT_TT      0x9
#define ERR_EVENT_INVALMS 0xa
#define ERR_EVENT_SERR    0xb
#define ERR_EVENT_NOMSI   0x10
#define ERR_EVENT_INVALBV 0x11
#define ERR_EVENT_AIBV    0x12
#define ERR_EVENT_AIRERR  0x13
#define ERR_EVENT_FMBA    0x2a
#define ERR_EVENT_FMBUP   0x2b
#define ERR_EVENT_FMBPRO  0x2c
#define ERR_EVENT_CCONF   0x30
#define ERR_EVENT_SERVAC  0x3a
#define ERR_EVENT_PERMERR 0x3b

#define ERR_EVENT_Q_BIT 0x2
#define ERR_EVENT_MVN_OFFSET 16

#define ZPCI_MSI_VEC_BITS 11
#define ZPCI_MSI_VEC_MASK 0x7ff

#define ZPCI_MSI_ADDR  0xfe00000000000000ULL
#define ZPCI_SDMA_ADDR 0x100000000ULL
#define ZPCI_EDMA_ADDR 0x1ffffffffffffffULL

#define PAGE_SHIFT      12
#define PAGE_SIZE       (1 << PAGE_SHIFT)
#define PAGE_MASK       (~(PAGE_SIZE-1))
#define PAGE_DEFAULT_ACC        0
#define PAGE_DEFAULT_KEY        (PAGE_DEFAULT_ACC << 4)

/* I/O Translation Anchor (IOTA) */
enum ZpciIoatDtype {
    ZPCI_IOTA_STO = 0,
    ZPCI_IOTA_RTTO = 1,
    ZPCI_IOTA_RSTO = 2,
    ZPCI_IOTA_RFTO = 3,
    ZPCI_IOTA_PFAA = 4,
    ZPCI_IOTA_IOPFAA = 5,
    ZPCI_IOTA_IOPTO = 7
};

#define ZPCI_IOTA_IOT_ENABLED           0x800ULL
#define ZPCI_IOTA_DT_ST                 (ZPCI_IOTA_STO  << 2)
#define ZPCI_IOTA_DT_RT                 (ZPCI_IOTA_RTTO << 2)
#define ZPCI_IOTA_DT_RS                 (ZPCI_IOTA_RSTO << 2)
#define ZPCI_IOTA_DT_RF                 (ZPCI_IOTA_RFTO << 2)
#define ZPCI_IOTA_DT_PF                 (ZPCI_IOTA_PFAA << 2)
#define ZPCI_IOTA_FS_4K                 0
#define ZPCI_IOTA_FS_1M                 1
#define ZPCI_IOTA_FS_2G                 2
#define ZPCI_KEY                        (PAGE_DEFAULT_KEY << 5)

#define ZPCI_IOTA_STO_FLAG  (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_ST)
#define ZPCI_IOTA_RTTO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_RT)
#define ZPCI_IOTA_RSTO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_RS)
#define ZPCI_IOTA_RFTO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_RF)
#define ZPCI_IOTA_RFAA_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY |\
                             ZPCI_IOTA_DT_PF | ZPCI_IOTA_FS_2G)

/* I/O Region and segment tables */
#define ZPCI_INDEX_MASK         0x7ffULL

#define ZPCI_TABLE_TYPE_MASK    0xc
#define ZPCI_TABLE_TYPE_RFX     0xc
#define ZPCI_TABLE_TYPE_RSX     0x8
#define ZPCI_TABLE_TYPE_RTX     0x4
#define ZPCI_TABLE_TYPE_SX      0x0

#define ZPCI_TABLE_LEN_RFX      0x3
#define ZPCI_TABLE_LEN_RSX      0x3
#define ZPCI_TABLE_LEN_RTX      0x3

#define ZPCI_TABLE_OFFSET_MASK  0xc0
#define ZPCI_TABLE_SIZE         0x4000
#define ZPCI_TABLE_ALIGN        ZPCI_TABLE_SIZE
#define ZPCI_TABLE_ENTRY_SIZE   (sizeof(unsigned long))
#define ZPCI_TABLE_ENTRIES      (ZPCI_TABLE_SIZE / ZPCI_TABLE_ENTRY_SIZE)

#define ZPCI_TABLE_BITS         11
#define ZPCI_PT_BITS            8
#define ZPCI_ST_SHIFT           (ZPCI_PT_BITS + PAGE_SHIFT)
#define ZPCI_RT_SHIFT           (ZPCI_ST_SHIFT + ZPCI_TABLE_BITS)

#define ZPCI_RTE_FLAG_MASK      0x3fffULL
#define ZPCI_RTE_ADDR_MASK      (~ZPCI_RTE_FLAG_MASK)
#define ZPCI_STE_FLAG_MASK      0x7ffULL
#define ZPCI_STE_ADDR_MASK      (~ZPCI_STE_FLAG_MASK)

/* I/O Page tables */
#define ZPCI_PTE_VALID_MASK             0x400
#define ZPCI_PTE_INVALID                0x400
#define ZPCI_PTE_VALID                  0x000
#define ZPCI_PT_SIZE                    0x800
#define ZPCI_PT_ALIGN                   ZPCI_PT_SIZE
#define ZPCI_PT_ENTRIES                 (ZPCI_PT_SIZE / ZPCI_TABLE_ENTRY_SIZE)
#define ZPCI_PT_MASK                    (ZPCI_PT_ENTRIES - 1)

#define ZPCI_PTE_FLAG_MASK              0xfffULL
#define ZPCI_PTE_ADDR_MASK              (~ZPCI_PTE_FLAG_MASK)

/* Shared bits */
#define ZPCI_TABLE_VALID                0x00
#define ZPCI_TABLE_INVALID              0x20
#define ZPCI_TABLE_PROTECTED            0x200
#define ZPCI_TABLE_UNPROTECTED          0x000

#define ZPCI_TABLE_VALID_MASK           0x20
#define ZPCI_TABLE_PROT_MASK            0x200

/* PCI Function States
 *
 * reserved: default; device has just been plugged or is in progress of being
 *           unplugged
 * standby: device is present but not configured; transition from any
 *          configured state/to this state via sclp configure/deconfigure
 *
 * The following states make up the "configured" meta-state:
 * disabled: device is configured but not enabled; transition between this
 *           state and enabled via clp enable/disable
 * enbaled: device is ready for use; transition to disabled via clp disable;
 *          may enter an error state
 * blocked: ignore all DMA and interrupts; transition back to enabled or from
 *          error state via mpcifc
 * error: an error occurred; transition back to enabled via mpcifc
 * permanent error: an unrecoverable error occurred; transition to standby via
 *                  sclp deconfigure
 */
typedef enum {
    ZPCI_FS_RESERVED,
    ZPCI_FS_STANDBY,
    ZPCI_FS_DISABLED,
    ZPCI_FS_ENABLED,
    ZPCI_FS_BLOCKED,
    ZPCI_FS_ERROR,
    ZPCI_FS_PERMANENT_ERROR,
} ZpciState;

typedef struct SeiContainer {
    QTAILQ_ENTRY(SeiContainer) link;
    uint32_t fid;
    uint32_t fh;
    uint8_t cc;
    uint16_t pec;
    uint64_t faddr;
    uint32_t e;
} SeiContainer;

typedef struct PciCcdfErr {
    uint32_t reserved1;
    uint32_t fh;
    uint32_t fid;
    uint32_t e;
    uint64_t faddr;
    uint32_t reserved3;
    uint16_t reserved4;
    uint16_t pec;
} QEMU_PACKED PciCcdfErr;

typedef struct PciCcdfAvail {
    uint32_t reserved1;
    uint32_t fh;
    uint32_t fid;
    uint32_t reserved2;
    uint32_t reserved3;
    uint32_t reserved4;
    uint32_t reserved5;
    uint16_t reserved6;
    uint16_t pec;
} QEMU_PACKED PciCcdfAvail;

typedef struct ChscSeiNt2Res {
    uint16_t length;
    uint16_t code;
    uint16_t reserved1;
    uint8_t reserved2;
    uint8_t nt;
    uint8_t flags;
    uint8_t reserved3;
    uint8_t reserved4;
    uint8_t cc;
    uint32_t reserved5[13];
    uint8_t ccdf[4016];
} QEMU_PACKED ChscSeiNt2Res;

typedef struct PciCfgSccb {
    SCCBHeader header;
    uint8_t atype;
    uint8_t reserved1;
    uint16_t reserved2;
    uint32_t aid;
} QEMU_PACKED PciCfgSccb;

typedef struct S390MsixInfo {
    bool available;
    uint8_t table_bar;
    uint8_t pba_bar;
    uint16_t entries;
    uint32_t table_offset;
    uint32_t pba_offset;
} S390MsixInfo;

typedef struct S390PCIBusDevice S390PCIBusDevice;
typedef struct S390PCIIOMMU {
    Object parent_obj;
    S390PCIBusDevice *pbdev;
    AddressSpace as;
    MemoryRegion mr;
    IOMMUMemoryRegion iommu_mr;
    bool enabled;
    uint64_t g_iota;
    uint64_t pba;
    uint64_t pal;
} S390PCIIOMMU;

typedef struct S390PCIIOMMUTable {
    uint64_t key;
    S390PCIIOMMU *iommu[PCI_SLOT_MAX];
} S390PCIIOMMUTable;

struct S390PCIBusDevice {
    DeviceState qdev;
    PCIDevice *pdev;
    ZpciState state;
    char *target;
    uint16_t uid;
    uint32_t idx;
    uint32_t fh;
    uint32_t fid;
    bool fid_defined;
    uint64_t fmb_addr;
    uint8_t isc;
    uint16_t noi;
    uint8_t sum;
    S390MsixInfo msix;
    AdapterRoutes routes;
    S390PCIIOMMU *iommu;
    MemoryRegion msix_notify_mr;
    IndAddr *summary_ind;
    IndAddr *indicator;
    QEMUTimer *release_timer;
    QTAILQ_ENTRY(S390PCIBusDevice) link;
};

typedef struct S390PCIBus {
    BusState qbus;
} S390PCIBus;

typedef struct S390pciState {
    PCIHostState parent_obj;
    uint32_t next_idx;
    int bus_no;
    S390PCIBus *bus;
    GHashTable *iommu_table;
    GHashTable *zpci_table;
    QTAILQ_HEAD(, SeiContainer) pending_sei;
    QTAILQ_HEAD(, S390PCIBusDevice) zpci_devs;
} S390pciState;

S390pciState *s390_get_phb(void);
int chsc_sei_nt2_get_event(void *res);
int chsc_sei_nt2_have_event(void);
void s390_pci_sclp_configure(SCCB *sccb);
void s390_pci_sclp_deconfigure(SCCB *sccb);
void s390_pci_iommu_enable(S390PCIIOMMU *iommu);
void s390_pci_iommu_disable(S390PCIIOMMU *iommu);
void s390_pci_generate_error_event(uint16_t pec, uint32_t fh, uint32_t fid,
                                   uint64_t faddr, uint32_t e);
S390PCIBusDevice *s390_pci_find_dev_by_idx(S390pciState *s, uint32_t idx);
S390PCIBusDevice *s390_pci_find_dev_by_fh(S390pciState *s, uint32_t fh);
S390PCIBusDevice *s390_pci_find_dev_by_fid(S390pciState *s, uint32_t fid);
S390PCIBusDevice *s390_pci_find_next_avail_dev(S390pciState *s,
                                               S390PCIBusDevice *pbdev);

#endif
Commit	Line	Data
8cba80c3 FB	1	/*
	2	* s390 PCI BUS definitions
	3	*
	4	* Copyright 2014 IBM Corp.
	5	* Author(s): Frank Blaschka <[email protected]>
	6	* Hong Bo Li <[email protected]>
	7	* Yi Min Zhao <[email protected]>
	8	*
	9	* This work is licensed under the terms of the GNU GPL, version 2 or (at
	10	* your option) any later version. See the COPYING file in the top-level
	11	* directory.
	12	*/
	13
	14	#ifndef HW_S390_PCI_BUS_H
	15	#define HW_S390_PCI_BUS_H
	16
a9c94277 MA	17	#include "hw/pci/pci.h"
a9c94277 MA	18	#include "hw/pci/pci_host.h"
8cba80c3 FB	19	#include "hw/s390x/sclp.h"
	20	#include "hw/s390x/s390_flic.h"
	21	#include "hw/s390x/css.h"
	22
	23	#define TYPE_S390_PCI_HOST_BRIDGE "s390-pcihost"
90a0f9af	24	#define TYPE_S390_PCI_BUS "s390-pcibus"
3e5cfba3	25	#define TYPE_S390_PCI_DEVICE "zpci"
de91ea92	26	#define TYPE_S390_PCI_IOMMU "s390-pci-iommu"
c188e303 YMZ	27	#define FH_MASK_ENABLE 0x80000000
	28	#define FH_MASK_INSTANCE 0x7f000000
	29	#define FH_MASK_SHM 0x00ff0000
e70377df	30	#define FH_MASK_INDEX 0x0000ffff
c188e303 YMZ	31	#define FH_SHM_VFIO 0x00010000
c188e303 YMZ	32	#define FH_SHM_EMUL 0x00020000
3e5cfba3 YMZ	33	#define ZPCI_MAX_FID 0xffffffff
	34	#define ZPCI_MAX_UID 0xffff
	35	#define UID_UNDEFINED 0
bf328399	36	#define UID_CHECKING_ENABLED 0x01
93d16d81	37	#define HOT_UNPLUG_TIMEOUT (NANOSECONDS_PER_SECOND * 60 * 5)
8cba80c3 FB	38
	39	#define S390_PCI_HOST_BRIDGE(obj) \
	40	OBJECT_CHECK(S390pciState, (obj), TYPE_S390_PCI_HOST_BRIDGE)
90a0f9af YMZ	41	#define S390_PCI_BUS(obj) \
90a0f9af YMZ	42	OBJECT_CHECK(S390PCIBus, (obj), TYPE_S390_PCI_BUS)
3e5cfba3 YMZ	43	#define S390_PCI_DEVICE(obj) \
3e5cfba3 YMZ	44	OBJECT_CHECK(S390PCIBusDevice, (obj), TYPE_S390_PCI_DEVICE)
de91ea92 YMZ	45	#define S390_PCI_IOMMU(obj) \
de91ea92 YMZ	46	OBJECT_CHECK(S390PCIIOMMU, (obj), TYPE_S390_PCI_IOMMU)
8cba80c3 FB	47
	48	#define HP_EVENT_TO_CONFIGURED 0x0301
	49	#define HP_EVENT_RESERVED_TO_STANDBY 0x0302
93d16d81	50	#define HP_EVENT_DECONFIGURE_REQUEST 0x0303
8cba80c3 FB	51	#define HP_EVENT_CONFIGURED_TO_STBRES 0x0304
	52	#define HP_EVENT_STANDBY_TO_RESERVED 0x0308
	53
	54	#define ERR_EVENT_INVALAS 0x1
	55	#define ERR_EVENT_OORANGE 0x2
	56	#define ERR_EVENT_INVALTF 0x3
	57	#define ERR_EVENT_TPROTE 0x4
	58	#define ERR_EVENT_APROTE 0x5
	59	#define ERR_EVENT_KEYE 0x6
	60	#define ERR_EVENT_INVALTE 0x7
	61	#define ERR_EVENT_INVALTL 0x8
	62	#define ERR_EVENT_TT 0x9
	63	#define ERR_EVENT_INVALMS 0xa
	64	#define ERR_EVENT_SERR 0xb
	65	#define ERR_EVENT_NOMSI 0x10
	66	#define ERR_EVENT_INVALBV 0x11
	67	#define ERR_EVENT_AIBV 0x12
	68	#define ERR_EVENT_AIRERR 0x13
	69	#define ERR_EVENT_FMBA 0x2a
	70	#define ERR_EVENT_FMBUP 0x2b
	71	#define ERR_EVENT_FMBPRO 0x2c
	72	#define ERR_EVENT_CCONF 0x30
	73	#define ERR_EVENT_SERVAC 0x3a
	74	#define ERR_EVENT_PERMERR 0x3b
	75
	76	#define ERR_EVENT_Q_BIT 0x2
	77	#define ERR_EVENT_MVN_OFFSET 16
	78
	79	#define ZPCI_MSI_VEC_BITS 11
	80	#define ZPCI_MSI_VEC_MASK 0x7ff
	81
	82	#define ZPCI_MSI_ADDR 0xfe00000000000000ULL
	83	#define ZPCI_SDMA_ADDR 0x100000000ULL
	84	#define ZPCI_EDMA_ADDR 0x1ffffffffffffffULL
	85
	86	#define PAGE_SHIFT 12
8f955950	87	#define PAGE_SIZE (1 << PAGE_SHIFT)
8cba80c3 FB	88	#define PAGE_MASK (~(PAGE_SIZE-1))
	89	#define PAGE_DEFAULT_ACC 0
	90	#define PAGE_DEFAULT_KEY (PAGE_DEFAULT_ACC << 4)
	91
	92	/* I/O Translation Anchor (IOTA) */
	93	enum ZpciIoatDtype {
	94	ZPCI_IOTA_STO = 0,
	95	ZPCI_IOTA_RTTO = 1,
	96	ZPCI_IOTA_RSTO = 2,
	97	ZPCI_IOTA_RFTO = 3,
	98	ZPCI_IOTA_PFAA = 4,
	99	ZPCI_IOTA_IOPFAA = 5,
	100	ZPCI_IOTA_IOPTO = 7
	101	};
	102
	103	#define ZPCI_IOTA_IOT_ENABLED 0x800ULL
	104	#define ZPCI_IOTA_DT_ST (ZPCI_IOTA_STO << 2)
	105	#define ZPCI_IOTA_DT_RT (ZPCI_IOTA_RTTO << 2)
	106	#define ZPCI_IOTA_DT_RS (ZPCI_IOTA_RSTO << 2)
	107	#define ZPCI_IOTA_DT_RF (ZPCI_IOTA_RFTO << 2)
	108	#define ZPCI_IOTA_DT_PF (ZPCI_IOTA_PFAA << 2)
	109	#define ZPCI_IOTA_FS_4K 0
	110	#define ZPCI_IOTA_FS_1M 1
	111	#define ZPCI_IOTA_FS_2G 2
	112	#define ZPCI_KEY (PAGE_DEFAULT_KEY << 5)
	113
	114	#define ZPCI_IOTA_STO_FLAG (ZPCI_IOTA_IOT_ENABLED \| ZPCI_KEY \| ZPCI_IOTA_DT_ST)
	115	#define ZPCI_IOTA_RTTO_FLAG (ZPCI_IOTA_IOT_ENABLED \| ZPCI_KEY \| ZPCI_IOTA_DT_RT)
	116	#define ZPCI_IOTA_RSTO_FLAG (ZPCI_IOTA_IOT_ENABLED \| ZPCI_KEY \| ZPCI_IOTA_DT_RS)
	117	#define ZPCI_IOTA_RFTO_FLAG (ZPCI_IOTA_IOT_ENABLED \| ZPCI_KEY \| ZPCI_IOTA_DT_RF)
	118	#define ZPCI_IOTA_RFAA_FLAG (ZPCI_IOTA_IOT_ENABLED \| ZPCI_KEY \|\
	119	ZPCI_IOTA_DT_PF \| ZPCI_IOTA_FS_2G)
	120
	121	/* I/O Region and segment tables */
	122	#define ZPCI_INDEX_MASK 0x7ffULL
	123
	124	#define ZPCI_TABLE_TYPE_MASK 0xc
	125	#define ZPCI_TABLE_TYPE_RFX 0xc
	126	#define ZPCI_TABLE_TYPE_RSX 0x8
	127	#define ZPCI_TABLE_TYPE_RTX 0x4
	128	#define ZPCI_TABLE_TYPE_SX 0x0
	129
	130	#define ZPCI_TABLE_LEN_RFX 0x3
	131	#define ZPCI_TABLE_LEN_RSX 0x3
	132	#define ZPCI_TABLE_LEN_RTX 0x3
	133
	134	#define ZPCI_TABLE_OFFSET_MASK 0xc0
	135	#define ZPCI_TABLE_SIZE 0x4000
	136	#define ZPCI_TABLE_ALIGN ZPCI_TABLE_SIZE
	137	#define ZPCI_TABLE_ENTRY_SIZE (sizeof(unsigned long))
	138	#define ZPCI_TABLE_ENTRIES (ZPCI_TABLE_SIZE / ZPCI_TABLE_ENTRY_SIZE)
	139
	140	#define ZPCI_TABLE_BITS 11
	141	#define ZPCI_PT_BITS 8
	142	#define ZPCI_ST_SHIFT (ZPCI_PT_BITS + PAGE_SHIFT)
	143	#define ZPCI_RT_SHIFT (ZPCI_ST_SHIFT + ZPCI_TABLE_BITS)
	144
	145	#define ZPCI_RTE_FLAG_MASK 0x3fffULL
	146	#define ZPCI_RTE_ADDR_MASK (~ZPCI_RTE_FLAG_MASK)
	147	#define ZPCI_STE_FLAG_MASK 0x7ffULL
	148	#define ZPCI_STE_ADDR_MASK (~ZPCI_STE_FLAG_MASK)
	149
	150	/* I/O Page tables */
	151	#define ZPCI_PTE_VALID_MASK 0x400
152	#define ZPCI_PTE_INVALID 0x400
153	#define ZPCI_PTE_VALID 0x000
154	#define ZPCI_PT_SIZE 0x800
155	#define ZPCI_PT_ALIGN ZPCI_PT_SIZE
156	#define ZPCI_PT_ENTRIES (ZPCI_PT_SIZE / ZPCI_TABLE_ENTRY_SIZE)
157	#define ZPCI_PT_MASK (ZPCI_PT_ENTRIES - 1)
158
159	#define ZPCI_PTE_FLAG_MASK 0xfffULL
160	#define ZPCI_PTE_ADDR_MASK (~ZPCI_PTE_FLAG_MASK)
161
162	/* Shared bits */
163	#define ZPCI_TABLE_VALID 0x00
164	#define ZPCI_TABLE_INVALID 0x20
165	#define ZPCI_TABLE_PROTECTED 0x200
166	#define ZPCI_TABLE_UNPROTECTED 0x000
167
168	#define ZPCI_TABLE_VALID_MASK 0x20
169	#define ZPCI_TABLE_PROT_MASK 0x200
170
5d1abf23 YMZ	171	/* PCI Function States
	172	*
	173	* reserved: default; device has just been plugged or is in progress of being
	174	* unplugged
	175	* standby: device is present but not configured; transition from any
	176	* configured state/to this state via sclp configure/deconfigure
	177	*
	178	* The following states make up the "configured" meta-state:
	179	* disabled: device is configured but not enabled; transition between this
	180	* state and enabled via clp enable/disable
	181	* enbaled: device is ready for use; transition to disabled via clp disable;
	182	* may enter an error state
	183	* blocked: ignore all DMA and interrupts; transition back to enabled or from
	184	* error state via mpcifc
b12227af SW	185	* error: an error occurred; transition back to enabled via mpcifc
b12227af SW	186	* permanent error: an unrecoverable error occurred; transition to standby via
5d1abf23 YMZ	187	* sclp deconfigure
	188	*/
	189	typedef enum {
	190	ZPCI_FS_RESERVED,
	191	ZPCI_FS_STANDBY,
	192	ZPCI_FS_DISABLED,
	193	ZPCI_FS_ENABLED,
	194	ZPCI_FS_BLOCKED,
	195	ZPCI_FS_ERROR,
	196	ZPCI_FS_PERMANENT_ERROR,
	197	} ZpciState;
	198
8cba80c3 FB	199	typedef struct SeiContainer {
	200	QTAILQ_ENTRY(SeiContainer) link;
	201	uint32_t fid;
	202	uint32_t fh;
	203	uint8_t cc;
	204	uint16_t pec;
	205	uint64_t faddr;
	206	uint32_t e;
	207	} SeiContainer;
	208
	209	typedef struct PciCcdfErr {
	210	uint32_t reserved1;
	211	uint32_t fh;
	212	uint32_t fid;
	213	uint32_t e;
	214	uint64_t faddr;
	215	uint32_t reserved3;
	216	uint16_t reserved4;
	217	uint16_t pec;
	218	} QEMU_PACKED PciCcdfErr;
	219
	220	typedef struct PciCcdfAvail {
	221	uint32_t reserved1;
	222	uint32_t fh;
	223	uint32_t fid;
	224	uint32_t reserved2;
	225	uint32_t reserved3;
	226	uint32_t reserved4;
	227	uint32_t reserved5;
	228	uint16_t reserved6;
	229	uint16_t pec;
	230	} QEMU_PACKED PciCcdfAvail;
	231
	232	typedef struct ChscSeiNt2Res {
	233	uint16_t length;
	234	uint16_t code;
	235	uint16_t reserved1;
	236	uint8_t reserved2;
	237	uint8_t nt;
	238	uint8_t flags;
	239	uint8_t reserved3;
	240	uint8_t reserved4;
	241	uint8_t cc;
	242	uint32_t reserved5[13];
	243	uint8_t ccdf[4016];
	244	} QEMU_PACKED ChscSeiNt2Res;
	245
	246	typedef struct PciCfgSccb {
c2691694 YMZ	247	SCCBHeader header;
	248	uint8_t atype;
	249	uint8_t reserved1;
	250	uint16_t reserved2;
	251	uint32_t aid;
8cba80c3 FB	252	} QEMU_PACKED PciCfgSccb;
	253
	254	typedef struct S390MsixInfo {
	255	bool available;
	256	uint8_t table_bar;
	257	uint8_t pba_bar;
	258	uint16_t entries;
	259	uint32_t table_offset;
	260	uint32_t pba_offset;
	261	} S390MsixInfo;
	262
de91ea92	263	typedef struct S390PCIBusDevice S390PCIBusDevice;
67d5cd97	264	typedef struct S390PCIIOMMU {
de91ea92 YMZ	265	Object parent_obj;
de91ea92 YMZ	266	S390PCIBusDevice *pbdev;
67d5cd97 YMZ	267	AddressSpace as;
67d5cd97 YMZ	268	MemoryRegion mr;
3df9d748	269	IOMMUMemoryRegion iommu_mr;
de91ea92 YMZ	270	bool enabled;
	271	uint64_t g_iota;
	272	uint64_t pba;
	273	uint64_t pal;
67d5cd97 YMZ	274	} S390PCIIOMMU;
67d5cd97 YMZ	275
03805be0 YMZ	276	typedef struct S390PCIIOMMUTable {
	277	uint64_t key;
	278	S390PCIIOMMU *iommu[PCI_SLOT_MAX];
	279	} S390PCIIOMMUTable;
	280
2034ee51	281	struct S390PCIBusDevice {
3e5cfba3	282	DeviceState qdev;
8cba80c3	283	PCIDevice *pdev;
5d1abf23	284	ZpciState state;
3e5cfba3 YMZ	285	char *target;
3e5cfba3 YMZ	286	uint16_t uid;
e70377df	287	uint32_t idx;
8cba80c3 FB	288	uint32_t fh;
8cba80c3 FB	289	uint32_t fid;
3e5cfba3	290	bool fid_defined;
8cba80c3 FB	291	uint64_t fmb_addr;
	292	uint8_t isc;
	293	uint16_t noi;
	294	uint8_t sum;
	295	S390MsixInfo msix;
	296	AdapterRoutes routes;
67d5cd97	297	S390PCIIOMMU *iommu;
8f955950	298	MemoryRegion msix_notify_mr;
8581c115 YMZ	299	IndAddr *summary_ind;
8581c115 YMZ	300	IndAddr *indicator;
93d16d81	301	QEMUTimer *release_timer;
e70377df	302	QTAILQ_ENTRY(S390PCIBusDevice) link;
2034ee51	303	};
8cba80c3	304
90a0f9af YMZ	305	typedef struct S390PCIBus {
	306	BusState qbus;
	307	} S390PCIBus;
	308
8cba80c3 FB	309	typedef struct S390pciState {
8cba80c3 FB	310	PCIHostState parent_obj;
e70377df	311	uint32_t next_idx;
d2f07120	312	int bus_no;
90a0f9af	313	S390PCIBus *bus;
03805be0	314	GHashTable *iommu_table;
df8dd91b	315	GHashTable *zpci_table;
8cba80c3	316	QTAILQ_HEAD(, SeiContainer) pending_sei;
e70377df	317	QTAILQ_HEAD(, S390PCIBusDevice) zpci_devs;
8cba80c3 FB	318	} S390pciState;
8cba80c3 FB	319
a975a24a	320	S390pciState *s390_get_phb(void);
8cba80c3 FB	321	int chsc_sei_nt2_get_event(void *res);
8cba80c3 FB	322	int chsc_sei_nt2_have_event(void);
8f5cb693 YMZ	323	void s390_pci_sclp_configure(SCCB *sccb);
8f5cb693 YMZ	324	void s390_pci_sclp_deconfigure(SCCB *sccb);
de91ea92 YMZ	325	void s390_pci_iommu_enable(S390PCIIOMMU *iommu);
de91ea92 YMZ	326	void s390_pci_iommu_disable(S390PCIIOMMU *iommu);
5d1abf23 YMZ	327	void s390_pci_generate_error_event(uint16_t pec, uint32_t fh, uint32_t fid,
5d1abf23 YMZ	328	uint64_t faddr, uint32_t e);
a975a24a YMZ	329	S390PCIBusDevice s390_pci_find_dev_by_idx(S390pciState s, uint32_t idx);
	330	S390PCIBusDevice s390_pci_find_dev_by_fh(S390pciState s, uint32_t fh);
	331	S390PCIBusDevice s390_pci_find_dev_by_fid(S390pciState s, uint32_t fid);
	332	S390PCIBusDevice s390_pci_find_next_avail_dev(S390pciState s,
	333	S390PCIBusDevice *pbdev);
8cba80c3 FB	334
8cba80c3 FB	335	#endif