[qemu.git] / hw / pci-host / q35.c

/*
 * QEMU MCH/ICH9 PCI Bridge Emulation
 *
 * Copyright (c) 2006 Fabrice Bellard
 * Copyright (c) 2009, 2010, 2011
 *               Isaku Yamahata <yamahata at valinux co jp>
 *               VA Linux Systems Japan K.K.
 * Copyright (C) 2012 Jason Baron <[email protected]>
 *
 * This is based on piix.c, but heavily modified.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "hw/hw.h"
#include "hw/pci-host/q35.h"
#include "qapi/visitor.h"

/****************************************************************************
 * Q35 host
 */

static void q35_host_realize(DeviceState *dev, Error **errp)
{
    PCIHostState *pci = PCI_HOST_BRIDGE(dev);
    Q35PCIHost *s = Q35_HOST_DEVICE(dev);
    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);

    sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, &pci->conf_mem);
    sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, 4);

    sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_mem);
    sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, 4);

    pci->bus = pci_bus_new(DEVICE(s), "pcie.0",
                           s->mch.pci_address_space, s->mch.address_space_io,
                           0, TYPE_PCIE_BUS);
    qdev_set_parent_bus(DEVICE(&s->mch), BUS(pci->bus));
    qdev_init_nofail(DEVICE(&s->mch));
}

static const char *q35_host_root_bus_path(PCIHostState *host_bridge,
                                          PCIBus *rootbus)
{
    Q35PCIHost *s = Q35_HOST_DEVICE(host_bridge);

     /* For backwards compat with old device paths */
    if (s->mch.short_root_bus) {
        return "0000";
    }
    return "0000:00";
}

static void q35_host_get_pci_hole_start(Object *obj, Visitor *v,
                                        void *opaque, const char *name,
                                        Error **errp)
{
    Q35PCIHost *s = Q35_HOST_DEVICE(obj);
    uint32_t value = s->mch.pci_info.w32.begin;

    visit_type_uint32(v, &value, name, errp);
}

static void q35_host_get_pci_hole_end(Object *obj, Visitor *v,
                                      void *opaque, const char *name,
                                      Error **errp)
{
    Q35PCIHost *s = Q35_HOST_DEVICE(obj);
    uint32_t value = s->mch.pci_info.w32.end;

    visit_type_uint32(v, &value, name, errp);
}

static void q35_host_get_pci_hole64_start(Object *obj, Visitor *v,
                                          void *opaque, const char *name,
                                          Error **errp)
{
    PCIHostState *h = PCI_HOST_BRIDGE(obj);
    Range w64;

    pci_bus_get_w64_range(h->bus, &w64);

    visit_type_uint64(v, &w64.begin, name, errp);
}

static void q35_host_get_pci_hole64_end(Object *obj, Visitor *v,
                                        void *opaque, const char *name,
                                        Error **errp)
{
    PCIHostState *h = PCI_HOST_BRIDGE(obj);
    Range w64;

    pci_bus_get_w64_range(h->bus, &w64);

    visit_type_uint64(v, &w64.end, name, errp);
}

static void q35_host_get_mmcfg_size(Object *obj, Visitor *v,
                                    void *opaque, const char *name,
                                    Error **errp)
{
    PCIExpressHost *e = PCIE_HOST_BRIDGE(obj);
    uint32_t value = e->size;

    visit_type_uint32(v, &value, name, errp);
}

static Property mch_props[] = {
    DEFINE_PROP_UINT64(PCIE_HOST_MCFG_BASE, Q35PCIHost, parent_obj.base_addr,
                        MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT),
    DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, Q35PCIHost,
                     mch.pci_hole64_size, DEFAULT_PCI_HOLE64_SIZE),
    DEFINE_PROP_UINT32("short_root_bus", Q35PCIHost, mch.short_root_bus, 0),
    DEFINE_PROP_END_OF_LIST(),
};

static void q35_host_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);

    hc->root_bus_path = q35_host_root_bus_path;
    dc->realize = q35_host_realize;
    dc->props = mch_props;
    set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
    dc->fw_name = "pci";
}

static void q35_host_initfn(Object *obj)
{
    Q35PCIHost *s = Q35_HOST_DEVICE(obj);
    PCIHostState *phb = PCI_HOST_BRIDGE(obj);

    memory_region_init_io(&phb->conf_mem, obj, &pci_host_conf_le_ops, phb,
                          "pci-conf-idx", 4);
    memory_region_init_io(&phb->data_mem, obj, &pci_host_data_le_ops, phb,
                          "pci-conf-data", 4);

    object_initialize(&s->mch, sizeof(s->mch), TYPE_MCH_PCI_DEVICE);
    object_property_add_child(OBJECT(s), "mch", OBJECT(&s->mch), NULL);
    qdev_prop_set_uint32(DEVICE(&s->mch), "addr", PCI_DEVFN(0, 0));
    qdev_prop_set_bit(DEVICE(&s->mch), "multifunction", false);

    object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "int",
                        q35_host_get_pci_hole_start,
                        NULL, NULL, NULL, NULL);

    object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_END, "int",
                        q35_host_get_pci_hole_end,
                        NULL, NULL, NULL, NULL);

    object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_START, "int",
                        q35_host_get_pci_hole64_start,
                        NULL, NULL, NULL, NULL);

    object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_END, "int",
                        q35_host_get_pci_hole64_end,
                        NULL, NULL, NULL, NULL);

    object_property_add(obj, PCIE_HOST_MCFG_SIZE, "int",
                        q35_host_get_mmcfg_size,
                        NULL, NULL, NULL, NULL);

    /* Leave enough space for the biggest MCFG BAR */
    /* TODO: this matches current bios behaviour, but
     * it's not a power of two, which means an MTRR
     * can't cover it exactly.
     */
    s->mch.pci_info.w32.begin = MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT +
        MCH_HOST_BRIDGE_PCIEXBAR_MAX;
    s->mch.pci_info.w32.end = IO_APIC_DEFAULT_ADDRESS;
}

static const TypeInfo q35_host_info = {
    .name       = TYPE_Q35_HOST_DEVICE,
    .parent     = TYPE_PCIE_HOST_BRIDGE,
    .instance_size = sizeof(Q35PCIHost),
    .instance_init = q35_host_initfn,
    .class_init = q35_host_class_init,
};

/****************************************************************************
 * MCH D0:F0
 */

/* PCIe MMCFG */
static void mch_update_pciexbar(MCHPCIState *mch)
{
    PCIDevice *pci_dev = PCI_DEVICE(mch);
    BusState *bus = qdev_get_parent_bus(DEVICE(mch));
    PCIExpressHost *pehb = PCIE_HOST_BRIDGE(bus->parent);

    uint64_t pciexbar;
    int enable;
    uint64_t addr;
    uint64_t addr_mask;
    uint32_t length;

    pciexbar = pci_get_quad(pci_dev->config + MCH_HOST_BRIDGE_PCIEXBAR);
    enable = pciexbar & MCH_HOST_BRIDGE_PCIEXBAREN;
    addr_mask = MCH_HOST_BRIDGE_PCIEXBAR_ADMSK;
    switch (pciexbar & MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK) {
    case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M:
        length = 256 * 1024 * 1024;
        break;
    case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M:
        length = 128 * 1024 * 1024;
        addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK |
            MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK;
        break;
    case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M:
        length = 64 * 1024 * 1024;
        addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK;
        break;
    case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD:
    default:
        enable = 0;
        length = 0;
        abort();
        break;
    }
    addr = pciexbar & addr_mask;
    pcie_host_mmcfg_update(pehb, enable, addr, length);
    /* Leave enough space for the MCFG BAR */
    /*
     * TODO: this matches current bios behaviour, but it's not a power of two,
     * which means an MTRR can't cover it exactly.
     */
    if (enable) {
        mch->pci_info.w32.begin = addr + length;
    } else {
        mch->pci_info.w32.begin = MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT;
    }
}

/* PAM */
static void mch_update_pam(MCHPCIState *mch)
{
    PCIDevice *pd = PCI_DEVICE(mch);
    int i;

    memory_region_transaction_begin();
    for (i = 0; i < 13; i++) {
        pam_update(&mch->pam_regions[i], i,
                   pd->config[MCH_HOST_BRIDGE_PAM0 + ((i + 1) / 2)]);
    }
    memory_region_transaction_commit();
}

/* SMRAM */
static void mch_update_smram(MCHPCIState *mch)
{
    PCIDevice *pd = PCI_DEVICE(mch);

    memory_region_transaction_begin();
    memory_region_set_enabled(&mch->smram_region,
                              !(pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_D_OPEN));
    memory_region_set_enabled(&mch->smram,
                              pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_G_SMRAME);
    memory_region_transaction_commit();
}

static void mch_write_config(PCIDevice *d,
                              uint32_t address, uint32_t val, int len)
{
    MCHPCIState *mch = MCH_PCI_DEVICE(d);

    /* XXX: implement SMRAM.D_LOCK */
    pci_default_write_config(d, address, val, len);

    if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PAM0,
                       MCH_HOST_BRIDGE_PAM_SIZE)) {
        mch_update_pam(mch);
    }

    if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PCIEXBAR,
                       MCH_HOST_BRIDGE_PCIEXBAR_SIZE)) {
        mch_update_pciexbar(mch);
    }

    if (ranges_overlap(address, len, MCH_HOST_BRIDGE_SMRAM,
                       MCH_HOST_BRIDGE_SMRAM_SIZE)) {
        mch_update_smram(mch);
    }
}

static void mch_update(MCHPCIState *mch)
{
    mch_update_pciexbar(mch);
    mch_update_pam(mch);
    mch_update_smram(mch);
}

static int mch_post_load(void *opaque, int version_id)
{
    MCHPCIState *mch = opaque;
    mch_update(mch);
    return 0;
}

static const VMStateDescription vmstate_mch = {
    .name = "mch",
    .version_id = 1,
    .minimum_version_id = 1,
    .post_load = mch_post_load,
    .fields = (VMStateField[]) {
        VMSTATE_PCI_DEVICE(parent_obj, MCHPCIState),
        /* Used to be smm_enabled, which was basically always zero because
         * SeaBIOS hardly uses SMM.  SMRAM is now handled by CPU code.
         */
        VMSTATE_UNUSED(1),
        VMSTATE_END_OF_LIST()
    }
};

static void mch_reset(DeviceState *qdev)
{
    PCIDevice *d = PCI_DEVICE(qdev);
    MCHPCIState *mch = MCH_PCI_DEVICE(d);

    pci_set_quad(d->config + MCH_HOST_BRIDGE_PCIEXBAR,
                 MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT);

    d->config[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT;

    mch_update(mch);
}

static AddressSpace *q35_host_dma_iommu(PCIBus *bus, void *opaque, int devfn)
{
    IntelIOMMUState *s = opaque;
    VTDAddressSpace **pvtd_as;
    int bus_num = pci_bus_num(bus);

    assert(0 <= bus_num && bus_num <= VTD_PCI_BUS_MAX);
    assert(0 <= devfn && devfn <= VTD_PCI_DEVFN_MAX);

    pvtd_as = s->address_spaces[bus_num];
    if (!pvtd_as) {
        /* No corresponding free() */
        pvtd_as = g_malloc0(sizeof(VTDAddressSpace *) * VTD_PCI_DEVFN_MAX);
        s->address_spaces[bus_num] = pvtd_as;
    }
    if (!pvtd_as[devfn]) {
        pvtd_as[devfn] = g_malloc0(sizeof(VTDAddressSpace));

        pvtd_as[devfn]->bus_num = (uint8_t)bus_num;
        pvtd_as[devfn]->devfn = (uint8_t)devfn;
        pvtd_as[devfn]->iommu_state = s;
        pvtd_as[devfn]->context_cache_entry.context_cache_gen = 0;
        memory_region_init_iommu(&pvtd_as[devfn]->iommu, OBJECT(s),
                                 &s->iommu_ops, "intel_iommu", UINT64_MAX);
        address_space_init(&pvtd_as[devfn]->as,
                           &pvtd_as[devfn]->iommu, "intel_iommu");
    }
    return &pvtd_as[devfn]->as;
}

static void mch_init_dmar(MCHPCIState *mch)
{
    PCIBus *pci_bus = PCI_BUS(qdev_get_parent_bus(DEVICE(mch)));

    mch->iommu = INTEL_IOMMU_DEVICE(qdev_create(NULL, TYPE_INTEL_IOMMU_DEVICE));
    object_property_add_child(OBJECT(mch), "intel-iommu",
                              OBJECT(mch->iommu), NULL);
    qdev_init_nofail(DEVICE(mch->iommu));
    sysbus_mmio_map(SYS_BUS_DEVICE(mch->iommu), 0, Q35_HOST_BRIDGE_IOMMU_ADDR);

    pci_setup_iommu(pci_bus, q35_host_dma_iommu, mch->iommu);
}

static void mch_realize(PCIDevice *d, Error **errp)
{
    int i;
    MCHPCIState *mch = MCH_PCI_DEVICE(d);

    /* setup pci memory mapping */
    pc_pci_as_mapping_init(OBJECT(mch), mch->system_memory,
                           mch->pci_address_space);

    /* if *disabled* show SMRAM to all CPUs */
    memory_region_init_alias(&mch->smram_region, OBJECT(mch), "smram-region",
                             mch->pci_address_space, 0xa0000, 0x20000);
    memory_region_add_subregion_overlap(mch->system_memory, 0xa0000,
                                        &mch->smram_region, 1);
    memory_region_set_enabled(&mch->smram_region, true);

    /* smram, as seen by SMM CPUs */
    memory_region_init(&mch->smram, OBJECT(mch), "smram", 1ull << 32);
    memory_region_set_enabled(&mch->smram, true);
    memory_region_init_alias(&mch->low_smram, OBJECT(mch), "smram-low",
                             mch->ram_memory, 0xa0000, 0x20000);
    memory_region_set_enabled(&mch->low_smram, true);
    memory_region_add_subregion(&mch->smram, 0xa0000, &mch->low_smram);
    object_property_add_const_link(qdev_get_machine(), "smram",
                                   OBJECT(&mch->smram), &error_abort);

    init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory,
             mch->pci_address_space, &mch->pam_regions[0],
             PAM_BIOS_BASE, PAM_BIOS_SIZE);
    for (i = 0; i < 12; ++i) {
        init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory,
                 mch->pci_address_space, &mch->pam_regions[i+1],
                 PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, PAM_EXPAN_SIZE);
    }
    /* Intel IOMMU (VT-d) */
    if (machine_iommu(current_machine)) {
        mch_init_dmar(mch);
    }
}

uint64_t mch_mcfg_base(void)
{
    bool ambiguous;
    Object *o = object_resolve_path_type("", TYPE_MCH_PCI_DEVICE, &ambiguous);
    if (!o) {
        return 0;
    }
    return MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT;
}

static void mch_class_init(ObjectClass *klass, void *data)
{
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
    DeviceClass *dc = DEVICE_CLASS(klass);

    k->realize = mch_realize;
    k->config_write = mch_write_config;
    dc->reset = mch_reset;
    set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
    dc->desc = "Host bridge";
    dc->vmsd = &vmstate_mch;
    k->vendor_id = PCI_VENDOR_ID_INTEL;
    k->device_id = PCI_DEVICE_ID_INTEL_Q35_MCH;
    k->revision = MCH_HOST_BRIDGE_REVISION_DEFAULT;
    k->class_id = PCI_CLASS_BRIDGE_HOST;
    /*
     * PCI-facing part of the host bridge, not usable without the
     * host-facing part, which can't be device_add'ed, yet.
     */
    dc->cannot_instantiate_with_device_add_yet = true;
}

static const TypeInfo mch_info = {
    .name = TYPE_MCH_PCI_DEVICE,
    .parent = TYPE_PCI_DEVICE,
    .instance_size = sizeof(MCHPCIState),
    .class_init = mch_class_init,
};

static void q35_register(void)
{
    type_register_static(&mch_info);
    type_register_static(&q35_host_info);
}

type_init(q35_register);
Commit	Line	Data
df2d8b3e IY	1	/*
	2	* QEMU MCH/ICH9 PCI Bridge Emulation
	3	*
	4	* Copyright (c) 2006 Fabrice Bellard
	5	* Copyright (c) 2009, 2010, 2011
	6	* Isaku Yamahata <yamahata at valinux co jp>
	7	* VA Linux Systems Japan K.K.
	8	* Copyright (C) 2012 Jason Baron <[email protected]>
	9	*
ef9f7b58	10	* This is based on piix.c, but heavily modified.
df2d8b3e IY	11	*
	12	* Permission is hereby granted, free of charge, to any person obtaining a copy
	13	* of this software and associated documentation files (the "Software"), to deal
	14	* in the Software without restriction, including without limitation the rights
	15	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	16	* copies of the Software, and to permit persons to whom the Software is
	17	* furnished to do so, subject to the following conditions:
	18	*
	19	* The above copyright notice and this permission notice shall be included in
	20	* all copies or substantial portions of the Software.
	21	*
	22	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	23	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	24	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	25	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	26	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	27	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	28	* THE SOFTWARE.
	29	*/
83c9f4ca	30	#include "hw/hw.h"
0d09e41a	31	#include "hw/pci-host/q35.h"
39848901	32	#include "qapi/visitor.h"
df2d8b3e IY	33
	34	/****************************************************************************
	35	* Q35 host
	36	*/
	37
62d92e43	38	static void q35_host_realize(DeviceState dev, Error *errp)
df2d8b3e	39	{
ce88812f HT	40	PCIHostState *pci = PCI_HOST_BRIDGE(dev);
ce88812f HT	41	Q35PCIHost *s = Q35_HOST_DEVICE(dev);
62d92e43	42	SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
df2d8b3e	43
62d92e43 HT	44	sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, &pci->conf_mem);
62d92e43 HT	45	sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, 4);
df2d8b3e	46
62d92e43 HT	47	sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_mem);
62d92e43 HT	48	sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, 4);
df2d8b3e	49
ce88812f HT	50	pci->bus = pci_bus_new(DEVICE(s), "pcie.0",
	51	s->mch.pci_address_space, s->mch.address_space_io,
	52	0, TYPE_PCIE_BUS);
	53	qdev_set_parent_bus(DEVICE(&s->mch), BUS(pci->bus));
df2d8b3e	54	qdev_init_nofail(DEVICE(&s->mch));
df2d8b3e IY	55	}
df2d8b3e IY	56
568f0690 DG	57	static const char q35_host_root_bus_path(PCIHostState host_bridge,
	58	PCIBus *rootbus)
	59	{
04c7d8b8 CR	60	Q35PCIHost *s = Q35_HOST_DEVICE(host_bridge);
	61
	62	/* For backwards compat with old device paths */
	63	if (s->mch.short_root_bus) {
	64	return "0000";
	65	}
	66	return "0000:00";
568f0690 DG	67	}
568f0690 DG	68
39848901 IM	69	static void q35_host_get_pci_hole_start(Object obj, Visitor v,
	70	void opaque, const char name,
	71	Error **errp)
	72	{
	73	Q35PCIHost *s = Q35_HOST_DEVICE(obj);
	74	uint32_t value = s->mch.pci_info.w32.begin;
	75
	76	visit_type_uint32(v, &value, name, errp);
	77	}
	78
	79	static void q35_host_get_pci_hole_end(Object obj, Visitor v,
	80	void opaque, const char name,
	81	Error **errp)
	82	{
	83	Q35PCIHost *s = Q35_HOST_DEVICE(obj);
	84	uint32_t value = s->mch.pci_info.w32.end;
	85
	86	visit_type_uint32(v, &value, name, errp);
	87	}
	88
	89	static void q35_host_get_pci_hole64_start(Object obj, Visitor v,
	90	void opaque, const char name,
	91	Error **errp)
	92	{
8b42d730 MT	93	PCIHostState *h = PCI_HOST_BRIDGE(obj);
	94	Range w64;
	95
	96	pci_bus_get_w64_range(h->bus, &w64);
39848901	97
8b42d730	98	visit_type_uint64(v, &w64.begin, name, errp);
39848901 IM	99	}
	100
	101	static void q35_host_get_pci_hole64_end(Object obj, Visitor v,
	102	void opaque, const char name,
	103	Error **errp)
	104	{
8b42d730 MT	105	PCIHostState *h = PCI_HOST_BRIDGE(obj);
8b42d730 MT	106	Range w64;
39848901	107
8b42d730	108	pci_bus_get_w64_range(h->bus, &w64);
39848901	109
8b42d730	110	visit_type_uint64(v, &w64.end, name, errp);
39848901 IM	111	}
39848901 IM	112
cbcaf79e MT	113	static void q35_host_get_mmcfg_size(Object obj, Visitor v,
	114	void opaque, const char name,
	115	Error **errp)
	116	{
	117	PCIExpressHost *e = PCIE_HOST_BRIDGE(obj);
	118	uint32_t value = e->size;
	119
	120	visit_type_uint32(v, &value, name, errp);
	121	}
	122
df2d8b3e	123	static Property mch_props[] = {
87f65245	124	DEFINE_PROP_UINT64(PCIE_HOST_MCFG_BASE, Q35PCIHost, parent_obj.base_addr,
df2d8b3e	125	MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT),
39848901 IM	126	DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, Q35PCIHost,
39848901 IM	127	mch.pci_hole64_size, DEFAULT_PCI_HOLE64_SIZE),
04c7d8b8	128	DEFINE_PROP_UINT32("short_root_bus", Q35PCIHost, mch.short_root_bus, 0),
df2d8b3e IY	129	DEFINE_PROP_END_OF_LIST(),
	130	};
	131
	132	static void q35_host_class_init(ObjectClass klass, void data)
	133	{
	134	DeviceClass *dc = DEVICE_CLASS(klass);
568f0690	135	PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
df2d8b3e	136
568f0690	137	hc->root_bus_path = q35_host_root_bus_path;
62d92e43	138	dc->realize = q35_host_realize;
df2d8b3e	139	dc->props = mch_props;
125ee0ed	140	set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
68c0e134	141	dc->fw_name = "pci";
df2d8b3e IY	142	}
	143
	144	static void q35_host_initfn(Object *obj)
	145	{
	146	Q35PCIHost *s = Q35_HOST_DEVICE(obj);
62d92e43 HT	147	PCIHostState *phb = PCI_HOST_BRIDGE(obj);
	148
	149	memory_region_init_io(&phb->conf_mem, obj, &pci_host_conf_le_ops, phb,
	150	"pci-conf-idx", 4);
	151	memory_region_init_io(&phb->data_mem, obj, &pci_host_data_le_ops, phb,
	152	"pci-conf-data", 4);
df2d8b3e	153
213f0c4f	154	object_initialize(&s->mch, sizeof(s->mch), TYPE_MCH_PCI_DEVICE);
df2d8b3e IY	155	object_property_add_child(OBJECT(s), "mch", OBJECT(&s->mch), NULL);
	156	qdev_prop_set_uint32(DEVICE(&s->mch), "addr", PCI_DEVFN(0, 0));
	157	qdev_prop_set_bit(DEVICE(&s->mch), "multifunction", false);
39848901 IM	158
	159	object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "int",
	160	q35_host_get_pci_hole_start,
	161	NULL, NULL, NULL, NULL);
	162
	163	object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_END, "int",
	164	q35_host_get_pci_hole_end,
	165	NULL, NULL, NULL, NULL);
	166
	167	object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_START, "int",
	168	q35_host_get_pci_hole64_start,
	169	NULL, NULL, NULL, NULL);
	170
	171	object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_END, "int",
	172	q35_host_get_pci_hole64_end,
	173	NULL, NULL, NULL, NULL);
	174
cbcaf79e MT	175	object_property_add(obj, PCIE_HOST_MCFG_SIZE, "int",
	176	q35_host_get_mmcfg_size,
	177	NULL, NULL, NULL, NULL);
	178
39848901 IM	179	/* Leave enough space for the biggest MCFG BAR */
	180	/* TODO: this matches current bios behaviour, but
	181	* it's not a power of two, which means an MTRR
	182	* can't cover it exactly.
	183	*/
	184	s->mch.pci_info.w32.begin = MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT +
	185	MCH_HOST_BRIDGE_PCIEXBAR_MAX;
	186	s->mch.pci_info.w32.end = IO_APIC_DEFAULT_ADDRESS;
df2d8b3e IY	187	}
	188
	189	static const TypeInfo q35_host_info = {
	190	.name = TYPE_Q35_HOST_DEVICE,
	191	.parent = TYPE_PCIE_HOST_BRIDGE,
	192	.instance_size = sizeof(Q35PCIHost),
	193	.instance_init = q35_host_initfn,
	194	.class_init = q35_host_class_init,
	195	};
	196
	197	/****************************************************************************
	198	* MCH D0:F0
	199	*/
	200
	201	/* PCIe MMCFG */
	202	static void mch_update_pciexbar(MCHPCIState *mch)
	203	{
ce88812f HT	204	PCIDevice *pci_dev = PCI_DEVICE(mch);
	205	BusState *bus = qdev_get_parent_bus(DEVICE(mch));
	206	PCIExpressHost *pehb = PCIE_HOST_BRIDGE(bus->parent);
df2d8b3e IY	207
	208	uint64_t pciexbar;
	209	int enable;
	210	uint64_t addr;
	211	uint64_t addr_mask;
	212	uint32_t length;
	213
	214	pciexbar = pci_get_quad(pci_dev->config + MCH_HOST_BRIDGE_PCIEXBAR);
	215	enable = pciexbar & MCH_HOST_BRIDGE_PCIEXBAREN;
	216	addr_mask = MCH_HOST_BRIDGE_PCIEXBAR_ADMSK;
	217	switch (pciexbar & MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK) {
	218	case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M:
	219	length = 256 * 1024 * 1024;
	220	break;
	221	case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M:
	222	length = 128 * 1024 * 1024;
	223	addr_mask \|= MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK \|
	224	MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK;
	225	break;
	226	case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M:
	227	length = 64 * 1024 * 1024;
	228	addr_mask \|= MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK;
	229	break;
	230	case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD:
	231	default:
	232	enable = 0;
	233	length = 0;
	234	abort();
	235	break;
	236	}
	237	addr = pciexbar & addr_mask;
ce88812f	238	pcie_host_mmcfg_update(pehb, enable, addr, length);
636228a8 MT	239	/* Leave enough space for the MCFG BAR */
	240	/*
	241	* TODO: this matches current bios behaviour, but it's not a power of two,
	242	* which means an MTRR can't cover it exactly.
	243	*/
	244	if (enable) {
	245	mch->pci_info.w32.begin = addr + length;
	246	} else {
	247	mch->pci_info.w32.begin = MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT;
	248	}
df2d8b3e IY	249	}
	250
	251	/* PAM */
	252	static void mch_update_pam(MCHPCIState *mch)
	253	{
ce88812f	254	PCIDevice *pd = PCI_DEVICE(mch);
df2d8b3e IY	255	int i;
	256
	257	memory_region_transaction_begin();
	258	for (i = 0; i < 13; i++) {
	259	pam_update(&mch->pam_regions[i], i,
ce88812f	260	pd->config[MCH_HOST_BRIDGE_PAM0 + ((i + 1) / 2)]);
df2d8b3e IY	261	}
	262	memory_region_transaction_commit();
	263	}
	264
	265	/* SMRAM */
	266	static void mch_update_smram(MCHPCIState *mch)
	267	{
ce88812f HT	268	PCIDevice *pd = PCI_DEVICE(mch);
ce88812f HT	269
df2d8b3e	270	memory_region_transaction_begin();
3de70c08 PB	271	memory_region_set_enabled(&mch->smram_region,
3de70c08 PB	272	!(pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_D_OPEN));
fe6567d5 PB	273	memory_region_set_enabled(&mch->smram,
fe6567d5 PB	274	pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_G_SMRAME);
df2d8b3e IY	275	memory_region_transaction_commit();
	276	}
	277
df2d8b3e IY	278	static void mch_write_config(PCIDevice *d,
	279	uint32_t address, uint32_t val, int len)
	280	{
	281	MCHPCIState *mch = MCH_PCI_DEVICE(d);
	282
	283	/* XXX: implement SMRAM.D_LOCK */
	284	pci_default_write_config(d, address, val, len);
	285
	286	if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PAM0,
	287	MCH_HOST_BRIDGE_PAM_SIZE)) {
	288	mch_update_pam(mch);
	289	}
	290
	291	if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PCIEXBAR,
	292	MCH_HOST_BRIDGE_PCIEXBAR_SIZE)) {
	293	mch_update_pciexbar(mch);
	294	}
	295
263cf436 BZ	296	if (ranges_overlap(address, len, MCH_HOST_BRIDGE_SMRAM,
263cf436 BZ	297	MCH_HOST_BRIDGE_SMRAM_SIZE)) {
df2d8b3e IY	298	mch_update_smram(mch);
	299	}
	300	}
	301
	302	static void mch_update(MCHPCIState *mch)
	303	{
	304	mch_update_pciexbar(mch);
	305	mch_update_pam(mch);
	306	mch_update_smram(mch);
	307	}
	308
	309	static int mch_post_load(void *opaque, int version_id)
	310	{
	311	MCHPCIState *mch = opaque;
	312	mch_update(mch);
	313	return 0;
	314	}
	315
	316	static const VMStateDescription vmstate_mch = {
	317	.name = "mch",
	318	.version_id = 1,
	319	.minimum_version_id = 1,
df2d8b3e	320	.post_load = mch_post_load,
d49805ae	321	.fields = (VMStateField[]) {
ce88812f	322	VMSTATE_PCI_DEVICE(parent_obj, MCHPCIState),
f809c605 PB	323	/* Used to be smm_enabled, which was basically always zero because
	324	* SeaBIOS hardly uses SMM. SMRAM is now handled by CPU code.
	325	*/
	326	VMSTATE_UNUSED(1),
df2d8b3e IY	327	VMSTATE_END_OF_LIST()
	328	}
	329	};
	330
	331	static void mch_reset(DeviceState *qdev)
	332	{
	333	PCIDevice *d = PCI_DEVICE(qdev);
	334	MCHPCIState *mch = MCH_PCI_DEVICE(d);
	335
	336	pci_set_quad(d->config + MCH_HOST_BRIDGE_PCIEXBAR,
	337	MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT);
	338
263cf436	339	d->config[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT;
df2d8b3e IY	340
	341	mch_update(mch);
	342	}
	343
a52a7fdf LT	344	static AddressSpace q35_host_dma_iommu(PCIBus bus, void *opaque, int devfn)
	345	{
	346	IntelIOMMUState *s = opaque;
	347	VTDAddressSpace **pvtd_as;
	348	int bus_num = pci_bus_num(bus);
	349
	350	assert(0 <= bus_num && bus_num <= VTD_PCI_BUS_MAX);
	351	assert(0 <= devfn && devfn <= VTD_PCI_DEVFN_MAX);
	352
	353	pvtd_as = s->address_spaces[bus_num];
	354	if (!pvtd_as) {
	355	/* No corresponding free() */
	356	pvtd_as = g_malloc0(sizeof(VTDAddressSpace ) VTD_PCI_DEVFN_MAX);
	357	s->address_spaces[bus_num] = pvtd_as;
	358	}
	359	if (!pvtd_as[devfn]) {
	360	pvtd_as[devfn] = g_malloc0(sizeof(VTDAddressSpace));
	361
	362	pvtd_as[devfn]->bus_num = (uint8_t)bus_num;
	363	pvtd_as[devfn]->devfn = (uint8_t)devfn;
	364	pvtd_as[devfn]->iommu_state = s;
d92fa2dc	365	pvtd_as[devfn]->context_cache_entry.context_cache_gen = 0;
a52a7fdf LT	366	memory_region_init_iommu(&pvtd_as[devfn]->iommu, OBJECT(s),
	367	&s->iommu_ops, "intel_iommu", UINT64_MAX);
	368	address_space_init(&pvtd_as[devfn]->as,
	369	&pvtd_as[devfn]->iommu, "intel_iommu");
	370	}
	371	return &pvtd_as[devfn]->as;
	372	}
	373
	374	static void mch_init_dmar(MCHPCIState *mch)
	375	{
	376	PCIBus *pci_bus = PCI_BUS(qdev_get_parent_bus(DEVICE(mch)));
	377
	378	mch->iommu = INTEL_IOMMU_DEVICE(qdev_create(NULL, TYPE_INTEL_IOMMU_DEVICE));
	379	object_property_add_child(OBJECT(mch), "intel-iommu",
	380	OBJECT(mch->iommu), NULL);
	381	qdev_init_nofail(DEVICE(mch->iommu));
	382	sysbus_mmio_map(SYS_BUS_DEVICE(mch->iommu), 0, Q35_HOST_BRIDGE_IOMMU_ADDR);
	383
	384	pci_setup_iommu(pci_bus, q35_host_dma_iommu, mch->iommu);
	385	}
	386
9af21dbe	387	static void mch_realize(PCIDevice d, Error *errp)
df2d8b3e IY	388	{
df2d8b3e IY	389	int i;
df2d8b3e	390	MCHPCIState *mch = MCH_PCI_DEVICE(d);
83d08f26 MT	391
	392	/* setup pci memory mapping */
	393	pc_pci_as_mapping_init(OBJECT(mch), mch->system_memory,
	394	mch->pci_address_space);
	395
fe6567d5	396	/* if disabled show SMRAM to all CPUs */
40c5dce9	397	memory_region_init_alias(&mch->smram_region, OBJECT(mch), "smram-region",
df2d8b3e IY	398	mch->pci_address_space, 0xa0000, 0x20000);
	399	memory_region_add_subregion_overlap(mch->system_memory, 0xa0000,
	400	&mch->smram_region, 1);
fe6567d5 PB	401	memory_region_set_enabled(&mch->smram_region, true);
	402
	403	/* smram, as seen by SMM CPUs */
	404	memory_region_init(&mch->smram, OBJECT(mch), "smram", 1ull << 32);
	405	memory_region_set_enabled(&mch->smram, true);
	406	memory_region_init_alias(&mch->low_smram, OBJECT(mch), "smram-low",
f809c605	407	mch->ram_memory, 0xa0000, 0x20000);
fe6567d5 PB	408	memory_region_set_enabled(&mch->low_smram, true);
	409	memory_region_add_subregion(&mch->smram, 0xa0000, &mch->low_smram);
	410	object_property_add_const_link(qdev_get_machine(), "smram",
	411	OBJECT(&mch->smram), &error_abort);
	412
ac40aa15 LT	413	init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory,
	414	mch->pci_address_space, &mch->pam_regions[0],
	415	PAM_BIOS_BASE, PAM_BIOS_SIZE);
df2d8b3e	416	for (i = 0; i < 12; ++i) {
ac40aa15 LT	417	init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory,
	418	mch->pci_address_space, &mch->pam_regions[i+1],
	419	PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, PAM_EXPAN_SIZE);
df2d8b3e	420	}
a52a7fdf	421	/* Intel IOMMU (VT-d) */
8caff636	422	if (machine_iommu(current_machine)) {
a52a7fdf LT	423	mch_init_dmar(mch);
a52a7fdf LT	424	}
df2d8b3e IY	425	}
df2d8b3e IY	426
6f1426ab MT	427	uint64_t mch_mcfg_base(void)
	428	{
	429	bool ambiguous;
	430	Object *o = object_resolve_path_type("", TYPE_MCH_PCI_DEVICE, &ambiguous);
	431	if (!o) {
	432	return 0;
	433	}
	434	return MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT;
	435	}
	436
df2d8b3e IY	437	static void mch_class_init(ObjectClass klass, void data)
	438	{
	439	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
	440	DeviceClass *dc = DEVICE_CLASS(klass);
	441
9af21dbe	442	k->realize = mch_realize;
df2d8b3e IY	443	k->config_write = mch_write_config;
df2d8b3e IY	444	dc->reset = mch_reset;
125ee0ed	445	set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
df2d8b3e IY	446	dc->desc = "Host bridge";
	447	dc->vmsd = &vmstate_mch;
	448	k->vendor_id = PCI_VENDOR_ID_INTEL;
	449	k->device_id = PCI_DEVICE_ID_INTEL_Q35_MCH;
451f7846	450	k->revision = MCH_HOST_BRIDGE_REVISION_DEFAULT;
df2d8b3e	451	k->class_id = PCI_CLASS_BRIDGE_HOST;
08c58f92 MA	452	/*
	453	* PCI-facing part of the host bridge, not usable without the
	454	* host-facing part, which can't be device_add'ed, yet.
	455	*/
	456	dc->cannot_instantiate_with_device_add_yet = true;
df2d8b3e IY	457	}
	458
	459	static const TypeInfo mch_info = {
	460	.name = TYPE_MCH_PCI_DEVICE,
	461	.parent = TYPE_PCI_DEVICE,
	462	.instance_size = sizeof(MCHPCIState),
	463	.class_init = mch_class_init,
	464	};
	465
	466	static void q35_register(void)
	467	{
	468	type_register_static(&mch_info);
	469	type_register_static(&q35_host_info);
	470	}
	471
	472	type_init(q35_register);