[qemu.git] / hw / arm / highbank.c

/*
 * Calxeda Highbank SoC emulation
 *
 * Copyright (c) 2010-2012 Calxeda
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2 or later, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 *
 */

#include "qemu/osdep.h"
#include "qapi/error.h"
#include "hw/sysbus.h"
#include "hw/arm/arm.h"
#include "hw/devices.h"
#include "hw/loader.h"
#include "net/net.h"
#include "sysemu/kvm.h"
#include "sysemu/sysemu.h"
#include "hw/boards.h"
#include "sysemu/block-backend.h"
#include "exec/address-spaces.h"
#include "qemu/error-report.h"
#include "hw/char/pl011.h"

#define SMP_BOOT_ADDR           0x100
#define SMP_BOOT_REG            0x40
#define MPCORE_PERIPHBASE       0xfff10000

#define MVBAR_ADDR              0x200
#define BOARD_SETUP_ADDR        (MVBAR_ADDR + 8 * sizeof(uint32_t))

#define NIRQ_GIC                160

/* Board init.  */

static void hb_write_board_setup(ARMCPU *cpu,
                                 const struct arm_boot_info *info)
{
    arm_write_secure_board_setup_dummy_smc(cpu, info, MVBAR_ADDR);
}

static void hb_write_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
{
    int n;
    uint32_t smpboot[] = {
        0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 - read current core id */
        0xe210000f, /* ands r0, r0, #0x0f */
        0xe3a03040, /* mov r3, #0x40 - jump address is 0x40 + 0x10 * core id */
        0xe0830200, /* add r0, r3, r0, lsl #4 */
        0xe59f2024, /* ldr r2, privbase */
        0xe3a01001, /* mov r1, #1 */
        0xe5821100, /* str r1, [r2, #256] - set GICC_CTLR.Enable */
        0xe3a010ff, /* mov r1, #0xff */
        0xe5821104, /* str r1, [r2, #260] - set GICC_PMR.Priority to 0xff */
        0xf57ff04f, /* dsb */
        0xe320f003, /* wfi */
        0xe5901000, /* ldr     r1, [r0] */
        0xe1110001, /* tst     r1, r1 */
        0x0afffffb, /* beq     <wfi> */
        0xe12fff11, /* bx      r1 */
        MPCORE_PERIPHBASE   /* privbase: MPCore peripheral base address.  */
    };
    for (n = 0; n < ARRAY_SIZE(smpboot); n++) {
        smpboot[n] = tswap32(smpboot[n]);
    }
    rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), SMP_BOOT_ADDR);
}

static void hb_reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
{
    CPUARMState *env = &cpu->env;

    switch (info->nb_cpus) {
    case 4:
        address_space_stl_notdirty(&address_space_memory,
                                   SMP_BOOT_REG + 0x30, 0,
                                   MEMTXATTRS_UNSPECIFIED, NULL);
    case 3:
        address_space_stl_notdirty(&address_space_memory,
                                   SMP_BOOT_REG + 0x20, 0,
                                   MEMTXATTRS_UNSPECIFIED, NULL);
    case 2:
        address_space_stl_notdirty(&address_space_memory,
                                   SMP_BOOT_REG + 0x10, 0,
                                   MEMTXATTRS_UNSPECIFIED, NULL);
        env->regs[15] = SMP_BOOT_ADDR;
        break;
    default:
        break;
    }
}

#define NUM_REGS      0x200
static void hb_regs_write(void *opaque, hwaddr offset,
                          uint64_t value, unsigned size)
{
    uint32_t *regs = opaque;

    if (offset == 0xf00) {
        if (value == 1 || value == 2) {
            qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
        } else if (value == 3) {
            qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
        }
    }

    regs[offset/4] = value;
}

static uint64_t hb_regs_read(void *opaque, hwaddr offset,
                             unsigned size)
{
    uint32_t *regs = opaque;
    uint32_t value = regs[offset/4];

    if ((offset == 0x100) || (offset == 0x108) || (offset == 0x10C)) {
        value |= 0x30000000;
    }

    return value;
}

static const MemoryRegionOps hb_mem_ops = {
    .read = hb_regs_read,
    .write = hb_regs_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

#define TYPE_HIGHBANK_REGISTERS "highbank-regs"
#define HIGHBANK_REGISTERS(obj) \
    OBJECT_CHECK(HighbankRegsState, (obj), TYPE_HIGHBANK_REGISTERS)

typedef struct {
    /*< private >*/
    SysBusDevice parent_obj;
    /*< public >*/

    MemoryRegion iomem;
    uint32_t regs[NUM_REGS];
} HighbankRegsState;

static VMStateDescription vmstate_highbank_regs = {
    .name = "highbank-regs",
    .version_id = 0,
    .minimum_version_id = 0,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32_ARRAY(regs, HighbankRegsState, NUM_REGS),
        VMSTATE_END_OF_LIST(),
    },
};

static void highbank_regs_reset(DeviceState *dev)
{
    HighbankRegsState *s = HIGHBANK_REGISTERS(dev);

    s->regs[0x40] = 0x05F20121;
    s->regs[0x41] = 0x2;
    s->regs[0x42] = 0x05F30121;
    s->regs[0x43] = 0x05F40121;
}

static void highbank_regs_init(Object *obj)
{
    HighbankRegsState *s = HIGHBANK_REGISTERS(obj);
    SysBusDevice *dev = SYS_BUS_DEVICE(obj);

    memory_region_init_io(&s->iomem, obj, &hb_mem_ops, s->regs,
                          "highbank_regs", 0x1000);
    sysbus_init_mmio(dev, &s->iomem);
}

static void highbank_regs_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->desc = "Calxeda Highbank registers";
    dc->vmsd = &vmstate_highbank_regs;
    dc->reset = highbank_regs_reset;
}

static const TypeInfo highbank_regs_info = {
    .name          = TYPE_HIGHBANK_REGISTERS,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(HighbankRegsState),
    .instance_init = highbank_regs_init,
    .class_init    = highbank_regs_class_init,
};

static void highbank_regs_register_types(void)
{
    type_register_static(&highbank_regs_info);
}

type_init(highbank_regs_register_types)

static struct arm_boot_info highbank_binfo;

enum cxmachines {
    CALXEDA_HIGHBANK,
    CALXEDA_MIDWAY,
};

/* ram_size must be set to match the upper bound of memory in the
 * device tree (linux/arch/arm/boot/dts/highbank.dts), which is
 * normally 0xff900000 or -m 4089. When running this board on a
 * 32-bit host, set the reg value of memory to 0xf7ff00000 in the
 * device tree and pass -m 2047 to QEMU.
 */
static void calxeda_init(MachineState *machine, enum cxmachines machine_id)
{
    ram_addr_t ram_size = machine->ram_size;
    const char *cpu_model = machine->cpu_model;
    const char *kernel_filename = machine->kernel_filename;
    const char *kernel_cmdline = machine->kernel_cmdline;
    const char *initrd_filename = machine->initrd_filename;
    DeviceState *dev = NULL;
    SysBusDevice *busdev;
    qemu_irq pic[128];
    int n;
    qemu_irq cpu_irq[4];
    qemu_irq cpu_fiq[4];
    MemoryRegion *sysram;
    MemoryRegion *dram;
    MemoryRegion *sysmem;
    char *sysboot_filename;

    switch (machine_id) {
    case CALXEDA_HIGHBANK:
        cpu_model = "cortex-a9";
        break;
    case CALXEDA_MIDWAY:
        cpu_model = "cortex-a15";
        break;
    }

    for (n = 0; n < smp_cpus; n++) {
        ObjectClass *oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);
        Object *cpuobj;
        ARMCPU *cpu;

        cpuobj = object_new(object_class_get_name(oc));
        cpu = ARM_CPU(cpuobj);

        object_property_set_int(cpuobj, QEMU_PSCI_CONDUIT_SMC,
                                "psci-conduit", &error_abort);

        if (n) {
            /* Secondary CPUs start in PSCI powered-down state */
            object_property_set_bool(cpuobj, true,
                                     "start-powered-off", &error_abort);
        }

        if (object_property_find(cpuobj, "reset-cbar", NULL)) {
            object_property_set_int(cpuobj, MPCORE_PERIPHBASE,
                                    "reset-cbar", &error_abort);
        }
        object_property_set_bool(cpuobj, true, "realized", &error_fatal);
        cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ);
        cpu_fiq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ);
    }

    sysmem = get_system_memory();
    dram = g_new(MemoryRegion, 1);
    memory_region_allocate_system_memory(dram, NULL, "highbank.dram", ram_size);
    /* SDRAM at address zero.  */
    memory_region_add_subregion(sysmem, 0, dram);

    sysram = g_new(MemoryRegion, 1);
    memory_region_init_ram(sysram, NULL, "highbank.sysram", 0x8000,
                           &error_fatal);
    memory_region_add_subregion(sysmem, 0xfff88000, sysram);
    if (bios_name != NULL) {
        sysboot_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
        if (sysboot_filename != NULL) {
            if (load_image_targphys(sysboot_filename, 0xfff88000, 0x8000) < 0) {
                error_report("Unable to load %s", bios_name);
                exit(1);
            }
            g_free(sysboot_filename);
        } else {
            error_report("Unable to find %s", bios_name);
            exit(1);
        }
    }

    switch (machine_id) {
    case CALXEDA_HIGHBANK:
        dev = qdev_create(NULL, "l2x0");
        qdev_init_nofail(dev);
        busdev = SYS_BUS_DEVICE(dev);
        sysbus_mmio_map(busdev, 0, 0xfff12000);

        dev = qdev_create(NULL, "a9mpcore_priv");
        break;
    case CALXEDA_MIDWAY:
        dev = qdev_create(NULL, "a15mpcore_priv");
        break;
    }
    qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
    qdev_prop_set_uint32(dev, "num-irq", NIRQ_GIC);
    qdev_init_nofail(dev);
    busdev = SYS_BUS_DEVICE(dev);
    sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
    for (n = 0; n < smp_cpus; n++) {
        sysbus_connect_irq(busdev, n, cpu_irq[n]);
        sysbus_connect_irq(busdev, n + smp_cpus, cpu_fiq[n]);
    }

    for (n = 0; n < 128; n++) {
        pic[n] = qdev_get_gpio_in(dev, n);
    }

    dev = qdev_create(NULL, "sp804");
    qdev_prop_set_uint32(dev, "freq0", 150000000);
    qdev_prop_set_uint32(dev, "freq1", 150000000);
    qdev_init_nofail(dev);
    busdev = SYS_BUS_DEVICE(dev);
    sysbus_mmio_map(busdev, 0, 0xfff34000);
    sysbus_connect_irq(busdev, 0, pic[18]);
    pl011_create(0xfff36000, pic[20], serial_hds[0]);

    dev = qdev_create(NULL, "highbank-regs");
    qdev_init_nofail(dev);
    busdev = SYS_BUS_DEVICE(dev);
    sysbus_mmio_map(busdev, 0, 0xfff3c000);

    sysbus_create_simple("pl061", 0xfff30000, pic[14]);
    sysbus_create_simple("pl061", 0xfff31000, pic[15]);
    sysbus_create_simple("pl061", 0xfff32000, pic[16]);
    sysbus_create_simple("pl061", 0xfff33000, pic[17]);
    sysbus_create_simple("pl031", 0xfff35000, pic[19]);
    sysbus_create_simple("pl022", 0xfff39000, pic[23]);

    sysbus_create_simple("sysbus-ahci", 0xffe08000, pic[83]);

    if (nd_table[0].used) {
        qemu_check_nic_model(&nd_table[0], "xgmac");
        dev = qdev_create(NULL, "xgmac");
        qdev_set_nic_properties(dev, &nd_table[0]);
        qdev_init_nofail(dev);
        sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff50000);
        sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[77]);
        sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[78]);
        sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[79]);

        qemu_check_nic_model(&nd_table[1], "xgmac");
        dev = qdev_create(NULL, "xgmac");
        qdev_set_nic_properties(dev, &nd_table[1]);
        qdev_init_nofail(dev);
        sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff51000);
        sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[80]);
        sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[81]);
        sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[82]);
    }

    /* TODO create and connect IDE devices for ide_drive_get() */

    highbank_binfo.ram_size = ram_size;
    highbank_binfo.kernel_filename = kernel_filename;
    highbank_binfo.kernel_cmdline = kernel_cmdline;
    highbank_binfo.initrd_filename = initrd_filename;
    /* highbank requires a dtb in order to boot, and the dtb will override
     * the board ID. The following value is ignored, so set it to -1 to be
     * clear that the value is meaningless.
     */
    highbank_binfo.board_id = -1;
    highbank_binfo.nb_cpus = smp_cpus;
    highbank_binfo.loader_start = 0;
    highbank_binfo.write_secondary_boot = hb_write_secondary;
    highbank_binfo.secondary_cpu_reset_hook = hb_reset_secondary;
    if (!kvm_enabled()) {
        highbank_binfo.board_setup_addr = BOARD_SETUP_ADDR;
        highbank_binfo.write_board_setup = hb_write_board_setup;
        highbank_binfo.secure_board_setup = true;
    } else {
        warn_report("cannot load built-in Monitor support "
                    "if KVM is enabled. Some guests (such as Linux) "
                    "may not boot.");
    }

    arm_load_kernel(ARM_CPU(first_cpu), &highbank_binfo);
}

static void highbank_init(MachineState *machine)
{
    calxeda_init(machine, CALXEDA_HIGHBANK);
}

static void midway_init(MachineState *machine)
{
    calxeda_init(machine, CALXEDA_MIDWAY);
}

static void highbank_class_init(ObjectClass *oc, void *data)
{
    MachineClass *mc = MACHINE_CLASS(oc);

    mc->desc = "Calxeda Highbank (ECX-1000)";
    mc->init = highbank_init;
    mc->block_default_type = IF_IDE;
    mc->units_per_default_bus = 1;
    mc->max_cpus = 4;
}

static const TypeInfo highbank_type = {
    .name = MACHINE_TYPE_NAME("highbank"),
    .parent = TYPE_MACHINE,
    .class_init = highbank_class_init,
};

static void midway_class_init(ObjectClass *oc, void *data)
{
    MachineClass *mc = MACHINE_CLASS(oc);

    mc->desc = "Calxeda Midway (ECX-2000)";
    mc->init = midway_init;
    mc->block_default_type = IF_IDE;
    mc->units_per_default_bus = 1;
    mc->max_cpus = 4;
}

static const TypeInfo midway_type = {
    .name = MACHINE_TYPE_NAME("midway"),
    .parent = TYPE_MACHINE,
    .class_init = midway_class_init,
};

static void calxeda_machines_init(void)
{
    type_register_static(&highbank_type);
    type_register_static(&midway_type);
}

type_init(calxeda_machines_init)
Commit	Line	Data
2488514c RH	1	/*
	2	* Calxeda Highbank SoC emulation
	3	*
	4	* Copyright (c) 2010-2012 Calxeda
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms and conditions of the GNU General Public License,
	8	* version 2 or later, as published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope it will be useful, but WITHOUT
	11	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	* more details.
	14	*
	15	* You should have received a copy of the GNU General Public License along with
	16	* this program. If not, see <http://www.gnu.org/licenses/>.
	17	*
	18	*/
	19
12b16722	20	#include "qemu/osdep.h"
da34e65c	21	#include "qapi/error.h"
83c9f4ca	22	#include "hw/sysbus.h"
bd2be150 PM	23	#include "hw/arm/arm.h"
bd2be150 PM	24	#include "hw/devices.h"
83c9f4ca	25	#include "hw/loader.h"
1422e32d	26	#include "net/net.h"
40340e5f	27	#include "sysemu/kvm.h"
9c17d615	28	#include "sysemu/sysemu.h"
83c9f4ca	29	#include "hw/boards.h"
4be74634	30	#include "sysemu/block-backend.h"
022c62cb	31	#include "exec/address-spaces.h"
f282f296	32	#include "qemu/error-report.h"
f0d1d2c1	33	#include "hw/char/pl011.h"
2488514c	34
e2cddeeb PC	35	#define SMP_BOOT_ADDR 0x100
	36	#define SMP_BOOT_REG 0x40
	37	#define MPCORE_PERIPHBASE 0xfff10000
2488514c	38
40340e5f	39	#define MVBAR_ADDR 0x200
716536a9	40	#define BOARD_SETUP_ADDR (MVBAR_ADDR + 8 * sizeof(uint32_t))
40340e5f	41
e2cddeeb	42	#define NIRQ_GIC 160
2488514c RH	43
2488514c RH	44	/* Board init. */
2488514c	45
40340e5f PC	46	static void hb_write_board_setup(ARMCPU *cpu,
	47	const struct arm_boot_info *info)
	48	{
716536a9	49	arm_write_secure_board_setup_dummy_smc(cpu, info, MVBAR_ADDR);
40340e5f PC	50	}
40340e5f PC	51
9543b0cd	52	static void hb_write_secondary(ARMCPU cpu, const struct arm_boot_info info)
2488514c RH	53	{
	54	int n;
	55	uint32_t smpboot[] = {
	56	0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 - read current core id */
	57	0xe210000f, /* ands r0, r0, #0x0f */
	58	0xe3a03040, /* mov r3, #0x40 - jump address is 0x40 + 0x10 * core id */
	59	0xe0830200, /* add r0, r3, r0, lsl #4 */
bf471f79	60	0xe59f2024, /* ldr r2, privbase */
2488514c	61	0xe3a01001, /* mov r1, #1 */
bf471f79 PM	62	0xe5821100, /* str r1, [r2, #256] - set GICC_CTLR.Enable */
	63	0xe3a010ff, /* mov r1, #0xff */
	64	0xe5821104, /* str r1, [r2, #260] - set GICC_PMR.Priority to 0xff */
	65	0xf57ff04f, /* dsb */
2488514c RH	66	0xe320f003, /* wfi */
	67	0xe5901000, /* ldr r1, [r0] */
	68	0xe1110001, /* tst r1, r1 */
	69	0x0afffffb, /* beq <wfi> */
	70	0xe12fff11, /* bx r1 */
e2cddeeb	71	MPCORE_PERIPHBASE /* privbase: MPCore peripheral base address. */
2488514c RH	72	};
	73	for (n = 0; n < ARRAY_SIZE(smpboot); n++) {
	74	smpboot[n] = tswap32(smpboot[n]);
	75	}
	76	rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), SMP_BOOT_ADDR);
	77	}
	78
5d309320	79	static void hb_reset_secondary(ARMCPU cpu, const struct arm_boot_info info)
2488514c	80	{
5d309320 AF	81	CPUARMState *env = &cpu->env;
5d309320 AF	82
2488514c RH	83	switch (info->nb_cpus) {
2488514c RH	84	case 4:
42874d3a PM	85	address_space_stl_notdirty(&address_space_memory,
	86	SMP_BOOT_REG + 0x30, 0,
	87	MEMTXATTRS_UNSPECIFIED, NULL);
2488514c	88	case 3:
42874d3a PM	89	address_space_stl_notdirty(&address_space_memory,
	90	SMP_BOOT_REG + 0x20, 0,
	91	MEMTXATTRS_UNSPECIFIED, NULL);
2488514c	92	case 2:
42874d3a PM	93	address_space_stl_notdirty(&address_space_memory,
	94	SMP_BOOT_REG + 0x10, 0,
	95	MEMTXATTRS_UNSPECIFIED, NULL);
2488514c RH	96	env->regs[15] = SMP_BOOT_ADDR;
	97	break;
	98	default:
	99	break;
	100	}
	101	}
	102
	103	#define NUM_REGS 0x200
a8170e5e	104	static void hb_regs_write(void *opaque, hwaddr offset,
2488514c RH	105	uint64_t value, unsigned size)
	106	{
	107	uint32_t *regs = opaque;
	108
	109	if (offset == 0xf00) {
	110	if (value == 1 \|\| value == 2) {
cf83f140	111	qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
2488514c	112	} else if (value == 3) {
cf83f140	113	qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
2488514c RH	114	}
	115	}
	116
	117	regs[offset/4] = value;
	118	}
	119
a8170e5e	120	static uint64_t hb_regs_read(void *opaque, hwaddr offset,
2488514c RH	121	unsigned size)
	122	{
	123	uint32_t *regs = opaque;
	124	uint32_t value = regs[offset/4];
	125
	126	if ((offset == 0x100) \|\| (offset == 0x108) \|\| (offset == 0x10C)) {
	127	value \|= 0x30000000;
	128	}
	129
	130	return value;
	131	}
	132
	133	static const MemoryRegionOps hb_mem_ops = {
	134	.read = hb_regs_read,
	135	.write = hb_regs_write,
	136	.endianness = DEVICE_NATIVE_ENDIAN,
	137	};
	138
426533fa AF	139	#define TYPE_HIGHBANK_REGISTERS "highbank-regs"
	140	#define HIGHBANK_REGISTERS(obj) \
	141	OBJECT_CHECK(HighbankRegsState, (obj), TYPE_HIGHBANK_REGISTERS)
	142
2488514c	143	typedef struct {
426533fa AF	144	/< private >/
	145	SysBusDevice parent_obj;
	146	/< public >/
	147
112f2ac9	148	MemoryRegion iomem;
2488514c RH	149	uint32_t regs[NUM_REGS];
	150	} HighbankRegsState;
	151
	152	static VMStateDescription vmstate_highbank_regs = {
	153	.name = "highbank-regs",
	154	.version_id = 0,
	155	.minimum_version_id = 0,
2488514c RH	156	.fields = (VMStateField[]) {
	157	VMSTATE_UINT32_ARRAY(regs, HighbankRegsState, NUM_REGS),
	158	VMSTATE_END_OF_LIST(),
	159	},
	160	};
	161
	162	static void highbank_regs_reset(DeviceState *dev)
	163	{
426533fa	164	HighbankRegsState *s = HIGHBANK_REGISTERS(dev);
2488514c RH	165
	166	s->regs[0x40] = 0x05F20121;
	167	s->regs[0x41] = 0x2;
	168	s->regs[0x42] = 0x05F30121;
	169	s->regs[0x43] = 0x05F40121;
	170	}
	171
ff7a27c1	172	static void highbank_regs_init(Object *obj)
2488514c	173	{
ff7a27c1 XZ	174	HighbankRegsState *s = HIGHBANK_REGISTERS(obj);
ff7a27c1 XZ	175	SysBusDevice *dev = SYS_BUS_DEVICE(obj);
2488514c	176
ff7a27c1	177	memory_region_init_io(&s->iomem, obj, &hb_mem_ops, s->regs,
64bde0f3	178	"highbank_regs", 0x1000);
112f2ac9	179	sysbus_init_mmio(dev, &s->iomem);
2488514c RH	180	}
2488514c RH	181
999e12bb AL	182	static void highbank_regs_class_init(ObjectClass klass, void data)
999e12bb AL	183	{
39bffca2	184	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb	185
39bffca2 AL	186	dc->desc = "Calxeda Highbank registers";
	187	dc->vmsd = &vmstate_highbank_regs;
	188	dc->reset = highbank_regs_reset;
999e12bb AL	189	}
999e12bb AL	190
8c43a6f0	191	static const TypeInfo highbank_regs_info = {
426533fa	192	.name = TYPE_HIGHBANK_REGISTERS,
39bffca2 AL	193	.parent = TYPE_SYS_BUS_DEVICE,
39bffca2 AL	194	.instance_size = sizeof(HighbankRegsState),
ff7a27c1	195	.instance_init = highbank_regs_init,
39bffca2	196	.class_init = highbank_regs_class_init,
2488514c RH	197	};
2488514c RH	198
83f7d43a	199	static void highbank_regs_register_types(void)
2488514c	200	{
39bffca2	201	type_register_static(&highbank_regs_info);
2488514c RH	202	}
2488514c RH	203
83f7d43a	204	type_init(highbank_regs_register_types)
2488514c RH	205
	206	static struct arm_boot_info highbank_binfo;
	207
574f66bc AP	208	enum cxmachines {
574f66bc AP	209	CALXEDA_HIGHBANK,
b25a83f0	210	CALXEDA_MIDWAY,
574f66bc AP	211	};
574f66bc AP	212
2488514c RH	213	/* ram_size must be set to match the upper bound of memory in the
	214	* device tree (linux/arch/arm/boot/dts/highbank.dts), which is
	215	* normally 0xff900000 or -m 4089. When running this board on a
	216	* 32-bit host, set the reg value of memory to 0xf7ff00000 in the
	217	* device tree and pass -m 2047 to QEMU.
	218	*/
3ef96221	219	static void calxeda_init(MachineState *machine, enum cxmachines machine_id)
2488514c	220	{
3ef96221 MA	221	ram_addr_t ram_size = machine->ram_size;
	222	const char *cpu_model = machine->cpu_model;
	223	const char *kernel_filename = machine->kernel_filename;
	224	const char *kernel_cmdline = machine->kernel_cmdline;
	225	const char *initrd_filename = machine->initrd_filename;
574f66bc	226	DeviceState *dev = NULL;
2488514c	227	SysBusDevice *busdev;
2488514c RH	228	qemu_irq pic[128];
	229	int n;
	230	qemu_irq cpu_irq[4];
5ae79fe8	231	qemu_irq cpu_fiq[4];
2488514c RH	232	MemoryRegion *sysram;
	233	MemoryRegion *dram;
	234	MemoryRegion *sysmem;
	235	char *sysboot_filename;
	236
dca6eeed PC	237	switch (machine_id) {
	238	case CALXEDA_HIGHBANK:
	239	cpu_model = "cortex-a9";
	240	break;
	241	case CALXEDA_MIDWAY:
	242	cpu_model = "cortex-a15";
	243	break;
2488514c RH	244	}
	245
	246	for (n = 0; n < smp_cpus; n++) {
f282f296	247	ObjectClass *oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);
d097696e	248	Object *cpuobj;
c5fad12f	249	ARMCPU *cpu;
f282f296	250
d097696e PM	251	cpuobj = object_new(object_class_get_name(oc));
d097696e PM	252	cpu = ARM_CPU(cpuobj);
f282f296	253
40340e5f PC	254	object_property_set_int(cpuobj, QEMU_PSCI_CONDUIT_SMC,
	255	"psci-conduit", &error_abort);
	256
	257	if (n) {
	258	/* Secondary CPUs start in PSCI powered-down state */
	259	object_property_set_bool(cpuobj, true,
	260	"start-powered-off", &error_abort);
61e2f352 GB	261	}
61e2f352 GB	262
d097696e PM	263	if (object_property_find(cpuobj, "reset-cbar", NULL)) {
	264	object_property_set_int(cpuobj, MPCORE_PERIPHBASE,
	265	"reset-cbar", &error_abort);
c0f1ead9	266	}
007b0657	267	object_property_set_bool(cpuobj, true, "realized", &error_fatal);
9188dbf7	268	cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ);
5ae79fe8	269	cpu_fiq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ);
2488514c RH	270	}
	271
	272	sysmem = get_system_memory();
	273	dram = g_new(MemoryRegion, 1);
c8623c02	274	memory_region_allocate_system_memory(dram, NULL, "highbank.dram", ram_size);
2488514c RH	275	/* SDRAM at address zero. */
	276	memory_region_add_subregion(sysmem, 0, dram);
	277
	278	sysram = g_new(MemoryRegion, 1);
49946538	279	memory_region_init_ram(sysram, NULL, "highbank.sysram", 0x8000,
f8ed85ac	280	&error_fatal);
2488514c RH	281	memory_region_add_subregion(sysmem, 0xfff88000, sysram);
	282	if (bios_name != NULL) {
	283	sysboot_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
	284	if (sysboot_filename != NULL) {
60ff4e63	285	if (load_image_targphys(sysboot_filename, 0xfff88000, 0x8000) < 0) {
c525436e MA	286	error_report("Unable to load %s", bios_name);
c525436e MA	287	exit(1);
2488514c	288	}
6e05a12f	289	g_free(sysboot_filename);
2488514c	290	} else {
c525436e MA	291	error_report("Unable to find %s", bios_name);
c525436e MA	292	exit(1);
2488514c RH	293	}
	294	}
	295
3ef96221	296	switch (machine_id) {
574f66bc	297	case CALXEDA_HIGHBANK:
b25a83f0 AP	298	dev = qdev_create(NULL, "l2x0");
	299	qdev_init_nofail(dev);
	300	busdev = SYS_BUS_DEVICE(dev);
	301	sysbus_mmio_map(busdev, 0, 0xfff12000);
	302
574f66bc AP	303	dev = qdev_create(NULL, "a9mpcore_priv");
574f66bc AP	304	break;
b25a83f0 AP	305	case CALXEDA_MIDWAY:
	306	dev = qdev_create(NULL, "a15mpcore_priv");
	307	break;
574f66bc	308	}
2488514c RH	309	qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
	310	qdev_prop_set_uint32(dev, "num-irq", NIRQ_GIC);
	311	qdev_init_nofail(dev);
1356b98d	312	busdev = SYS_BUS_DEVICE(dev);
e2cddeeb	313	sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
2488514c RH	314	for (n = 0; n < smp_cpus; n++) {
2488514c RH	315	sysbus_connect_irq(busdev, n, cpu_irq[n]);
5ae79fe8	316	sysbus_connect_irq(busdev, n + smp_cpus, cpu_fiq[n]);
2488514c RH	317	}
	318
	319	for (n = 0; n < 128; n++) {
	320	pic[n] = qdev_get_gpio_in(dev, n);
	321	}
	322
2488514c RH	323	dev = qdev_create(NULL, "sp804");
	324	qdev_prop_set_uint32(dev, "freq0", 150000000);
	325	qdev_prop_set_uint32(dev, "freq1", 150000000);
	326	qdev_init_nofail(dev);
1356b98d	327	busdev = SYS_BUS_DEVICE(dev);
2488514c RH	328	sysbus_mmio_map(busdev, 0, 0xfff34000);
2488514c RH	329	sysbus_connect_irq(busdev, 0, pic[18]);
f0d1d2c1	330	pl011_create(0xfff36000, pic[20], serial_hds[0]);
2488514c RH	331
	332	dev = qdev_create(NULL, "highbank-regs");
	333	qdev_init_nofail(dev);
1356b98d	334	busdev = SYS_BUS_DEVICE(dev);
2488514c RH	335	sysbus_mmio_map(busdev, 0, 0xfff3c000);
	336
	337	sysbus_create_simple("pl061", 0xfff30000, pic[14]);
	338	sysbus_create_simple("pl061", 0xfff31000, pic[15]);
	339	sysbus_create_simple("pl061", 0xfff32000, pic[16]);
	340	sysbus_create_simple("pl061", 0xfff33000, pic[17]);
	341	sysbus_create_simple("pl031", 0xfff35000, pic[19]);
	342	sysbus_create_simple("pl022", 0xfff39000, pic[23]);
	343
	344	sysbus_create_simple("sysbus-ahci", 0xffe08000, pic[83]);
	345
a005d073	346	if (nd_table[0].used) {
2488514c RH	347	qemu_check_nic_model(&nd_table[0], "xgmac");
	348	dev = qdev_create(NULL, "xgmac");
	349	qdev_set_nic_properties(dev, &nd_table[0]);
	350	qdev_init_nofail(dev);
1356b98d AF	351	sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff50000);
	352	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[77]);
	353	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[78]);
	354	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[79]);
2488514c RH	355
	356	qemu_check_nic_model(&nd_table[1], "xgmac");
	357	dev = qdev_create(NULL, "xgmac");
	358	qdev_set_nic_properties(dev, &nd_table[1]);
	359	qdev_init_nofail(dev);
1356b98d AF	360	sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff51000);
	361	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[80]);
	362	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[81]);
	363	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[82]);
2488514c RH	364	}
2488514c RH	365
2a7ae4ee MA	366	/* TODO create and connect IDE devices for ide_drive_get() */
2a7ae4ee MA	367
2488514c RH	368	highbank_binfo.ram_size = ram_size;
	369	highbank_binfo.kernel_filename = kernel_filename;
	370	highbank_binfo.kernel_cmdline = kernel_cmdline;
	371	highbank_binfo.initrd_filename = initrd_filename;
	372	/* highbank requires a dtb in order to boot, and the dtb will override
	373	* the board ID. The following value is ignored, so set it to -1 to be
	374	* clear that the value is meaningless.
	375	*/
	376	highbank_binfo.board_id = -1;
	377	highbank_binfo.nb_cpus = smp_cpus;
	378	highbank_binfo.loader_start = 0;
	379	highbank_binfo.write_secondary_boot = hb_write_secondary;
	380	highbank_binfo.secondary_cpu_reset_hook = hb_reset_secondary;
40340e5f PC	381	if (!kvm_enabled()) {
	382	highbank_binfo.board_setup_addr = BOARD_SETUP_ADDR;
	383	highbank_binfo.write_board_setup = hb_write_board_setup;
	384	highbank_binfo.secure_board_setup = true;
	385	} else {
3dc6f869 AF	386	warn_report("cannot load built-in Monitor support "
	387	"if KVM is enabled. Some guests (such as Linux) "
	388	"may not boot.");
40340e5f PC	389	}
40340e5f PC	390
182735ef	391	arm_load_kernel(ARM_CPU(first_cpu), &highbank_binfo);
2488514c RH	392	}
2488514c RH	393
3ef96221	394	static void highbank_init(MachineState *machine)
574f66bc	395	{
3ef96221	396	calxeda_init(machine, CALXEDA_HIGHBANK);
574f66bc AP	397	}
574f66bc AP	398
3ef96221	399	static void midway_init(MachineState *machine)
b25a83f0	400	{
3ef96221	401	calxeda_init(machine, CALXEDA_MIDWAY);
b25a83f0 AP	402	}
b25a83f0 AP	403
8a661aea	404	static void highbank_class_init(ObjectClass oc, void data)
e264d29d	405	{
8a661aea AF	406	MachineClass *mc = MACHINE_CLASS(oc);
8a661aea AF	407
e264d29d EH	408	mc->desc = "Calxeda Highbank (ECX-1000)";
e264d29d EH	409	mc->init = highbank_init;
2a7ae4ee MA	410	mc->block_default_type = IF_IDE;
2a7ae4ee MA	411	mc->units_per_default_bus = 1;
e264d29d EH	412	mc->max_cpus = 4;
e264d29d EH	413	}
2488514c	414
8a661aea AF	415	static const TypeInfo highbank_type = {
	416	.name = MACHINE_TYPE_NAME("highbank"),
	417	.parent = TYPE_MACHINE,
	418	.class_init = highbank_class_init,
	419	};
b25a83f0	420
8a661aea	421	static void midway_class_init(ObjectClass oc, void data)
2488514c	422	{
8a661aea AF	423	MachineClass *mc = MACHINE_CLASS(oc);
8a661aea AF	424
e264d29d EH	425	mc->desc = "Calxeda Midway (ECX-2000)";
e264d29d EH	426	mc->init = midway_init;
2a7ae4ee MA	427	mc->block_default_type = IF_IDE;
2a7ae4ee MA	428	mc->units_per_default_bus = 1;
e264d29d	429	mc->max_cpus = 4;
2488514c RH	430	}
2488514c RH	431
8a661aea AF	432	static const TypeInfo midway_type = {
	433	.name = MACHINE_TYPE_NAME("midway"),
	434	.parent = TYPE_MACHINE,
	435	.class_init = midway_class_init,
	436	};
	437
	438	static void calxeda_machines_init(void)
	439	{
	440	type_register_static(&highbank_type);
	441	type_register_static(&midway_type);
	442	}
	443
0e6aac87	444	type_init(calxeda_machines_init)