[qemu.git] / user-exec.c

/*
 *  User emulator execution
 *
 *  Copyright (c) 2003-2005 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */
#include "config.h"
#include "cpu.h"
#ifndef CONFIG_TCG_PASS_AREG0
#include "dyngen-exec.h"
#endif
#include "disas.h"
#include "tcg.h"

#undef EAX
#undef ECX
#undef EDX
#undef EBX
#undef ESP
#undef EBP
#undef ESI
#undef EDI
#undef EIP
#include <signal.h>
#ifdef __linux__
#include <sys/ucontext.h>
#endif

//#define DEBUG_SIGNAL

static void exception_action(CPUArchState *env1)
{
#if defined(TARGET_I386)
    raise_exception_err(env1, env1->exception_index, env1->error_code);
#else
    cpu_loop_exit(env1);
#endif
}

/* exit the current TB from a signal handler. The host registers are
   restored in a state compatible with the CPU emulator
 */
void cpu_resume_from_signal(CPUArchState *env1, void *puc)
{
#ifdef __linux__
    struct ucontext *uc = puc;
#elif defined(__OpenBSD__)
    struct sigcontext *uc = puc;
#endif

#ifndef CONFIG_TCG_PASS_AREG0
    env = env1;

    /* XXX: restore cpu registers saved in host registers */
#endif

    if (puc) {
        /* XXX: use siglongjmp ? */
#ifdef __linux__
#ifdef __ia64
        sigprocmask(SIG_SETMASK, (sigset_t *)&uc->uc_sigmask, NULL);
#else
        sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
#endif
#elif defined(__OpenBSD__)
        sigprocmask(SIG_SETMASK, &uc->sc_mask, NULL);
#endif
    }
    env1->exception_index = -1;
    longjmp(env1->jmp_env, 1);
}

/* 'pc' is the host PC at which the exception was raised. 'address' is
   the effective address of the memory exception. 'is_write' is 1 if a
   write caused the exception and otherwise 0'. 'old_set' is the
   signal set which should be restored */
static inline int handle_cpu_signal(uintptr_t pc, unsigned long address,
                                    int is_write, sigset_t *old_set,
                                    void *puc)
{
    TranslationBlock *tb;
    int ret;

#ifndef CONFIG_TCG_PASS_AREG0
    if (cpu_single_env) {
        env = cpu_single_env; /* XXX: find a correct solution for multithread */
    }
#endif
#if defined(DEBUG_SIGNAL)
    qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
                pc, address, is_write, *(unsigned long *)old_set);
#endif
    /* XXX: locking issue */
    if (is_write && h2g_valid(address)
        && page_unprotect(h2g(address), pc, puc)) {
        return 1;
    }

    /* see if it is an MMU fault */
    ret = cpu_handle_mmu_fault(cpu_single_env, address, is_write,
                               MMU_USER_IDX);
    if (ret < 0) {
        return 0; /* not an MMU fault */
    }
    if (ret == 0) {
        return 1; /* the MMU fault was handled without causing real CPU fault */
    }
    /* now we have a real cpu fault */
    tb = tb_find_pc(pc);
    if (tb) {
        /* the PC is inside the translated code. It means that we have
           a virtual CPU fault */
        cpu_restore_state(tb, cpu_single_env, pc);
    }

    /* we restore the process signal mask as the sigreturn should
       do it (XXX: use sigsetjmp) */
    sigprocmask(SIG_SETMASK, old_set, NULL);
    exception_action(cpu_single_env);

    /* never comes here */
    return 1;
}

#if defined(__i386__)

#if defined(__APPLE__)
#include <sys/ucontext.h>

#define EIP_sig(context)  (*((unsigned long *)&(context)->uc_mcontext->ss.eip))
#define TRAP_sig(context)    ((context)->uc_mcontext->es.trapno)
#define ERROR_sig(context)   ((context)->uc_mcontext->es.err)
#define MASK_sig(context)    ((context)->uc_sigmask)
#elif defined(__NetBSD__)
#include <ucontext.h>

#define EIP_sig(context)     ((context)->uc_mcontext.__gregs[_REG_EIP])
#define TRAP_sig(context)    ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
#define ERROR_sig(context)   ((context)->uc_mcontext.__gregs[_REG_ERR])
#define MASK_sig(context)    ((context)->uc_sigmask)
#elif defined(__FreeBSD__) || defined(__DragonFly__)
#include <ucontext.h>

#define EIP_sig(context)  (*((unsigned long *)&(context)->uc_mcontext.mc_eip))
#define TRAP_sig(context)    ((context)->uc_mcontext.mc_trapno)
#define ERROR_sig(context)   ((context)->uc_mcontext.mc_err)
#define MASK_sig(context)    ((context)->uc_sigmask)
#elif defined(__OpenBSD__)
#define EIP_sig(context)     ((context)->sc_eip)
#define TRAP_sig(context)    ((context)->sc_trapno)
#define ERROR_sig(context)   ((context)->sc_err)
#define MASK_sig(context)    ((context)->sc_mask)
#else
#define EIP_sig(context)     ((context)->uc_mcontext.gregs[REG_EIP])
#define TRAP_sig(context)    ((context)->uc_mcontext.gregs[REG_TRAPNO])
#define ERROR_sig(context)   ((context)->uc_mcontext.gregs[REG_ERR])
#define MASK_sig(context)    ((context)->uc_sigmask)
#endif

int cpu_signal_handler(int host_signum, void *pinfo,
                       void *puc)
{
    siginfo_t *info = pinfo;
#if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__)
    ucontext_t *uc = puc;
#elif defined(__OpenBSD__)
    struct sigcontext *uc = puc;
#else
    struct ucontext *uc = puc;
#endif
    unsigned long pc;
    int trapno;

#ifndef REG_EIP
/* for glibc 2.1 */
#define REG_EIP    EIP
#define REG_ERR    ERR
#define REG_TRAPNO TRAPNO
#endif
    pc = EIP_sig(uc);
    trapno = TRAP_sig(uc);
    return handle_cpu_signal(pc, (unsigned long)info->si_addr,
                             trapno == 0xe ?
                             (ERROR_sig(uc) >> 1) & 1 : 0,
                             &MASK_sig(uc), puc);
}

#elif defined(__x86_64__)

#ifdef __NetBSD__
#define PC_sig(context)       _UC_MACHINE_PC(context)
#define TRAP_sig(context)     ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
#define ERROR_sig(context)    ((context)->uc_mcontext.__gregs[_REG_ERR])
#define MASK_sig(context)     ((context)->uc_sigmask)
#elif defined(__OpenBSD__)
#define PC_sig(context)       ((context)->sc_rip)
#define TRAP_sig(context)     ((context)->sc_trapno)
#define ERROR_sig(context)    ((context)->sc_err)
#define MASK_sig(context)     ((context)->sc_mask)
#elif defined(__FreeBSD__) || defined(__DragonFly__)
#include <ucontext.h>

#define PC_sig(context)  (*((unsigned long *)&(context)->uc_mcontext.mc_rip))
#define TRAP_sig(context)     ((context)->uc_mcontext.mc_trapno)
#define ERROR_sig(context)    ((context)->uc_mcontext.mc_err)
#define MASK_sig(context)     ((context)->uc_sigmask)
#else
#define PC_sig(context)       ((context)->uc_mcontext.gregs[REG_RIP])
#define TRAP_sig(context)     ((context)->uc_mcontext.gregs[REG_TRAPNO])
#define ERROR_sig(context)    ((context)->uc_mcontext.gregs[REG_ERR])
#define MASK_sig(context)     ((context)->uc_sigmask)
#endif

int cpu_signal_handler(int host_signum, void *pinfo,
                       void *puc)
{
    siginfo_t *info = pinfo;
    unsigned long pc;
#if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__)
    ucontext_t *uc = puc;
#elif defined(__OpenBSD__)
    struct sigcontext *uc = puc;
#else
    struct ucontext *uc = puc;
#endif

    pc = PC_sig(uc);
    return handle_cpu_signal(pc, (unsigned long)info->si_addr,
                             TRAP_sig(uc) == 0xe ?
                             (ERROR_sig(uc) >> 1) & 1 : 0,
                             &MASK_sig(uc), puc);
}

#elif defined(_ARCH_PPC)

/***********************************************************************
 * signal context platform-specific definitions
 * From Wine
 */
#ifdef linux
/* All Registers access - only for local access */
#define REG_sig(reg_name, context)              \
    ((context)->uc_mcontext.regs->reg_name)
/* Gpr Registers access  */
#define GPR_sig(reg_num, context)              REG_sig(gpr[reg_num], context)
/* Program counter */
#define IAR_sig(context)                       REG_sig(nip, context)
/* Machine State Register (Supervisor) */
#define MSR_sig(context)                       REG_sig(msr, context)
/* Count register */
#define CTR_sig(context)                       REG_sig(ctr, context)
/* User's integer exception register */
#define XER_sig(context)                       REG_sig(xer, context)
/* Link register */
#define LR_sig(context)                        REG_sig(link, context)
/* Condition register */
#define CR_sig(context)                        REG_sig(ccr, context)

/* Float Registers access  */
#define FLOAT_sig(reg_num, context)                                     \
    (((double *)((char *)((context)->uc_mcontext.regs + 48 * 4)))[reg_num])
#define FPSCR_sig(context) \
    (*(int *)((char *)((context)->uc_mcontext.regs + (48 + 32 * 2) * 4)))
/* Exception Registers access */
#define DAR_sig(context)                       REG_sig(dar, context)
#define DSISR_sig(context)                     REG_sig(dsisr, context)
#define TRAP_sig(context)                      REG_sig(trap, context)
#endif /* linux */

#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
#include <ucontext.h>
#define IAR_sig(context)               ((context)->uc_mcontext.mc_srr0)
#define MSR_sig(context)               ((context)->uc_mcontext.mc_srr1)
#define CTR_sig(context)               ((context)->uc_mcontext.mc_ctr)
#define XER_sig(context)               ((context)->uc_mcontext.mc_xer)
#define LR_sig(context)                ((context)->uc_mcontext.mc_lr)
#define CR_sig(context)                ((context)->uc_mcontext.mc_cr)
/* Exception Registers access */
#define DAR_sig(context)               ((context)->uc_mcontext.mc_dar)
#define DSISR_sig(context)             ((context)->uc_mcontext.mc_dsisr)
#define TRAP_sig(context)              ((context)->uc_mcontext.mc_exc)
#endif /* __FreeBSD__|| __FreeBSD_kernel__ */

#ifdef __APPLE__
#include <sys/ucontext.h>
typedef struct ucontext SIGCONTEXT;
/* All Registers access - only for local access */
#define REG_sig(reg_name, context)              \
    ((context)->uc_mcontext->ss.reg_name)
#define FLOATREG_sig(reg_name, context)         \
    ((context)->uc_mcontext->fs.reg_name)
#define EXCEPREG_sig(reg_name, context)         \
    ((context)->uc_mcontext->es.reg_name)
#define VECREG_sig(reg_name, context)           \
    ((context)->uc_mcontext->vs.reg_name)
/* Gpr Registers access */
#define GPR_sig(reg_num, context)              REG_sig(r##reg_num, context)
/* Program counter */
#define IAR_sig(context)                       REG_sig(srr0, context)
/* Machine State Register (Supervisor) */
#define MSR_sig(context)                       REG_sig(srr1, context)
#define CTR_sig(context)                       REG_sig(ctr, context)
/* Link register */
#define XER_sig(context)                       REG_sig(xer, context)
/* User's integer exception register */
#define LR_sig(context)                        REG_sig(lr, context)
/* Condition register */
#define CR_sig(context)                        REG_sig(cr, context)
/* Float Registers access */
#define FLOAT_sig(reg_num, context)             \
    FLOATREG_sig(fpregs[reg_num], context)
#define FPSCR_sig(context)                      \
    ((double)FLOATREG_sig(fpscr, context))
/* Exception Registers access */
/* Fault registers for coredump */
#define DAR_sig(context)                       EXCEPREG_sig(dar, context)
#define DSISR_sig(context)                     EXCEPREG_sig(dsisr, context)
/* number of powerpc exception taken */
#define TRAP_sig(context)                      EXCEPREG_sig(exception, context)
#endif /* __APPLE__ */

int cpu_signal_handler(int host_signum, void *pinfo,
                       void *puc)
{
    siginfo_t *info = pinfo;
#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
    ucontext_t *uc = puc;
#else
    struct ucontext *uc = puc;
#endif
    unsigned long pc;
    int is_write;

    pc = IAR_sig(uc);
    is_write = 0;
#if 0
    /* ppc 4xx case */
    if (DSISR_sig(uc) & 0x00800000) {
        is_write = 1;
    }
#else
    if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000)) {
        is_write = 1;
    }
#endif
    return handle_cpu_signal(pc, (unsigned long)info->si_addr,
                             is_write, &uc->uc_sigmask, puc);
}

#elif defined(__alpha__)

int cpu_signal_handler(int host_signum, void *pinfo,
                           void *puc)
{
    siginfo_t *info = pinfo;
    struct ucontext *uc = puc;
    uint32_t *pc = uc->uc_mcontext.sc_pc;
    uint32_t insn = *pc;
    int is_write = 0;

    /* XXX: need kernel patch to get write flag faster */
    switch (insn >> 26) {
    case 0x0d: /* stw */
    case 0x0e: /* stb */
    case 0x0f: /* stq_u */
    case 0x24: /* stf */
    case 0x25: /* stg */
    case 0x26: /* sts */
    case 0x27: /* stt */
    case 0x2c: /* stl */
    case 0x2d: /* stq */
    case 0x2e: /* stl_c */
    case 0x2f: /* stq_c */
        is_write = 1;
    }

    return handle_cpu_signal(pc, (unsigned long)info->si_addr,
                             is_write, &uc->uc_sigmask, puc);
}
#elif defined(__sparc__)

int cpu_signal_handler(int host_signum, void *pinfo,
                       void *puc)
{
    siginfo_t *info = pinfo;
    int is_write;
    uint32_t insn;
#if !defined(__arch64__) || defined(CONFIG_SOLARIS)
    uint32_t *regs = (uint32_t *)(info + 1);
    void *sigmask = (regs + 20);
    /* XXX: is there a standard glibc define ? */
    unsigned long pc = regs[1];
#else
#ifdef __linux__
    struct sigcontext *sc = puc;
    unsigned long pc = sc->sigc_regs.tpc;
    void *sigmask = (void *)sc->sigc_mask;
#elif defined(__OpenBSD__)
    struct sigcontext *uc = puc;
    unsigned long pc = uc->sc_pc;
    void *sigmask = (void *)(long)uc->sc_mask;
#endif
#endif

    /* XXX: need kernel patch to get write flag faster */
    is_write = 0;
    insn = *(uint32_t *)pc;
    if ((insn >> 30) == 3) {
        switch ((insn >> 19) & 0x3f) {
        case 0x05: /* stb */
        case 0x15: /* stba */
        case 0x06: /* sth */
        case 0x16: /* stha */
        case 0x04: /* st */
        case 0x14: /* sta */
        case 0x07: /* std */
        case 0x17: /* stda */
        case 0x0e: /* stx */
        case 0x1e: /* stxa */
        case 0x24: /* stf */
        case 0x34: /* stfa */
        case 0x27: /* stdf */
        case 0x37: /* stdfa */
        case 0x26: /* stqf */
        case 0x36: /* stqfa */
        case 0x25: /* stfsr */
        case 0x3c: /* casa */
        case 0x3e: /* casxa */
            is_write = 1;
            break;
        }
    }
    return handle_cpu_signal(pc, (unsigned long)info->si_addr,
                             is_write, sigmask, NULL);
}

#elif defined(__arm__)

int cpu_signal_handler(int host_signum, void *pinfo,
                       void *puc)
{
    siginfo_t *info = pinfo;
    struct ucontext *uc = puc;
    unsigned long pc;
    int is_write;

#if (__GLIBC__ < 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3))
    pc = uc->uc_mcontext.gregs[R15];
#else
    pc = uc->uc_mcontext.arm_pc;
#endif
    /* XXX: compute is_write */
    is_write = 0;
    return handle_cpu_signal(pc, (unsigned long)info->si_addr,
                             is_write,
                             &uc->uc_sigmask, puc);
}

#elif defined(__mc68000)

int cpu_signal_handler(int host_signum, void *pinfo,
                       void *puc)
{
    siginfo_t *info = pinfo;
    struct ucontext *uc = puc;
    unsigned long pc;
    int is_write;

    pc = uc->uc_mcontext.gregs[16];
    /* XXX: compute is_write */
    is_write = 0;
    return handle_cpu_signal(pc, (unsigned long)info->si_addr,
                             is_write,
                             &uc->uc_sigmask, puc);
}

#elif defined(__ia64)

#ifndef __ISR_VALID
  /* This ought to be in <bits/siginfo.h>... */
# define __ISR_VALID    1
#endif

int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
{
    siginfo_t *info = pinfo;
    struct ucontext *uc = puc;
    unsigned long ip;
    int is_write = 0;

    ip = uc->uc_mcontext.sc_ip;
    switch (host_signum) {
    case SIGILL:
    case SIGFPE:
    case SIGSEGV:
    case SIGBUS:
    case SIGTRAP:
        if (info->si_code && (info->si_segvflags & __ISR_VALID)) {
            /* ISR.W (write-access) is bit 33:  */
            is_write = (info->si_isr >> 33) & 1;
        }
        break;

    default:
        break;
    }
    return handle_cpu_signal(ip, (unsigned long)info->si_addr,
                             is_write,
                             (sigset_t *)&uc->uc_sigmask, puc);
}

#elif defined(__s390__)

int cpu_signal_handler(int host_signum, void *pinfo,
                       void *puc)
{
    siginfo_t *info = pinfo;
    struct ucontext *uc = puc;
    unsigned long pc;
    uint16_t *pinsn;
    int is_write = 0;

    pc = uc->uc_mcontext.psw.addr;

    /* ??? On linux, the non-rt signal handler has 4 (!) arguments instead
       of the normal 2 arguments.  The 3rd argument contains the "int_code"
       from the hardware which does in fact contain the is_write value.
       The rt signal handler, as far as I can tell, does not give this value
       at all.  Not that we could get to it from here even if it were.  */
    /* ??? This is not even close to complete, since it ignores all
       of the read-modify-write instructions.  */
    pinsn = (uint16_t *)pc;
    switch (pinsn[0] >> 8) {
    case 0x50: /* ST */
    case 0x42: /* STC */
    case 0x40: /* STH */
        is_write = 1;
        break;
    case 0xc4: /* RIL format insns */
        switch (pinsn[0] & 0xf) {
        case 0xf: /* STRL */
        case 0xb: /* STGRL */
        case 0x7: /* STHRL */
            is_write = 1;
        }
        break;
    case 0xe3: /* RXY format insns */
        switch (pinsn[2] & 0xff) {
        case 0x50: /* STY */
        case 0x24: /* STG */
        case 0x72: /* STCY */
        case 0x70: /* STHY */
        case 0x8e: /* STPQ */
        case 0x3f: /* STRVH */
        case 0x3e: /* STRV */
        case 0x2f: /* STRVG */
            is_write = 1;
        }
        break;
    }
    return handle_cpu_signal(pc, (unsigned long)info->si_addr,
                             is_write, &uc->uc_sigmask, puc);
}

#elif defined(__mips__)

int cpu_signal_handler(int host_signum, void *pinfo,
                       void *puc)
{
    siginfo_t *info = pinfo;
    struct ucontext *uc = puc;
    greg_t pc = uc->uc_mcontext.pc;
    int is_write;

    /* XXX: compute is_write */
    is_write = 0;
    return handle_cpu_signal(pc, (unsigned long)info->si_addr,
                             is_write, &uc->uc_sigmask, puc);
}

#elif defined(__hppa__)

int cpu_signal_handler(int host_signum, void *pinfo,
                       void *puc)
{
    siginfo_t *info = pinfo;
    struct ucontext *uc = puc;
    unsigned long pc = uc->uc_mcontext.sc_iaoq[0];
    uint32_t insn = *(uint32_t *)pc;
    int is_write = 0;

    /* XXX: need kernel patch to get write flag faster.  */
    switch (insn >> 26) {
    case 0x1a: /* STW */
    case 0x19: /* STH */
    case 0x18: /* STB */
    case 0x1b: /* STWM */
        is_write = 1;
        break;

    case 0x09: /* CSTWX, FSTWX, FSTWS */
    case 0x0b: /* CSTDX, FSTDX, FSTDS */
        /* Distinguish from coprocessor load ... */
        is_write = (insn >> 9) & 1;
        break;

    case 0x03:
        switch ((insn >> 6) & 15) {
        case 0xa: /* STWS */
        case 0x9: /* STHS */
        case 0x8: /* STBS */
        case 0xe: /* STWAS */
        case 0xc: /* STBYS */
            is_write = 1;
        }
        break;
    }

    return handle_cpu_signal(pc, (unsigned long)info->si_addr,
                             is_write, &uc->uc_sigmask, puc);
}

#else

#error host CPU specific signal handler needed

#endif
Commit	Line	Data
42a623c7 BS	1	/*
	2	* User emulator execution
	3	*
	4	* Copyright (c) 2003-2005 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	18	*/
	19	#include "config.h"
3e457172	20	#include "cpu.h"
1846ec2c	21	#ifndef CONFIG_TCG_PASS_AREG0
3e457172	22	#include "dyngen-exec.h"
1846ec2c	23	#endif
42a623c7 BS	24	#include "disas.h"
	25	#include "tcg.h"
	26
	27	#undef EAX
	28	#undef ECX
	29	#undef EDX
	30	#undef EBX
	31	#undef ESP
	32	#undef EBP
	33	#undef ESI
	34	#undef EDI
	35	#undef EIP
	36	#include <signal.h>
	37	#ifdef __linux__
	38	#include <sys/ucontext.h>
	39	#endif
	40
	41	//#define DEBUG_SIGNAL
	42
9349b4f9	43	static void exception_action(CPUArchState *env1)
1162c041	44	{
42a623c7	45	#if defined(TARGET_I386)
77b2bc2c	46	raise_exception_err(env1, env1->exception_index, env1->error_code);
42a623c7	47	#else
1162c041	48	cpu_loop_exit(env1);
42a623c7	49	#endif
1162c041	50	}
42a623c7 BS	51
	52	/* exit the current TB from a signal handler. The host registers are
	53	restored in a state compatible with the CPU emulator
	54	*/
9349b4f9	55	void cpu_resume_from_signal(CPUArchState env1, void puc)
42a623c7 BS	56	{
	57	#ifdef __linux__
	58	struct ucontext *uc = puc;
	59	#elif defined(__OpenBSD__)
	60	struct sigcontext *uc = puc;
	61	#endif
	62
1846ec2c	63	#ifndef CONFIG_TCG_PASS_AREG0
42a623c7 BS	64	env = env1;
	65
	66	/* XXX: restore cpu registers saved in host registers */
1846ec2c	67	#endif
42a623c7 BS	68
	69	if (puc) {
	70	/* XXX: use siglongjmp ? */
	71	#ifdef __linux__
	72	#ifdef __ia64
	73	sigprocmask(SIG_SETMASK, (sigset_t *)&uc->uc_sigmask, NULL);
	74	#else
	75	sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
	76	#endif
	77	#elif defined(__OpenBSD__)
	78	sigprocmask(SIG_SETMASK, &uc->sc_mask, NULL);
	79	#endif
	80	}
1846ec2c BS	81	env1->exception_index = -1;
1846ec2c BS	82	longjmp(env1->jmp_env, 1);
42a623c7 BS	83	}
	84
	85	/* 'pc' is the host PC at which the exception was raised. 'address' is
	86	the effective address of the memory exception. 'is_write' is 1 if a
	87	write caused the exception and otherwise 0'. 'old_set' is the
	88	signal set which should be restored */
20503968	89	static inline int handle_cpu_signal(uintptr_t pc, unsigned long address,
42a623c7 BS	90	int is_write, sigset_t *old_set,
	91	void *puc)
	92	{
	93	TranslationBlock *tb;
	94	int ret;
	95
1846ec2c	96	#ifndef CONFIG_TCG_PASS_AREG0
42a623c7 BS	97	if (cpu_single_env) {
	98	env = cpu_single_env; /* XXX: find a correct solution for multithread */
	99	}
1846ec2c	100	#endif
42a623c7 BS	101	#if defined(DEBUG_SIGNAL)
	102	qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
	103	pc, address, is_write, (unsigned long )old_set);
	104	#endif
	105	/* XXX: locking issue */
c5954819 PM	106	if (is_write && h2g_valid(address)
c5954819 PM	107	&& page_unprotect(h2g(address), pc, puc)) {
42a623c7 BS	108	return 1;
	109	}
	110
	111	/* see if it is an MMU fault */
1846ec2c BS	112	ret = cpu_handle_mmu_fault(cpu_single_env, address, is_write,
1846ec2c BS	113	MMU_USER_IDX);
42a623c7 BS	114	if (ret < 0) {
	115	return 0; /* not an MMU fault */
	116	}
	117	if (ret == 0) {
	118	return 1; /* the MMU fault was handled without causing real CPU fault */
	119	}
	120	/* now we have a real cpu fault */
	121	tb = tb_find_pc(pc);
	122	if (tb) {
	123	/* the PC is inside the translated code. It means that we have
	124	a virtual CPU fault */
1846ec2c	125	cpu_restore_state(tb, cpu_single_env, pc);
42a623c7 BS	126	}
	127
	128	/* we restore the process signal mask as the sigreturn should
	129	do it (XXX: use sigsetjmp) */
	130	sigprocmask(SIG_SETMASK, old_set, NULL);
1846ec2c	131	exception_action(cpu_single_env);
42a623c7 BS	132
	133	/* never comes here */
	134	return 1;
	135	}
	136
	137	#if defined(__i386__)
	138
	139	#if defined(__APPLE__)
	140	#include <sys/ucontext.h>
	141
	142	#define EIP_sig(context) (((unsigned long )&(context)->uc_mcontext->ss.eip))
	143	#define TRAP_sig(context) ((context)->uc_mcontext->es.trapno)
	144	#define ERROR_sig(context) ((context)->uc_mcontext->es.err)
	145	#define MASK_sig(context) ((context)->uc_sigmask)
	146	#elif defined(__NetBSD__)
	147	#include <ucontext.h>
	148
	149	#define EIP_sig(context) ((context)->uc_mcontext.__gregs[_REG_EIP])
	150	#define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
	151	#define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR])
	152	#define MASK_sig(context) ((context)->uc_sigmask)
	153	#elif defined(__FreeBSD__) \|\| defined(__DragonFly__)
	154	#include <ucontext.h>
	155
	156	#define EIP_sig(context) (((unsigned long )&(context)->uc_mcontext.mc_eip))
	157	#define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno)
	158	#define ERROR_sig(context) ((context)->uc_mcontext.mc_err)
	159	#define MASK_sig(context) ((context)->uc_sigmask)
	160	#elif defined(__OpenBSD__)
	161	#define EIP_sig(context) ((context)->sc_eip)
	162	#define TRAP_sig(context) ((context)->sc_trapno)
	163	#define ERROR_sig(context) ((context)->sc_err)
	164	#define MASK_sig(context) ((context)->sc_mask)
	165	#else
	166	#define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP])
	167	#define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
	168	#define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
	169	#define MASK_sig(context) ((context)->uc_sigmask)
	170	#endif
	171
	172	int cpu_signal_handler(int host_signum, void *pinfo,
	173	void *puc)
	174	{
	175	siginfo_t *info = pinfo;
	176	#if defined(__NetBSD__) \|\| defined(__FreeBSD__) \|\| defined(__DragonFly__)
	177	ucontext_t *uc = puc;
	178	#elif defined(__OpenBSD__)
	179	struct sigcontext *uc = puc;
	180	#else
	181	struct ucontext *uc = puc;
	182	#endif
	183	unsigned long pc;
	184	int trapno;
	185
	186	#ifndef REG_EIP
	187	/* for glibc 2.1 */
	188	#define REG_EIP EIP
	189	#define REG_ERR ERR
	190	#define REG_TRAPNO TRAPNO
	191	#endif
	192	pc = EIP_sig(uc);
	193	trapno = TRAP_sig(uc);
	194	return handle_cpu_signal(pc, (unsigned long)info->si_addr,
	195	trapno == 0xe ?
196	(ERROR_sig(uc) >> 1) & 1 : 0,
197	&MASK_sig(uc), puc);
198	}
199
200	#elif defined(__x86_64__)
201
202	#ifdef __NetBSD__
203	#define PC_sig(context) _UC_MACHINE_PC(context)
204	#define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
205	#define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR])
206	#define MASK_sig(context) ((context)->uc_sigmask)
207	#elif defined(__OpenBSD__)
208	#define PC_sig(context) ((context)->sc_rip)
209	#define TRAP_sig(context) ((context)->sc_trapno)
210	#define ERROR_sig(context) ((context)->sc_err)
211	#define MASK_sig(context) ((context)->sc_mask)
212	#elif defined(__FreeBSD__) \|\| defined(__DragonFly__)
213	#include <ucontext.h>
214
215	#define PC_sig(context) (((unsigned long )&(context)->uc_mcontext.mc_rip))
216	#define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno)
217	#define ERROR_sig(context) ((context)->uc_mcontext.mc_err)
218	#define MASK_sig(context) ((context)->uc_sigmask)
219	#else
220	#define PC_sig(context) ((context)->uc_mcontext.gregs[REG_RIP])
221	#define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
222	#define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
223	#define MASK_sig(context) ((context)->uc_sigmask)
224	#endif
225
226	int cpu_signal_handler(int host_signum, void *pinfo,
227	void *puc)
228	{
229	siginfo_t *info = pinfo;
230	unsigned long pc;
231	#if defined(__NetBSD__) \|\| defined(__FreeBSD__) \|\| defined(__DragonFly__)
232	ucontext_t *uc = puc;
233	#elif defined(__OpenBSD__)
234	struct sigcontext *uc = puc;
235	#else
236	struct ucontext *uc = puc;
237	#endif
238
239	pc = PC_sig(uc);
240	return handle_cpu_signal(pc, (unsigned long)info->si_addr,
241	TRAP_sig(uc) == 0xe ?
242	(ERROR_sig(uc) >> 1) & 1 : 0,
243	&MASK_sig(uc), puc);
244	}
245
246	#elif defined(_ARCH_PPC)
247
248	/***********************************************************************
249	* signal context platform-specific definitions
250	* From Wine
251	*/
252	#ifdef linux
253	/* All Registers access - only for local access */
254	#define REG_sig(reg_name, context) \
255	((context)->uc_mcontext.regs->reg_name)
256	/* Gpr Registers access */
257	#define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
258	/* Program counter */
259	#define IAR_sig(context) REG_sig(nip, context)
260	/* Machine State Register (Supervisor) */
261	#define MSR_sig(context) REG_sig(msr, context)
262	/* Count register */
263	#define CTR_sig(context) REG_sig(ctr, context)
264	/* User's integer exception register */
265	#define XER_sig(context) REG_sig(xer, context)
266	/* Link register */
267	#define LR_sig(context) REG_sig(link, context)
268	/* Condition register */
269	#define CR_sig(context) REG_sig(ccr, context)
270
271	/* Float Registers access */
272	#define FLOAT_sig(reg_num, context) \
273	(((double )((char )((context)->uc_mcontext.regs + 48 * 4)))[reg_num])
274	#define FPSCR_sig(context) \
275	((int )((char )((context)->uc_mcontext.regs + (48 + 32 2) * 4)))
276	/* Exception Registers access */
277	#define DAR_sig(context) REG_sig(dar, context)
278	#define DSISR_sig(context) REG_sig(dsisr, context)
279	#define TRAP_sig(context) REG_sig(trap, context)
280	#endif /* linux */
281
282	#if defined(__FreeBSD__) \|\| defined(__FreeBSD_kernel__)
283	#include <ucontext.h>
284	#define IAR_sig(context) ((context)->uc_mcontext.mc_srr0)
285	#define MSR_sig(context) ((context)->uc_mcontext.mc_srr1)
286	#define CTR_sig(context) ((context)->uc_mcontext.mc_ctr)
287	#define XER_sig(context) ((context)->uc_mcontext.mc_xer)
288	#define LR_sig(context) ((context)->uc_mcontext.mc_lr)
289	#define CR_sig(context) ((context)->uc_mcontext.mc_cr)
290	/* Exception Registers access */
291	#define DAR_sig(context) ((context)->uc_mcontext.mc_dar)
292	#define DSISR_sig(context) ((context)->uc_mcontext.mc_dsisr)
293	#define TRAP_sig(context) ((context)->uc_mcontext.mc_exc)
294	#endif /* __FreeBSD__\|\| __FreeBSD_kernel__ */
295
296	#ifdef __APPLE__
297	#include <sys/ucontext.h>
298	typedef struct ucontext SIGCONTEXT;
299	/* All Registers access - only for local access */
300	#define REG_sig(reg_name, context) \
301	((context)->uc_mcontext->ss.reg_name)
302	#define FLOATREG_sig(reg_name, context) \
303	((context)->uc_mcontext->fs.reg_name)
304	#define EXCEPREG_sig(reg_name, context) \
305	((context)->uc_mcontext->es.reg_name)
306	#define VECREG_sig(reg_name, context) \
307	((context)->uc_mcontext->vs.reg_name)
308	/* Gpr Registers access */
309	#define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
310	/* Program counter */
311	#define IAR_sig(context) REG_sig(srr0, context)
312	/* Machine State Register (Supervisor) */
313	#define MSR_sig(context) REG_sig(srr1, context)
314	#define CTR_sig(context) REG_sig(ctr, context)
315	/* Link register */
316	#define XER_sig(context) REG_sig(xer, context)
317	/* User's integer exception register */
318	#define LR_sig(context) REG_sig(lr, context)
319	/* Condition register */
320	#define CR_sig(context) REG_sig(cr, context)
321	/* Float Registers access */
322	#define FLOAT_sig(reg_num, context) \
323	FLOATREG_sig(fpregs[reg_num], context)
324	#define FPSCR_sig(context) \
325	((double)FLOATREG_sig(fpscr, context))
326	/* Exception Registers access */
327	/* Fault registers for coredump */
328	#define DAR_sig(context) EXCEPREG_sig(dar, context)
329	#define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
330	/* number of powerpc exception taken */
331	#define TRAP_sig(context) EXCEPREG_sig(exception, context)
332	#endif /* __APPLE__ */
333
334	int cpu_signal_handler(int host_signum, void *pinfo,
335	void *puc)
336	{
337	siginfo_t *info = pinfo;
338	#if defined(__FreeBSD__) \|\| defined(__FreeBSD_kernel__)
339	ucontext_t *uc = puc;
340	#else
341	struct ucontext *uc = puc;
342	#endif
343	unsigned long pc;
344	int is_write;
345
346	pc = IAR_sig(uc);
347	is_write = 0;
348	#if 0
349	/* ppc 4xx case */
350	if (DSISR_sig(uc) & 0x00800000) {
351	is_write = 1;
352	}
353	#else
354	if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000)) {
355	is_write = 1;
356	}
357	#endif
358	return handle_cpu_signal(pc, (unsigned long)info->si_addr,
359	is_write, &uc->uc_sigmask, puc);
360	}
361
362	#elif defined(__alpha__)
363
364	int cpu_signal_handler(int host_signum, void *pinfo,
365	void *puc)
366	{
367	siginfo_t *info = pinfo;
368	struct ucontext *uc = puc;
369	uint32_t *pc = uc->uc_mcontext.sc_pc;
370	uint32_t insn = *pc;
371	int is_write = 0;
372
373	/* XXX: need kernel patch to get write flag faster */
374	switch (insn >> 26) {
375	case 0x0d: /* stw */
376	case 0x0e: /* stb */
377	case 0x0f: /* stq_u */
378	case 0x24: /* stf */
379	case 0x25: /* stg */
380	case 0x26: /* sts */
381	case 0x27: /* stt */
382	case 0x2c: /* stl */
383	case 0x2d: /* stq */
384	case 0x2e: /* stl_c */
385	case 0x2f: /* stq_c */
386	is_write = 1;
387	}
388
389	return handle_cpu_signal(pc, (unsigned long)info->si_addr,
390	is_write, &uc->uc_sigmask, puc);
391	}
392	#elif defined(__sparc__)
393
394	int cpu_signal_handler(int host_signum, void *pinfo,
395	void *puc)
396	{
397	siginfo_t *info = pinfo;
398	int is_write;
399	uint32_t insn;
400	#if !defined(__arch64__) \|\| defined(CONFIG_SOLARIS)
401	uint32_t regs = (uint32_t )(info + 1);
402	void *sigmask = (regs + 20);
403	/* XXX: is there a standard glibc define ? */
404	unsigned long pc = regs[1];
405	#else
406	#ifdef __linux__
407	struct sigcontext *sc = puc;
408	unsigned long pc = sc->sigc_regs.tpc;
409	void sigmask = (void )sc->sigc_mask;
410	#elif defined(__OpenBSD__)
411	struct sigcontext *uc = puc;
412	unsigned long pc = uc->sc_pc;
413	void sigmask = (void )(long)uc->sc_mask;
414	#endif
415	#endif
416
417	/* XXX: need kernel patch to get write flag faster */
418	is_write = 0;
419	insn = (uint32_t )pc;
420	if ((insn >> 30) == 3) {
421	switch ((insn >> 19) & 0x3f) {
422	case 0x05: /* stb */
423	case 0x15: /* stba */
424	case 0x06: /* sth */
425	case 0x16: /* stha */
426	case 0x04: /* st */
427	case 0x14: /* sta */
428	case 0x07: /* std */
429	case 0x17: /* stda */
430	case 0x0e: /* stx */
431	case 0x1e: /* stxa */
432	case 0x24: /* stf */
433	case 0x34: /* stfa */
434	case 0x27: /* stdf */
435	case 0x37: /* stdfa */
436	case 0x26: /* stqf */
437	case 0x36: /* stqfa */
438	case 0x25: /* stfsr */
439	case 0x3c: /* casa */
440	case 0x3e: /* casxa */
441	is_write = 1;
442	break;
443	}
444	}
445	return handle_cpu_signal(pc, (unsigned long)info->si_addr,
446	is_write, sigmask, NULL);
447	}
448
449	#elif defined(__arm__)
450
451	int cpu_signal_handler(int host_signum, void *pinfo,
452	void *puc)
453	{
454	siginfo_t *info = pinfo;
455	struct ucontext *uc = puc;
456	unsigned long pc;
457	int is_write;
458
459	#if (__GLIBC__ < 2 \|\| (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3))
460	pc = uc->uc_mcontext.gregs[R15];
461	#else
462	pc = uc->uc_mcontext.arm_pc;
463	#endif
464	/* XXX: compute is_write */
465	is_write = 0;
466	return handle_cpu_signal(pc, (unsigned long)info->si_addr,
467	is_write,
468	&uc->uc_sigmask, puc);
469	}
470
471	#elif defined(__mc68000)
472
473	int cpu_signal_handler(int host_signum, void *pinfo,
474	void *puc)
475	{
476	siginfo_t *info = pinfo;
477	struct ucontext *uc = puc;
478	unsigned long pc;
479	int is_write;
480
481	pc = uc->uc_mcontext.gregs[16];
482	/* XXX: compute is_write */
483	is_write = 0;
484	return handle_cpu_signal(pc, (unsigned long)info->si_addr,
485	is_write,
486	&uc->uc_sigmask, puc);
487	}
488
489	#elif defined(__ia64)
490
491	#ifndef __ISR_VALID
492	/* This ought to be in <bits/siginfo.h>... */
493	# define __ISR_VALID 1
494	#endif
495
496	int cpu_signal_handler(int host_signum, void pinfo, void puc)
497	{
498	siginfo_t *info = pinfo;
499	struct ucontext *uc = puc;
500	unsigned long ip;
501	int is_write = 0;
502
503	ip = uc->uc_mcontext.sc_ip;
504	switch (host_signum) {
505	case SIGILL:
506	case SIGFPE:
507	case SIGSEGV:
508	case SIGBUS:
509	case SIGTRAP:
510	if (info->si_code && (info->si_segvflags & __ISR_VALID)) {
511	/* ISR.W (write-access) is bit 33: */
512	is_write = (info->si_isr >> 33) & 1;
513	}
514	break;
515
516	default:
517	break;
518	}
519	return handle_cpu_signal(ip, (unsigned long)info->si_addr,
520	is_write,
521	(sigset_t *)&uc->uc_sigmask, puc);
522	}
523
524	#elif defined(__s390__)
525
526	int cpu_signal_handler(int host_signum, void *pinfo,
527	void *puc)
528	{
529	siginfo_t *info = pinfo;
530	struct ucontext *uc = puc;
531	unsigned long pc;
532	uint16_t *pinsn;
533	int is_write = 0;
534
535	pc = uc->uc_mcontext.psw.addr;
536
537	/* ??? On linux, the non-rt signal handler has 4 (!) arguments instead
538	of the normal 2 arguments. The 3rd argument contains the "int_code"
539	from the hardware which does in fact contain the is_write value.
540	The rt signal handler, as far as I can tell, does not give this value
541	at all. Not that we could get to it from here even if it were. */
542	/* ??? This is not even close to complete, since it ignores all
543	of the read-modify-write instructions. */
544	pinsn = (uint16_t *)pc;
545	switch (pinsn[0] >> 8) {
546	case 0x50: /* ST */
547	case 0x42: /* STC */
548	case 0x40: /* STH */
549	is_write = 1;
550	break;
551	case 0xc4: /* RIL format insns */
552	switch (pinsn[0] & 0xf) {
553	case 0xf: /* STRL */
554	case 0xb: /* STGRL */
555	case 0x7: /* STHRL */
556	is_write = 1;
557	}
558	break;
559	case 0xe3: /* RXY format insns */
560	switch (pinsn[2] & 0xff) {
561	case 0x50: /* STY */
562	case 0x24: /* STG */
563	case 0x72: /* STCY */
564	case 0x70: /* STHY */
565	case 0x8e: /* STPQ */
566	case 0x3f: /* STRVH */
567	case 0x3e: /* STRV */
568	case 0x2f: /* STRVG */
569	is_write = 1;
570	}
571	break;
572	}
573	return handle_cpu_signal(pc, (unsigned long)info->si_addr,
574	is_write, &uc->uc_sigmask, puc);
575	}
576
577	#elif defined(__mips__)
578
579	int cpu_signal_handler(int host_signum, void *pinfo,
580	void *puc)
581	{
582	siginfo_t *info = pinfo;
583	struct ucontext *uc = puc;
584	greg_t pc = uc->uc_mcontext.pc;
585	int is_write;
586
587	/* XXX: compute is_write */
588	is_write = 0;
589	return handle_cpu_signal(pc, (unsigned long)info->si_addr,
590	is_write, &uc->uc_sigmask, puc);
591	}
592
593	#elif defined(__hppa__)
594
595	int cpu_signal_handler(int host_signum, void *pinfo,
596	void *puc)
597	{
02d2bd5d	598	siginfo_t *info = pinfo;
42a623c7 BS	599	struct ucontext *uc = puc;
	600	unsigned long pc = uc->uc_mcontext.sc_iaoq[0];
	601	uint32_t insn = (uint32_t )pc;
	602	int is_write = 0;
	603
	604	/* XXX: need kernel patch to get write flag faster. */
	605	switch (insn >> 26) {
	606	case 0x1a: /* STW */
	607	case 0x19: /* STH */
	608	case 0x18: /* STB */
	609	case 0x1b: /* STWM */
	610	is_write = 1;
	611	break;
	612
	613	case 0x09: /* CSTWX, FSTWX, FSTWS */
	614	case 0x0b: /* CSTDX, FSTDX, FSTDS */
	615	/* Distinguish from coprocessor load ... */
	616	is_write = (insn >> 9) & 1;
	617	break;
	618
	619	case 0x03:
	620	switch ((insn >> 6) & 15) {
	621	case 0xa: /* STWS */
	622	case 0x9: /* STHS */
	623	case 0x8: /* STBS */
	624	case 0xe: /* STWAS */
	625	case 0xc: /* STBYS */
	626	is_write = 1;
	627	}
	628	break;
	629	}
	630
	631	return handle_cpu_signal(pc, (unsigned long)info->si_addr,
	632	is_write, &uc->uc_sigmask, puc);
	633	}
	634
	635	#else
	636
	637	#error host CPU specific signal handler needed
	638
	639	#endif