[qemu.git] / hw / char / sh_serial.c

/*
 * QEMU SCI/SCIF serial port emulation
 *
 * Copyright (c) 2007 Magnus Damm
 *
 * Based on serial.c - QEMU 16450 UART emulation
 * Copyright (c) 2003-2004 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "qemu/osdep.h"
#include "hw/irq.h"
#include "hw/sh4/sh.h"
#include "chardev/char-fe.h"
#include "qapi/error.h"
#include "qemu/timer.h"
#include "qemu/log.h"
#include "trace.h"

#define SH_SERIAL_FLAG_TEND (1 << 0)
#define SH_SERIAL_FLAG_TDE  (1 << 1)
#define SH_SERIAL_FLAG_RDF  (1 << 2)
#define SH_SERIAL_FLAG_BRK  (1 << 3)
#define SH_SERIAL_FLAG_DR   (1 << 4)

#define SH_RX_FIFO_LENGTH (16)

typedef struct {
    MemoryRegion iomem;
    MemoryRegion iomem_p4;
    MemoryRegion iomem_a7;
    uint8_t smr;
    uint8_t brr;
    uint8_t scr;
    uint8_t dr; /* ftdr / tdr */
    uint8_t sr; /* fsr / ssr */
    uint16_t fcr;
    uint8_t sptr;

    uint8_t rx_fifo[SH_RX_FIFO_LENGTH]; /* frdr / rdr */
    uint8_t rx_cnt;
    uint8_t rx_tail;
    uint8_t rx_head;

    int freq;
    int feat;
    int flags;
    int rtrg;

    CharBackend chr;
    QEMUTimer *fifo_timeout_timer;
    uint64_t etu; /* Elementary Time Unit (ns) */

    qemu_irq eri;
    qemu_irq rxi;
    qemu_irq txi;
    qemu_irq tei;
    qemu_irq bri;
} sh_serial_state;

static void sh_serial_clear_fifo(sh_serial_state *s)
{
    memset(s->rx_fifo, 0, SH_RX_FIFO_LENGTH);
    s->rx_cnt = 0;
    s->rx_head = 0;
    s->rx_tail = 0;
}

static void sh_serial_write(void *opaque, hwaddr offs,
                            uint64_t val, unsigned size)
{
    sh_serial_state *s = opaque;
    unsigned char ch;

    trace_sh_serial_write(size, offs, val);
    switch (offs) {
    case 0x00: /* SMR */
        s->smr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0x7b : 0xff);
        return;
    case 0x04: /* BRR */
        s->brr = val;
        return;
    case 0x08: /* SCR */
        /* TODO : For SH7751, SCIF mask should be 0xfb. */
        s->scr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0xfa : 0xff);
        if (!(val & (1 << 5))) {
            s->flags |= SH_SERIAL_FLAG_TEND;
        }
        if ((s->feat & SH_SERIAL_FEAT_SCIF) && s->txi) {
            qemu_set_irq(s->txi, val & (1 << 7));
        }
        if (!(val & (1 << 6))) {
            qemu_set_irq(s->rxi, 0);
        }
        return;
    case 0x0c: /* FTDR / TDR */
        if (qemu_chr_fe_backend_connected(&s->chr)) {
            ch = val;
            /*
             * XXX this blocks entire thread. Rewrite to use
             * qemu_chr_fe_write and background I/O callbacks
             */
            qemu_chr_fe_write_all(&s->chr, &ch, 1);
        }
        s->dr = val;
        s->flags &= ~SH_SERIAL_FLAG_TDE;
        return;
#if 0
    case 0x14: /* FRDR / RDR */
        ret = 0;
        break;
#endif
    }
    if (s->feat & SH_SERIAL_FEAT_SCIF) {
        switch (offs) {
        case 0x10: /* FSR */
            if (!(val & (1 << 6))) {
                s->flags &= ~SH_SERIAL_FLAG_TEND;
            }
            if (!(val & (1 << 5))) {
                s->flags &= ~SH_SERIAL_FLAG_TDE;
            }
            if (!(val & (1 << 4))) {
                s->flags &= ~SH_SERIAL_FLAG_BRK;
            }
            if (!(val & (1 << 1))) {
                s->flags &= ~SH_SERIAL_FLAG_RDF;
            }
            if (!(val & (1 << 0))) {
                s->flags &= ~SH_SERIAL_FLAG_DR;
            }

            if (!(val & (1 << 1)) || !(val & (1 << 0))) {
                if (s->rxi) {
                    qemu_set_irq(s->rxi, 0);
                }
            }
            return;
        case 0x18: /* FCR */
            s->fcr = val;
            switch ((val >> 6) & 3) {
            case 0:
                s->rtrg = 1;
                break;
            case 1:
                s->rtrg = 4;
                break;
            case 2:
                s->rtrg = 8;
                break;
            case 3:
                s->rtrg = 14;
                break;
            }
            if (val & (1 << 1)) {
                sh_serial_clear_fifo(s);
                s->sr &= ~(1 << 1);
            }

            return;
        case 0x20: /* SPTR */
            s->sptr = val & 0xf3;
            return;
        case 0x24: /* LSR */
            return;
        }
    } else {
        switch (offs) {
#if 0
        case 0x0c:
            ret = s->dr;
            break;
        case 0x10:
            ret = 0;
            break;
#endif
        case 0x1c:
            s->sptr = val & 0x8f;
            return;
        }
    }
    qemu_log_mask(LOG_GUEST_ERROR,
                  "%s: unsupported write to 0x%02" HWADDR_PRIx "\n",
                  __func__, offs);
}

static uint64_t sh_serial_read(void *opaque, hwaddr offs,
                               unsigned size)
{
    sh_serial_state *s = opaque;
    uint32_t ret = UINT32_MAX;

#if 0
    switch (offs) {
    case 0x00:
        ret = s->smr;
        break;
    case 0x04:
        ret = s->brr;
        break;
    case 0x08:
        ret = s->scr;
        break;
    case 0x14:
        ret = 0;
        break;
    }
#endif
    if (s->feat & SH_SERIAL_FEAT_SCIF) {
        switch (offs) {
        case 0x00: /* SMR */
            ret = s->smr;
            break;
        case 0x08: /* SCR */
            ret = s->scr;
            break;
        case 0x10: /* FSR */
            ret = 0;
            if (s->flags & SH_SERIAL_FLAG_TEND) {
                ret |= (1 << 6);
            }
            if (s->flags & SH_SERIAL_FLAG_TDE) {
                ret |= (1 << 5);
            }
            if (s->flags & SH_SERIAL_FLAG_BRK) {
                ret |= (1 << 4);
            }
            if (s->flags & SH_SERIAL_FLAG_RDF) {
                ret |= (1 << 1);
            }
            if (s->flags & SH_SERIAL_FLAG_DR) {
                ret |= (1 << 0);
            }

            if (s->scr & (1 << 5)) {
                s->flags |= SH_SERIAL_FLAG_TDE | SH_SERIAL_FLAG_TEND;
            }

            break;
        case 0x14:
            if (s->rx_cnt > 0) {
                ret = s->rx_fifo[s->rx_tail++];
                s->rx_cnt--;
                if (s->rx_tail == SH_RX_FIFO_LENGTH) {
                    s->rx_tail = 0;
                }
                if (s->rx_cnt < s->rtrg) {
                    s->flags &= ~SH_SERIAL_FLAG_RDF;
                }
            }
            break;
        case 0x18:
            ret = s->fcr;
            break;
        case 0x1c:
            ret = s->rx_cnt;
            break;
        case 0x20:
            ret = s->sptr;
            break;
        case 0x24:
            ret = 0;
            break;
        }
    } else {
        switch (offs) {
#if 0
        case 0x0c:
            ret = s->dr;
            break;
        case 0x10:
            ret = 0;
            break;
        case 0x14:
            ret = s->rx_fifo[0];
            break;
#endif
        case 0x1c:
            ret = s->sptr;
            break;
        }
    }
    trace_sh_serial_read(size, offs, ret);

    if (ret > UINT16_MAX) {
        qemu_log_mask(LOG_GUEST_ERROR,
                      "%s: unsupported read from 0x%02" HWADDR_PRIx "\n",
                      __func__, offs);
        ret = 0;
    }

    return ret;
}

static int sh_serial_can_receive(sh_serial_state *s)
{
    return s->scr & (1 << 4);
}

static void sh_serial_receive_break(sh_serial_state *s)
{
    if (s->feat & SH_SERIAL_FEAT_SCIF) {
        s->sr |= (1 << 4);
    }
}

static int sh_serial_can_receive1(void *opaque)
{
    sh_serial_state *s = opaque;
    return sh_serial_can_receive(s);
}

static void sh_serial_timeout_int(void *opaque)
{
    sh_serial_state *s = opaque;

    s->flags |= SH_SERIAL_FLAG_RDF;
    if (s->scr & (1 << 6) && s->rxi) {
        qemu_set_irq(s->rxi, 1);
    }
}

static void sh_serial_receive1(void *opaque, const uint8_t *buf, int size)
{
    sh_serial_state *s = opaque;

    if (s->feat & SH_SERIAL_FEAT_SCIF) {
        int i;
        for (i = 0; i < size; i++) {
            if (s->rx_cnt < SH_RX_FIFO_LENGTH) {
                s->rx_fifo[s->rx_head++] = buf[i];
                if (s->rx_head == SH_RX_FIFO_LENGTH) {
                    s->rx_head = 0;
                }
                s->rx_cnt++;
                if (s->rx_cnt >= s->rtrg) {
                    s->flags |= SH_SERIAL_FLAG_RDF;
                    if (s->scr & (1 << 6) && s->rxi) {
                        timer_del(s->fifo_timeout_timer);
                        qemu_set_irq(s->rxi, 1);
                    }
                } else {
                    timer_mod(s->fifo_timeout_timer,
                        qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 15 * s->etu);
                }
            }
        }
    } else {
        s->rx_fifo[0] = buf[0];
    }
}

static void sh_serial_event(void *opaque, QEMUChrEvent event)
{
    sh_serial_state *s = opaque;
    if (event == CHR_EVENT_BREAK) {
        sh_serial_receive_break(s);
    }
}

static const MemoryRegionOps sh_serial_ops = {
    .read = sh_serial_read,
    .write = sh_serial_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

void sh_serial_init(MemoryRegion *sysmem,
                    hwaddr base, int feat,
                    uint32_t freq, Chardev *chr,
                    qemu_irq eri_source,
                    qemu_irq rxi_source,
                    qemu_irq txi_source,
                    qemu_irq tei_source,
                    qemu_irq bri_source)
{
    sh_serial_state *s;

    s = g_malloc0(sizeof(sh_serial_state));

    s->feat = feat;
    s->flags = SH_SERIAL_FLAG_TEND | SH_SERIAL_FLAG_TDE;
    s->rtrg = 1;

    s->smr = 0;
    s->brr = 0xff;
    s->scr = 1 << 5; /* pretend that TX is enabled so early printk works */
    s->sptr = 0;

    if (feat & SH_SERIAL_FEAT_SCIF) {
        s->fcr = 0;
    } else {
        s->dr = 0xff;
    }

    sh_serial_clear_fifo(s);

    memory_region_init_io(&s->iomem, NULL, &sh_serial_ops, s,
                          "serial", 0x100000000ULL);

    memory_region_init_alias(&s->iomem_p4, NULL, "serial-p4", &s->iomem,
                             0, 0x28);
    memory_region_add_subregion(sysmem, P4ADDR(base), &s->iomem_p4);

    memory_region_init_alias(&s->iomem_a7, NULL, "serial-a7", &s->iomem,
                             0, 0x28);
    memory_region_add_subregion(sysmem, A7ADDR(base), &s->iomem_a7);

    if (chr) {
        qemu_chr_fe_init(&s->chr, chr, &error_abort);
        qemu_chr_fe_set_handlers(&s->chr, sh_serial_can_receive1,
                                 sh_serial_receive1,
                                 sh_serial_event, NULL, s, NULL, true);
    }

    s->fifo_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
                                         sh_serial_timeout_int, s);
    s->etu = NANOSECONDS_PER_SECOND / 9600;
    s->eri = eri_source;
    s->rxi = rxi_source;
    s->txi = txi_source;
    s->tei = tei_source;
    s->bri = bri_source;
}
Commit	Line	Data
2f062c72 TS	1	/*
	2	* QEMU SCI/SCIF serial port emulation
	3	*
	4	* Copyright (c) 2007 Magnus Damm
	5	*
	6	* Based on serial.c - QEMU 16450 UART emulation
	7	* Copyright (c) 2003-2004 Fabrice Bellard
	8	*
	9	* Permission is hereby granted, free of charge, to any person obtaining a copy
	10	* of this software and associated documentation files (the "Software"), to deal
	11	* in the Software without restriction, including without limitation the rights
	12	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	13	* copies of the Software, and to permit persons to whom the Software is
	14	* furnished to do so, subject to the following conditions:
	15	*
	16	* The above copyright notice and this permission notice shall be included in
	17	* all copies or substantial portions of the Software.
	18	*
	19	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	20	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	21	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	22	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	23	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	24	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	25	* THE SOFTWARE.
	26	*/
64552b6b	27
0430891c	28	#include "qemu/osdep.h"
64552b6b	29	#include "hw/irq.h"
0d09e41a	30	#include "hw/sh4/sh.h"
4d43a603	31	#include "chardev/char-fe.h"
32a6ebec	32	#include "qapi/error.h"
71bb4ce1	33	#include "qemu/timer.h"
3cf7ce43	34	#include "qemu/log.h"
ad52cfc1	35	#include "trace.h"
2f062c72 TS	36
	37	#define SH_SERIAL_FLAG_TEND (1 << 0)
	38	#define SH_SERIAL_FLAG_TDE (1 << 1)
	39	#define SH_SERIAL_FLAG_RDF (1 << 2)
	40	#define SH_SERIAL_FLAG_BRK (1 << 3)
	41	#define SH_SERIAL_FLAG_DR (1 << 4)
	42
63242a00 AJ	43	#define SH_RX_FIFO_LENGTH (16)
63242a00 AJ	44
2f062c72	45	typedef struct {
9a9d0b81 BC	46	MemoryRegion iomem;
	47	MemoryRegion iomem_p4;
	48	MemoryRegion iomem_a7;
2f062c72 TS	49	uint8_t smr;
	50	uint8_t brr;
	51	uint8_t scr;
	52	uint8_t dr; /* ftdr / tdr */
	53	uint8_t sr; /* fsr / ssr */
	54	uint16_t fcr;
	55	uint8_t sptr;
	56
63242a00	57	uint8_t rx_fifo[SH_RX_FIFO_LENGTH]; /* frdr / rdr */
2f062c72	58	uint8_t rx_cnt;
63242a00 AJ	59	uint8_t rx_tail;
63242a00 AJ	60	uint8_t rx_head;
2f062c72	61
2f062c72 TS	62	int freq;
	63	int feat;
	64	int flags;
63242a00	65	int rtrg;
2f062c72	66
32a6ebec	67	CharBackend chr;
71bb4ce1 GU	68	QEMUTimer *fifo_timeout_timer;
71bb4ce1 GU	69	uint64_t etu; /* Elementary Time Unit (ns) */
bf5b7423	70
4e7ed2d1 AJ	71	qemu_irq eri;
	72	qemu_irq rxi;
	73	qemu_irq txi;
	74	qemu_irq tei;
	75	qemu_irq bri;
2f062c72 TS	76	} sh_serial_state;
2f062c72 TS	77
f94bff13	78	static void sh_serial_clear_fifo(sh_serial_state *s)
63242a00 AJ	79	{
	80	memset(s->rx_fifo, 0, SH_RX_FIFO_LENGTH);
	81	s->rx_cnt = 0;
	82	s->rx_head = 0;
	83	s->rx_tail = 0;
	84	}
	85
a8170e5e	86	static void sh_serial_write(void *opaque, hwaddr offs,
9a9d0b81	87	uint64_t val, unsigned size)
2f062c72 TS	88	{
	89	sh_serial_state *s = opaque;
	90	unsigned char ch;
	91
ad52cfc1	92	trace_sh_serial_write(size, offs, val);
f94bff13	93	switch (offs) {
2f062c72 TS	94	case 0x00: /* SMR */
	95	s->smr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0x7b : 0xff);
	96	return;
	97	case 0x04: /* BRR */
	98	s->brr = val;
7d37435b	99	return;
2f062c72	100	case 0x08: /* SCR */
63242a00	101	/* TODO : For SH7751, SCIF mask should be 0xfb. */
bf5b7423	102	s->scr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0xfa : 0xff);
ac3c9e74	103	if (!(val & (1 << 5))) {
2f062c72	104	s->flags \|= SH_SERIAL_FLAG_TEND;
ac3c9e74	105	}
bf5b7423	106	if ((s->feat & SH_SERIAL_FEAT_SCIF) && s->txi) {
7d37435b	107	qemu_set_irq(s->txi, val & (1 << 7));
bf5b7423	108	}
4e7ed2d1	109	if (!(val & (1 << 6))) {
7d37435b	110	qemu_set_irq(s->rxi, 0);
63242a00	111	}
2f062c72 TS	112	return;
2f062c72 TS	113	case 0x0c: /* FTDR / TDR */
30650701	114	if (qemu_chr_fe_backend_connected(&s->chr)) {
2f062c72	115	ch = val;
22138965 BZ	116	/*
	117	* XXX this blocks entire thread. Rewrite to use
	118	* qemu_chr_fe_write and background I/O callbacks
	119	*/
5345fdb4	120	qemu_chr_fe_write_all(&s->chr, &ch, 1);
7d37435b PB	121	}
	122	s->dr = val;
	123	s->flags &= ~SH_SERIAL_FLAG_TDE;
2f062c72 TS	124	return;
	125	#if 0
	126	case 0x14: /* FRDR / RDR */
	127	ret = 0;
	128	break;
	129	#endif
	130	}
	131	if (s->feat & SH_SERIAL_FEAT_SCIF) {
f94bff13	132	switch (offs) {
2f062c72	133	case 0x10: /* FSR */
ac3c9e74	134	if (!(val & (1 << 6))) {
2f062c72	135	s->flags &= ~SH_SERIAL_FLAG_TEND;
ac3c9e74 BZ	136	}
ac3c9e74 BZ	137	if (!(val & (1 << 5))) {
2f062c72	138	s->flags &= ~SH_SERIAL_FLAG_TDE;
ac3c9e74 BZ	139	}
ac3c9e74 BZ	140	if (!(val & (1 << 4))) {
2f062c72	141	s->flags &= ~SH_SERIAL_FLAG_BRK;
ac3c9e74 BZ	142	}
ac3c9e74 BZ	143	if (!(val & (1 << 1))) {
2f062c72	144	s->flags &= ~SH_SERIAL_FLAG_RDF;
ac3c9e74 BZ	145	}
ac3c9e74 BZ	146	if (!(val & (1 << 0))) {
2f062c72	147	s->flags &= ~SH_SERIAL_FLAG_DR;
ac3c9e74	148	}
63242a00 AJ	149
63242a00 AJ	150	if (!(val & (1 << 1)) \|\| !(val & (1 << 0))) {
4e7ed2d1 AJ	151	if (s->rxi) {
4e7ed2d1 AJ	152	qemu_set_irq(s->rxi, 0);
63242a00 AJ	153	}
63242a00 AJ	154	}
2f062c72 TS	155	return;
	156	case 0x18: /* FCR */
	157	s->fcr = val;
63242a00 AJ	158	switch ((val >> 6) & 3) {
	159	case 0:
	160	s->rtrg = 1;
	161	break;
	162	case 1:
	163	s->rtrg = 4;
	164	break;
	165	case 2:
	166	s->rtrg = 8;
	167	break;
	168	case 3:
	169	s->rtrg = 14;
	170	break;
	171	}
	172	if (val & (1 << 1)) {
	173	sh_serial_clear_fifo(s);
	174	s->sr &= ~(1 << 1);
	175	}
	176
2f062c72 TS	177	return;
2f062c72 TS	178	case 0x20: /* SPTR */
63242a00	179	s->sptr = val & 0xf3;
2f062c72 TS	180	return;
	181	case 0x24: /* LSR */
	182	return;
	183	}
f94bff13 BZ	184	} else {
f94bff13 BZ	185	switch (offs) {
d1f193b0	186	#if 0
2f062c72 TS	187	case 0x0c:
	188	ret = s->dr;
	189	break;
	190	case 0x10:
	191	ret = 0;
	192	break;
d1f193b0	193	#endif
2f062c72	194	case 0x1c:
d1f193b0 AJ	195	s->sptr = val & 0x8f;
d1f193b0 AJ	196	return;
2f062c72	197	}
2f062c72	198	}
3cf7ce43 BZ	199	qemu_log_mask(LOG_GUEST_ERROR,
	200	"%s: unsupported write to 0x%02" HWADDR_PRIx "\n",
	201	__func__, offs);
2f062c72 TS	202	}
2f062c72 TS	203
a8170e5e	204	static uint64_t sh_serial_read(void *opaque, hwaddr offs,
9a9d0b81	205	unsigned size)
2f062c72 TS	206	{
2f062c72 TS	207	sh_serial_state *s = opaque;
3cf7ce43	208	uint32_t ret = UINT32_MAX;
2f062c72 TS	209
2f062c72 TS	210	#if 0
f94bff13	211	switch (offs) {
2f062c72 TS	212	case 0x00:
	213	ret = s->smr;
	214	break;
	215	case 0x04:
	216	ret = s->brr;
7d37435b	217	break;
2f062c72 TS	218	case 0x08:
	219	ret = s->scr;
	220	break;
	221	case 0x14:
	222	ret = 0;
	223	break;
	224	}
	225	#endif
	226	if (s->feat & SH_SERIAL_FEAT_SCIF) {
f94bff13	227	switch (offs) {
bf5b7423 AJ	228	case 0x00: /* SMR */
	229	ret = s->smr;
	230	break;
	231	case 0x08: /* SCR */
	232	ret = s->scr;
	233	break;
2f062c72 TS	234	case 0x10: /* FSR */
2f062c72 TS	235	ret = 0;
ac3c9e74	236	if (s->flags & SH_SERIAL_FLAG_TEND) {
2f062c72	237	ret \|= (1 << 6);
ac3c9e74 BZ	238	}
ac3c9e74 BZ	239	if (s->flags & SH_SERIAL_FLAG_TDE) {
2f062c72	240	ret \|= (1 << 5);
ac3c9e74 BZ	241	}
ac3c9e74 BZ	242	if (s->flags & SH_SERIAL_FLAG_BRK) {
2f062c72	243	ret \|= (1 << 4);
ac3c9e74 BZ	244	}
ac3c9e74 BZ	245	if (s->flags & SH_SERIAL_FLAG_RDF) {
2f062c72	246	ret \|= (1 << 1);
ac3c9e74 BZ	247	}
ac3c9e74 BZ	248	if (s->flags & SH_SERIAL_FLAG_DR) {
2f062c72	249	ret \|= (1 << 0);
ac3c9e74	250	}
2f062c72	251
ac3c9e74	252	if (s->scr & (1 << 5)) {
2f062c72	253	s->flags \|= SH_SERIAL_FLAG_TDE \| SH_SERIAL_FLAG_TEND;
ac3c9e74	254	}
2f062c72	255
63242a00 AJ	256	break;
	257	case 0x14:
	258	if (s->rx_cnt > 0) {
	259	ret = s->rx_fifo[s->rx_tail++];
	260	s->rx_cnt--;
ac3c9e74	261	if (s->rx_tail == SH_RX_FIFO_LENGTH) {
63242a00	262	s->rx_tail = 0;
ac3c9e74 BZ	263	}
ac3c9e74 BZ	264	if (s->rx_cnt < s->rtrg) {
63242a00	265	s->flags &= ~SH_SERIAL_FLAG_RDF;
ac3c9e74	266	}
63242a00	267	}
2f062c72	268	break;
2f062c72 TS	269	case 0x18:
	270	ret = s->fcr;
	271	break;
2f062c72 TS	272	case 0x1c:
	273	ret = s->rx_cnt;
	274	break;
	275	case 0x20:
	276	ret = s->sptr;
	277	break;
	278	case 0x24:
	279	ret = 0;
	280	break;
	281	}
f94bff13 BZ	282	} else {
f94bff13 BZ	283	switch (offs) {
d1f193b0	284	#if 0
2f062c72 TS	285	case 0x0c:
	286	ret = s->dr;
	287	break;
	288	case 0x10:
	289	ret = 0;
	290	break;
63242a00 AJ	291	case 0x14:
	292	ret = s->rx_fifo[0];
	293	break;
d1f193b0	294	#endif
2f062c72 TS	295	case 0x1c:
	296	ret = s->sptr;
	297	break;
	298	}
2f062c72	299	}
ad52cfc1	300	trace_sh_serial_read(size, offs, ret);
2f062c72	301
3cf7ce43 BZ	302	if (ret > UINT16_MAX) {
	303	qemu_log_mask(LOG_GUEST_ERROR,
	304	"%s: unsupported read from 0x%02" HWADDR_PRIx "\n",
	305	__func__, offs);
	306	ret = 0;
2f062c72 TS	307	}
	308
	309	return ret;
	310	}
	311
	312	static int sh_serial_can_receive(sh_serial_state *s)
	313	{
63242a00	314	return s->scr & (1 << 4);
2f062c72 TS	315	}
2f062c72 TS	316
2f062c72 TS	317	static void sh_serial_receive_break(sh_serial_state *s)
2f062c72 TS	318	{
ac3c9e74	319	if (s->feat & SH_SERIAL_FEAT_SCIF) {
63242a00	320	s->sr \|= (1 << 4);
ac3c9e74	321	}
2f062c72 TS	322	}
	323
	324	static int sh_serial_can_receive1(void *opaque)
	325	{
	326	sh_serial_state *s = opaque;
	327	return sh_serial_can_receive(s);
	328	}
	329
71bb4ce1 GU	330	static void sh_serial_timeout_int(void *opaque)
	331	{
	332	sh_serial_state *s = opaque;
	333
	334	s->flags \|= SH_SERIAL_FLAG_RDF;
	335	if (s->scr & (1 << 6) && s->rxi) {
	336	qemu_set_irq(s->rxi, 1);
	337	}
	338	}
	339
2f062c72 TS	340	static void sh_serial_receive1(void opaque, const uint8_t buf, int size)
	341	{
	342	sh_serial_state *s = opaque;
b7d2b020 AJ	343
	344	if (s->feat & SH_SERIAL_FEAT_SCIF) {
	345	int i;
	346	for (i = 0; i < size; i++) {
	347	if (s->rx_cnt < SH_RX_FIFO_LENGTH) {
	348	s->rx_fifo[s->rx_head++] = buf[i];
	349	if (s->rx_head == SH_RX_FIFO_LENGTH) {
	350	s->rx_head = 0;
	351	}
	352	s->rx_cnt++;
	353	if (s->rx_cnt >= s->rtrg) {
	354	s->flags \|= SH_SERIAL_FLAG_RDF;
	355	if (s->scr & (1 << 6) && s->rxi) {
71bb4ce1	356	timer_del(s->fifo_timeout_timer);
b7d2b020 AJ	357	qemu_set_irq(s->rxi, 1);
b7d2b020 AJ	358	}
71bb4ce1 GU	359	} else {
	360	timer_mod(s->fifo_timeout_timer,
	361	qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 15 * s->etu);
b7d2b020 AJ	362	}
	363	}
	364	}
	365	} else {
	366	s->rx_fifo[0] = buf[0];
	367	}
2f062c72 TS	368	}
2f062c72 TS	369
083b266f	370	static void sh_serial_event(void *opaque, QEMUChrEvent event)
2f062c72 TS	371	{
2f062c72 TS	372	sh_serial_state *s = opaque;
ac3c9e74	373	if (event == CHR_EVENT_BREAK) {
2f062c72	374	sh_serial_receive_break(s);
ac3c9e74	375	}
2f062c72 TS	376	}
2f062c72 TS	377
9a9d0b81 BC	378	static const MemoryRegionOps sh_serial_ops = {
	379	.read = sh_serial_read,
	380	.write = sh_serial_write,
	381	.endianness = DEVICE_NATIVE_ENDIAN,
2f062c72 TS	382	};
2f062c72 TS	383
9a9d0b81	384	void sh_serial_init(MemoryRegion *sysmem,
a8170e5e	385	hwaddr base, int feat,
0ec7b3e7	386	uint32_t freq, Chardev *chr,
9a9d0b81 BC	387	qemu_irq eri_source,
	388	qemu_irq rxi_source,
	389	qemu_irq txi_source,
	390	qemu_irq tei_source,
	391	qemu_irq bri_source)
2f062c72 TS	392	{
2f062c72 TS	393	sh_serial_state *s;
2f062c72	394
7267c094	395	s = g_malloc0(sizeof(sh_serial_state));
2f062c72	396
2f062c72 TS	397	s->feat = feat;
2f062c72 TS	398	s->flags = SH_SERIAL_FLAG_TEND \| SH_SERIAL_FLAG_TDE;
63242a00	399	s->rtrg = 1;
2f062c72 TS	400
	401	s->smr = 0;
	402	s->brr = 0xff;
b7d35e65	403	s->scr = 1 << 5; /* pretend that TX is enabled so early printk works */
2f062c72 TS	404	s->sptr = 0;
	405
	406	if (feat & SH_SERIAL_FEAT_SCIF) {
	407	s->fcr = 0;
f94bff13	408	} else {
2f062c72 TS	409	s->dr = 0xff;
	410	}
	411
63242a00	412	sh_serial_clear_fifo(s);
2f062c72	413
2c9b15ca	414	memory_region_init_io(&s->iomem, NULL, &sh_serial_ops, s,
9a9d0b81 BC	415	"serial", 0x100000000ULL);
9a9d0b81 BC	416
2c9b15ca	417	memory_region_init_alias(&s->iomem_p4, NULL, "serial-p4", &s->iomem,
9a9d0b81 BC	418	0, 0x28);
	419	memory_region_add_subregion(sysmem, P4ADDR(base), &s->iomem_p4);
	420
2c9b15ca	421	memory_region_init_alias(&s->iomem_a7, NULL, "serial-a7", &s->iomem,
9a9d0b81 BC	422	0, 0x28);
9a9d0b81 BC	423	memory_region_add_subregion(sysmem, A7ADDR(base), &s->iomem_a7);
2f062c72	424
456d6069	425	if (chr) {
32a6ebec	426	qemu_chr_fe_init(&s->chr, chr, &error_abort);
5345fdb4 MAL	427	qemu_chr_fe_set_handlers(&s->chr, sh_serial_can_receive1,
5345fdb4 MAL	428	sh_serial_receive1,
81517ba3	429	sh_serial_event, NULL, s, NULL, true);
456d6069	430	}
bf5b7423	431
71bb4ce1 GU	432	s->fifo_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
	433	sh_serial_timeout_int, s);
	434	s->etu = NANOSECONDS_PER_SECOND / 9600;
bf5b7423 AJ	435	s->eri = eri_source;
	436	s->rxi = rxi_source;
	437	s->txi = txi_source;
	438	s->tei = tei_source;
	439	s->bri = bri_source;
2f062c72	440	}