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Commit | Line | Data |
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dd43edf4 TS |
1 | # mach: crisv0 crisv3 crisv8 crisv10 crisv32 |
2 | # output: aa117acd\n | |
3 | # output: eeaabb42\n | |
4 | ||
5 | ; Bug with move to special register in delay slot, due to | |
6 | ; special flush-insn-cache simulator use. Ordinary move worked; | |
7 | ; special register caused branch to fail. | |
8 | ||
9 | .include "testutils.inc" | |
10 | start | |
11 | move -1,srp | |
12 | ||
13 | move.d 0xaa117acd,r1 | |
14 | moveq 3,r9 | |
15 | cmpq 1,r9 | |
16 | bhi 0f | |
17 | move.d r1,r3 | |
18 | ||
19 | fail | |
20 | 0: | |
21 | checkr3 aa117acd | |
22 | ||
23 | move.d 0xeeaabb42,r1 | |
24 | moveq 3,r9 | |
25 | cmpq 1,r9 | |
26 | bhi 0f | |
27 | move r1,srp | |
28 | ||
29 | fail | |
30 | 0: | |
31 | move srp,r3 | |
32 | checkr3 eeaabb42 | |
33 | quit |