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4040ab72 DG |
1 | #ifndef _HW_SPAPR_VIO_H |
2 | #define _HW_SPAPR_VIO_H | |
3 | /* | |
4 | * QEMU sPAPR VIO bus definitions | |
5 | * | |
6 | * Copyright (c) 2010 David Gibson, IBM Corporation <[email protected]> | |
7 | * Based on the s390 virtio bus definitions: | |
8 | * Copyright (c) 2009 Alexander Graf <[email protected]> | |
9 | * | |
10 | * This library is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU Lesser General Public | |
12 | * License as published by the Free Software Foundation; either | |
13 | * version 2 of the License, or (at your option) any later version. | |
14 | * | |
15 | * This library is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
18 | * Lesser General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU Lesser General Public | |
21 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
22 | */ | |
23 | ||
ee86dfee DG |
24 | #define SPAPR_VIO_TCE_PAGE_SHIFT 12 |
25 | #define SPAPR_VIO_TCE_PAGE_SIZE (1ULL << SPAPR_VIO_TCE_PAGE_SHIFT) | |
26 | #define SPAPR_VIO_TCE_PAGE_MASK (SPAPR_VIO_TCE_PAGE_SIZE - 1) | |
27 | ||
28 | enum VIOsPAPR_TCEAccess { | |
29 | SPAPR_TCE_FAULT = 0, | |
30 | SPAPR_TCE_RO = 1, | |
31 | SPAPR_TCE_WO = 2, | |
32 | SPAPR_TCE_RW = 3, | |
33 | }; | |
34 | ||
b4a78527 DG |
35 | #define SPAPR_VTY_BASE_ADDRESS 0x30000000 |
36 | ||
3954d33a AL |
37 | #define TYPE_VIO_SPAPR_DEVICE "vio-spapr-device" |
38 | #define VIO_SPAPR_DEVICE(obj) \ | |
39 | OBJECT_CHECK(VIOsPAPRDevice, (obj), TYPE_VIO_SPAPR_DEVICE) | |
40 | #define VIO_SPAPR_DEVICE_CLASS(klass) \ | |
41 | OBJECT_CLASS_CHECK(VIOsPAPRDeviceClass, (klass), TYPE_VIO_SPAPR_DEVICE) | |
42 | #define VIO_SPAPR_DEVICE_GET_CLASS(obj) \ | |
43 | OBJECT_GET_CLASS(VIOsPAPRDeviceClass, (obj), TYPE_VIO_SPAPR_DEVICE) | |
44 | ||
b45d63b6 BH |
45 | struct VIOsPAPRDevice; |
46 | ||
ee86dfee DG |
47 | typedef struct VIOsPAPR_RTCE { |
48 | uint64_t tce; | |
49 | } VIOsPAPR_RTCE; | |
50 | ||
b45d63b6 BH |
51 | typedef struct VIOsPAPR_CRQ { |
52 | uint64_t qladdr; | |
53 | uint32_t qsize; | |
54 | uint32_t qnext; | |
55 | int(*SendFunc)(struct VIOsPAPRDevice *vdev, uint8_t *crq); | |
56 | } VIOsPAPR_CRQ; | |
57 | ||
3954d33a AL |
58 | typedef struct VIOsPAPRDevice VIOsPAPRDevice; |
59 | typedef struct VIOsPAPRBus VIOsPAPRBus; | |
60 | ||
61 | typedef struct VIOsPAPRDeviceClass { | |
62 | DeviceClass parent_class; | |
63 | ||
64 | const char *dt_name, *dt_type, *dt_compatible; | |
65 | target_ulong signal_mask; | |
66 | int (*init)(VIOsPAPRDevice *dev); | |
67 | void (*hcalls)(VIOsPAPRBus *bus); | |
68 | int (*devnode)(VIOsPAPRDevice *dev, void *fdt, int node_off); | |
69 | } VIOsPAPRDeviceClass; | |
70 | ||
71 | struct VIOsPAPRDevice { | |
4040ab72 DG |
72 | DeviceState qdev; |
73 | uint32_t reg; | |
08942ac1 BH |
74 | uint32_t flags; |
75 | #define VIO_PAPR_FLAG_DMA_BYPASS 0x1 | |
00dc738d DG |
76 | qemu_irq qirq; |
77 | uint32_t vio_irq_num; | |
78 | target_ulong signal_state; | |
ee86dfee DG |
79 | uint32_t rtce_window_size; |
80 | VIOsPAPR_RTCE *rtce_table; | |
0f5cb298 | 81 | int kvmtce_fd; |
b45d63b6 | 82 | VIOsPAPR_CRQ crq; |
3954d33a | 83 | }; |
4040ab72 | 84 | |
77c7ea5e PB |
85 | #define DEFINE_SPAPR_PROPERTIES(type, field, default_reg, default_dma_window) \ |
86 | DEFINE_PROP_UINT32("reg", type, field.reg, default_reg), \ | |
87 | DEFINE_PROP_UINT32("dma-window", type, field.rtce_window_size, \ | |
88 | default_dma_window) | |
89 | ||
3954d33a | 90 | struct VIOsPAPRBus { |
4040ab72 | 91 | BusState bus; |
4040ab72 | 92 | int (*init)(VIOsPAPRDevice *dev); |
4040ab72 | 93 | int (*devnode)(VIOsPAPRDevice *dev, void *fdt, int node_off); |
3954d33a | 94 | }; |
4040ab72 DG |
95 | |
96 | extern VIOsPAPRBus *spapr_vio_bus_init(void); | |
97 | extern VIOsPAPRDevice *spapr_vio_find_by_reg(VIOsPAPRBus *bus, uint32_t reg); | |
4040ab72 | 98 | extern int spapr_populate_vdevice(VIOsPAPRBus *bus, void *fdt); |
68f3a94c | 99 | extern int spapr_populate_chosen_stdout(void *fdt, VIOsPAPRBus *bus); |
4040ab72 | 100 | |
00dc738d DG |
101 | extern int spapr_vio_signal(VIOsPAPRDevice *dev, target_ulong mode); |
102 | ||
ee86dfee DG |
103 | int spapr_vio_check_tces(VIOsPAPRDevice *dev, target_ulong ioba, |
104 | target_ulong len, | |
105 | enum VIOsPAPR_TCEAccess access); | |
106 | ||
107 | int spapr_tce_dma_read(VIOsPAPRDevice *dev, uint64_t taddr, | |
108 | void *buf, uint32_t size); | |
109 | int spapr_tce_dma_write(VIOsPAPRDevice *dev, uint64_t taddr, | |
110 | const void *buf, uint32_t size); | |
111 | int spapr_tce_dma_zero(VIOsPAPRDevice *dev, uint64_t taddr, uint32_t size); | |
112 | void stb_tce(VIOsPAPRDevice *dev, uint64_t taddr, uint8_t val); | |
113 | void sth_tce(VIOsPAPRDevice *dev, uint64_t taddr, uint16_t val); | |
114 | void stw_tce(VIOsPAPRDevice *dev, uint64_t taddr, uint32_t val); | |
115 | void stq_tce(VIOsPAPRDevice *dev, uint64_t taddr, uint64_t val); | |
116 | uint64_t ldq_tce(VIOsPAPRDevice *dev, uint64_t taddr); | |
117 | ||
b45d63b6 BH |
118 | int spapr_vio_send_crq(VIOsPAPRDevice *dev, uint8_t *crq); |
119 | ||
4040ab72 | 120 | void vty_putchars(VIOsPAPRDevice *sdev, uint8_t *buf, int len); |
277f9acf PB |
121 | void spapr_vty_create(VIOsPAPRBus *bus, uint32_t reg, CharDriverState *chardev); |
122 | void spapr_vlan_create(VIOsPAPRBus *bus, uint32_t reg, NICInfo *nd); | |
123 | void spapr_vscsi_create(VIOsPAPRBus *bus, uint32_t reg); | |
6e270446 | 124 | |
68f3a94c DG |
125 | VIOsPAPRDevice *spapr_vty_get_default(VIOsPAPRBus *bus); |
126 | ||
08942ac1 BH |
127 | int spapr_tce_set_bypass(uint32_t unit, uint32_t enable); |
128 | void spapr_vio_quiesce(void); | |
129 | ||
4040ab72 | 130 | #endif /* _HW_SPAPR_VIO_H */ |