[qemu.git] / hw / microblaze / petalogix_ml605_mmu.c

/*
 * Model of Petalogix linux reference design targeting Xilinx Spartan ml605
 * board.
 *
 * Copyright (c) 2011 Michal Simek <monstr@monstr.eu>
 * Copyright (c) 2011 PetaLogix
 * Copyright (c) 2009 Edgar E. Iglesias.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qemu-common.h"
#include "cpu.h"
#include "hw/sysbus.h"
#include "hw/hw.h"
#include "net/net.h"
#include "hw/block/flash.h"
#include "sysemu/sysemu.h"
#include "hw/devices.h"
#include "hw/boards.h"
#include "sysemu/block-backend.h"
#include "hw/char/serial.h"
#include "exec/address-spaces.h"
#include "hw/ssi/ssi.h"

#include "boot.h"

#include "hw/stream.h"

#define LMB_BRAM_SIZE  (128 * 1024)
#define FLASH_SIZE     (32 * 1024 * 1024)

#define BINARY_DEVICE_TREE_FILE "petalogix-ml605.dtb"

#define NUM_SPI_FLASHES 4

#define SPI_BASEADDR 0x40a00000
#define MEMORY_BASEADDR 0x50000000
#define FLASH_BASEADDR 0x86000000
#define INTC_BASEADDR 0x81800000
#define TIMER_BASEADDR 0x83c00000
#define UART16550_BASEADDR 0x83e00000
#define AXIENET_BASEADDR 0x82780000
#define AXIDMA_BASEADDR 0x84600000

#define AXIDMA_IRQ1         0
#define AXIDMA_IRQ0         1
#define TIMER_IRQ           2
#define AXIENET_IRQ         3
#define SPI_IRQ             4
#define UART16550_IRQ       5

static void
petalogix_ml605_init(MachineState *machine)
{
    ram_addr_t ram_size = machine->ram_size;
    MemoryRegion *address_space_mem = get_system_memory();
    DeviceState *dev, *dma, *eth0;
    Object *ds, *cs;
    MicroBlazeCPU *cpu;
    SysBusDevice *busdev;
    DriveInfo *dinfo;
    int i;
    MemoryRegion *phys_lmb_bram = g_new(MemoryRegion, 1);
    MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
    qemu_irq irq[32];

    /* init CPUs */
    cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU));
    object_property_set_str(OBJECT(cpu), "8.10.a", "version", &error_abort);
    /* Use FPU but don't use floating point conversion and square
     * root instructions
     */
    object_property_set_int(OBJECT(cpu), 1, "use-fpu", &error_abort);
    object_property_set_bool(OBJECT(cpu), true, "dcache-writeback",
                             &error_abort);
    object_property_set_bool(OBJECT(cpu), true, "endianness", &error_abort);
    object_property_set_bool(OBJECT(cpu), true, "realized", &error_abort);

    /* Attach emulated BRAM through the LMB.  */
    memory_region_init_ram(phys_lmb_bram, NULL, "petalogix_ml605.lmb_bram",
                           LMB_BRAM_SIZE, &error_fatal);
    vmstate_register_ram_global(phys_lmb_bram);
    memory_region_add_subregion(address_space_mem, 0x00000000, phys_lmb_bram);

    memory_region_init_ram(phys_ram, NULL, "petalogix_ml605.ram", ram_size,
                           &error_fatal);
    vmstate_register_ram_global(phys_ram);
    memory_region_add_subregion(address_space_mem, MEMORY_BASEADDR, phys_ram);

    dinfo = drive_get(IF_PFLASH, 0, 0);
    /* 5th parameter 2 means bank-width
     * 10th paremeter 0 means little-endian */
    pflash_cfi01_register(FLASH_BASEADDR,
                          NULL, "petalogix_ml605.flash", FLASH_SIZE,
                          dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
                          (64 * 1024), FLASH_SIZE >> 16,
                          2, 0x89, 0x18, 0x0000, 0x0, 0);


    dev = qdev_create(NULL, "xlnx.xps-intc");
    qdev_prop_set_uint32(dev, "kind-of-intr", 1 << TIMER_IRQ);
    qdev_init_nofail(dev);
    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR);
    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
                       qdev_get_gpio_in(DEVICE(cpu), MB_CPU_IRQ));
    for (i = 0; i < 32; i++) {
        irq[i] = qdev_get_gpio_in(dev, i);
    }

    serial_mm_init(address_space_mem, UART16550_BASEADDR + 0x1000, 2,
                   irq[UART16550_IRQ], 115200, serial_hds[0],
                   DEVICE_LITTLE_ENDIAN);

    /* 2 timers at irq 2 @ 100 Mhz.  */
    dev = qdev_create(NULL, "xlnx.xps-timer");
    qdev_prop_set_uint32(dev, "one-timer-only", 0);
    qdev_prop_set_uint32(dev, "clock-frequency", 100 * 1000000);
    qdev_init_nofail(dev);
    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR);
    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]);

    /* axi ethernet and dma initialization. */
    qemu_check_nic_model(&nd_table[0], "xlnx.axi-ethernet");
    eth0 = qdev_create(NULL, "xlnx.axi-ethernet");
    dma = qdev_create(NULL, "xlnx.axi-dma");

    /* FIXME: attach to the sysbus instead */
    object_property_add_child(qdev_get_machine(), "xilinx-eth", OBJECT(eth0),
                              NULL);
    object_property_add_child(qdev_get_machine(), "xilinx-dma", OBJECT(dma),
                              NULL);

    ds = object_property_get_link(OBJECT(dma),
                                  "axistream-connected-target", NULL);
    cs = object_property_get_link(OBJECT(dma),
                                  "axistream-control-connected-target", NULL);
    qdev_set_nic_properties(eth0, &nd_table[0]);
    qdev_prop_set_uint32(eth0, "rxmem", 0x1000);
    qdev_prop_set_uint32(eth0, "txmem", 0x1000);
    object_property_set_link(OBJECT(eth0), OBJECT(ds),
                             "axistream-connected", &error_abort);
    object_property_set_link(OBJECT(eth0), OBJECT(cs),
                             "axistream-control-connected", &error_abort);
    qdev_init_nofail(eth0);
    sysbus_mmio_map(SYS_BUS_DEVICE(eth0), 0, AXIENET_BASEADDR);
    sysbus_connect_irq(SYS_BUS_DEVICE(eth0), 0, irq[AXIENET_IRQ]);

    ds = object_property_get_link(OBJECT(eth0),
                                  "axistream-connected-target", NULL);
    cs = object_property_get_link(OBJECT(eth0),
                                  "axistream-control-connected-target", NULL);
    qdev_prop_set_uint32(dma, "freqhz", 100 * 1000000);
    object_property_set_link(OBJECT(dma), OBJECT(ds),
                             "axistream-connected", &error_abort);
    object_property_set_link(OBJECT(dma), OBJECT(cs),
                             "axistream-control-connected", &error_abort);
    qdev_init_nofail(dma);
    sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, AXIDMA_BASEADDR);
    sysbus_connect_irq(SYS_BUS_DEVICE(dma), 0, irq[AXIDMA_IRQ0]);
    sysbus_connect_irq(SYS_BUS_DEVICE(dma), 1, irq[AXIDMA_IRQ1]);

    {
        SSIBus *spi;

        dev = qdev_create(NULL, "xlnx.xps-spi");
        qdev_prop_set_uint8(dev, "num-ss-bits", NUM_SPI_FLASHES);
        qdev_init_nofail(dev);
        busdev = SYS_BUS_DEVICE(dev);
        sysbus_mmio_map(busdev, 0, SPI_BASEADDR);
        sysbus_connect_irq(busdev, 0, irq[SPI_IRQ]);

        spi = (SSIBus *)qdev_get_child_bus(dev, "spi");

        for (i = 0; i < NUM_SPI_FLASHES; i++) {
            DriveInfo *dinfo = drive_get_next(IF_MTD);
            qemu_irq cs_line;

            dev = ssi_create_slave_no_init(spi, "n25q128");
            if (dinfo) {
                qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
                                    &error_fatal);
            }
            qdev_init_nofail(dev);

            cs_line = qdev_get_gpio_in_named(dev, SSI_GPIO_CS, 0);
            sysbus_connect_irq(busdev, i+1, cs_line);
        }
    }

    /* setup PVR to match kernel settings */
    cpu->env.pvr.regs[4] = 0xc56b8000;
    cpu->env.pvr.regs[5] = 0xc56be000;
    cpu->env.pvr.regs[10] = 0x0e000000; /* virtex 6 */

    microblaze_load_kernel(cpu, MEMORY_BASEADDR, ram_size,
                           machine->initrd_filename,
                           BINARY_DEVICE_TREE_FILE,
                           NULL);

}

static void petalogix_ml605_machine_init(MachineClass *mc)
{
    mc->desc = "PetaLogix linux refdesign for xilinx ml605 little endian";
    mc->init = petalogix_ml605_init;
    mc->is_default = 0;
}

DEFINE_MACHINE("petalogix-ml605", petalogix_ml605_machine_init)
Commit	Line	Data
00914b7d MS	1	/*
	2	* Model of Petalogix linux reference design targeting Xilinx Spartan ml605
	3	* board.
	4	*
	5	* Copyright (c) 2011 Michal Simek <monstr@monstr.eu>
	6	* Copyright (c) 2011 PetaLogix
	7	* Copyright (c) 2009 Edgar E. Iglesias.
	8	*
	9	* Permission is hereby granted, free of charge, to any person obtaining a copy
	10	* of this software and associated documentation files (the "Software"), to deal
	11	* in the Software without restriction, including without limitation the rights
	12	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	13	* copies of the Software, and to permit persons to whom the Software is
	14	* furnished to do so, subject to the following conditions:
	15	*
	16	* The above copyright notice and this permission notice shall be included in
	17	* all copies or substantial portions of the Software.
	18	*
	19	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	20	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	21	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	22	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	23	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	24	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	25	* THE SOFTWARE.
	26	*/
	27
8fd9dece	28	#include "qemu/osdep.h"
da34e65c	29	#include "qapi/error.h"
4771d756 PB	30	#include "qemu-common.h"
4771d756 PB	31	#include "cpu.h"
83c9f4ca PB	32	#include "hw/sysbus.h"
83c9f4ca PB	33	#include "hw/hw.h"
1422e32d	34	#include "net/net.h"
0d09e41a	35	#include "hw/block/flash.h"
9c17d615	36	#include "sysemu/sysemu.h"
bd2be150	37	#include "hw/devices.h"
83c9f4ca	38	#include "hw/boards.h"
fa1d36df	39	#include "sysemu/block-backend.h"
0d09e41a	40	#include "hw/char/serial.h"
022c62cb	41	#include "exec/address-spaces.h"
8fd06719	42	#include "hw/ssi/ssi.h"
00914b7d	43
47b43a1f	44	#include "boot.h"
669b4983	45
83c9f4ca	46	#include "hw/stream.h"
00914b7d MS	47
	48	#define LMB_BRAM_SIZE (128 * 1024)
	49	#define FLASH_SIZE (32 * 1024 * 1024)
	50
d94e7434	51	#define BINARY_DEVICE_TREE_FILE "petalogix-ml605.dtb"
00914b7d	52
acd3b6be PC	53	#define NUM_SPI_FLASHES 4
acd3b6be PC	54
8174196b	55	#define SPI_BASEADDR 0x40a00000
d94e7434 PC	56	#define MEMORY_BASEADDR 0x50000000
	57	#define FLASH_BASEADDR 0x86000000
	58	#define INTC_BASEADDR 0x81800000
	59	#define TIMER_BASEADDR 0x83c00000
	60	#define UART16550_BASEADDR 0x83e00000
	61	#define AXIENET_BASEADDR 0x82780000
	62	#define AXIDMA_BASEADDR 0x84600000
00914b7d	63
8174196b PC	64	#define AXIDMA_IRQ1 0
	65	#define AXIDMA_IRQ0 1
	66	#define TIMER_IRQ 2
	67	#define AXIENET_IRQ 3
	68	#define SPI_IRQ 4
	69	#define UART16550_IRQ 5
	70
00914b7d	71	static void
3ef96221	72	petalogix_ml605_init(MachineState *machine)
00914b7d	73	{
3ef96221	74	ram_addr_t ram_size = machine->ram_size;
39186d8a	75	MemoryRegion *address_space_mem = get_system_memory();
669b4983	76	DeviceState dev, dma, *eth0;
42bb9c91	77	Object ds, cs;
a9480e5d	78	MicroBlazeCPU *cpu;
acd3b6be	79	SysBusDevice *busdev;
00914b7d MS	80	DriveInfo *dinfo;
00914b7d MS	81	int i;
d7973c77 AK	82	MemoryRegion *phys_lmb_bram = g_new(MemoryRegion, 1);
d7973c77 AK	83	MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
73c69456	84	qemu_irq irq[32];
00914b7d MS	85
00914b7d MS	86	/* init CPUs */
a4550442	87	cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU));
a7e00e25	88	object_property_set_str(OBJECT(cpu), "8.10.a", "version", &error_abort);
4e5d45ae AF	89	/* Use FPU but don't use floating point conversion and square
	90	* root instructions
	91	*/
	92	object_property_set_int(OBJECT(cpu), 1, "use-fpu", &error_abort);
a6c3ed24 AF	93	object_property_set_bool(OBJECT(cpu), true, "dcache-writeback",
a6c3ed24 AF	94	&error_abort);
a88bbb00	95	object_property_set_bool(OBJECT(cpu), true, "endianness", &error_abort);
a4550442	96	object_property_set_bool(OBJECT(cpu), true, "realized", &error_abort);
00914b7d	97
00914b7d	98	/* Attach emulated BRAM through the LMB. */
2c9b15ca	99	memory_region_init_ram(phys_lmb_bram, NULL, "petalogix_ml605.lmb_bram",
f8ed85ac	100	LMB_BRAM_SIZE, &error_fatal);
c5705a77	101	vmstate_register_ram_global(phys_lmb_bram);
d7973c77	102	memory_region_add_subregion(address_space_mem, 0x00000000, phys_lmb_bram);
00914b7d	103
49946538	104	memory_region_init_ram(phys_ram, NULL, "petalogix_ml605.ram", ram_size,
f8ed85ac	105	&error_fatal);
c5705a77	106	vmstate_register_ram_global(phys_ram);
f55f8852	107	memory_region_add_subregion(address_space_mem, MEMORY_BASEADDR, phys_ram);
00914b7d	108
00914b7d MS	109	dinfo = drive_get(IF_PFLASH, 0, 0);
	110	/* 5th parameter 2 means bank-width
	111	* 10th paremeter 0 means little-endian */
cfe5f011 AK	112	pflash_cfi01_register(FLASH_BASEADDR,
cfe5f011 AK	113	NULL, "petalogix_ml605.flash", FLASH_SIZE,
4be74634	114	dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
fa1d36df	115	(64 * 1024), FLASH_SIZE >> 16,
01e0451a	116	2, 0x89, 0x18, 0x0000, 0x0, 0);
00914b7d MS	117
00914b7d MS	118
13c9bfbf PC	119	dev = qdev_create(NULL, "xlnx.xps-intc");
	120	qdev_prop_set_uint32(dev, "kind-of-intr", 1 << TIMER_IRQ);
	121	qdev_init_nofail(dev);
	122	sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR);
	123	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
	124	qdev_get_gpio_in(DEVICE(cpu), MB_CPU_IRQ));
00914b7d MS	125	for (i = 0; i < 32; i++) {
	126	irq[i] = qdev_get_gpio_in(dev, i);
	127	}
	128
39186d8a	129	serial_mm_init(address_space_mem, UART16550_BASEADDR + 0x1000, 2,
8174196b PC	130	irq[UART16550_IRQ], 115200, serial_hds[0],
8174196b PC	131	DEVICE_LITTLE_ENDIAN);
00914b7d MS	132
00914b7d MS	133	/* 2 timers at irq 2 @ 100 Mhz. */
29873712 PC	134	dev = qdev_create(NULL, "xlnx.xps-timer");
	135	qdev_prop_set_uint32(dev, "one-timer-only", 0);
	136	qdev_prop_set_uint32(dev, "clock-frequency", 100 * 1000000);
	137	qdev_init_nofail(dev);
	138	sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR);
	139	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]);
00914b7d	140
669b4983	141	/* axi ethernet and dma initialization. */
dada5c7e PC	142	qemu_check_nic_model(&nd_table[0], "xlnx.axi-ethernet");
dada5c7e PC	143	eth0 = qdev_create(NULL, "xlnx.axi-ethernet");
669b4983	144	dma = qdev_create(NULL, "xlnx.axi-dma");
00914b7d	145
669b4983	146	/* FIXME: attach to the sysbus instead */
b19ceaad PC	147	object_property_add_child(qdev_get_machine(), "xilinx-eth", OBJECT(eth0),
b19ceaad PC	148	NULL);
54ff2a39 PC	149	object_property_add_child(qdev_get_machine(), "xilinx-dma", OBJECT(dma),
54ff2a39 PC	150	NULL);
669b4983	151
42bb9c91 PC	152	ds = object_property_get_link(OBJECT(dma),
	153	"axistream-connected-target", NULL);
	154	cs = object_property_get_link(OBJECT(dma),
	155	"axistream-control-connected-target", NULL);
d91a68a7 PC	156	qdev_set_nic_properties(eth0, &nd_table[0]);
	157	qdev_prop_set_uint32(eth0, "rxmem", 0x1000);
	158	qdev_prop_set_uint32(eth0, "txmem", 0x1000);
	159	object_property_set_link(OBJECT(eth0), OBJECT(ds),
	160	"axistream-connected", &error_abort);
	161	object_property_set_link(OBJECT(eth0), OBJECT(cs),
	162	"axistream-control-connected", &error_abort);
	163	qdev_init_nofail(eth0);
	164	sysbus_mmio_map(SYS_BUS_DEVICE(eth0), 0, AXIENET_BASEADDR);
	165	sysbus_connect_irq(SYS_BUS_DEVICE(eth0), 0, irq[AXIENET_IRQ]);
42bb9c91 PC	166
	167	ds = object_property_get_link(OBJECT(eth0),
	168	"axistream-connected-target", NULL);
	169	cs = object_property_get_link(OBJECT(eth0),
	170	"axistream-control-connected-target", NULL);
d91a68a7 PC	171	qdev_prop_set_uint32(dma, "freqhz", 100 * 1000000);
	172	object_property_set_link(OBJECT(dma), OBJECT(ds),
	173	"axistream-connected", &error_abort);
	174	object_property_set_link(OBJECT(dma), OBJECT(cs),
	175	"axistream-control-connected", &error_abort);
	176	qdev_init_nofail(dma);
	177	sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, AXIDMA_BASEADDR);
	178	sysbus_connect_irq(SYS_BUS_DEVICE(dma), 0, irq[AXIDMA_IRQ0]);
	179	sysbus_connect_irq(SYS_BUS_DEVICE(dma), 1, irq[AXIDMA_IRQ1]);
00914b7d	180
acd3b6be PC	181	{
	182	SSIBus *spi;
	183
	184	dev = qdev_create(NULL, "xlnx.xps-spi");
	185	qdev_prop_set_uint8(dev, "num-ss-bits", NUM_SPI_FLASHES);
	186	qdev_init_nofail(dev);
1356b98d	187	busdev = SYS_BUS_DEVICE(dev);
8174196b PC	188	sysbus_mmio_map(busdev, 0, SPI_BASEADDR);
8174196b PC	189	sysbus_connect_irq(busdev, 0, irq[SPI_IRQ]);
acd3b6be PC	190
	191	spi = (SSIBus *)qdev_get_child_bus(dev, "spi");
	192
	193	for (i = 0; i < NUM_SPI_FLASHES; i++) {
73bce518	194	DriveInfo *dinfo = drive_get_next(IF_MTD);
acd3b6be PC	195	qemu_irq cs_line;
acd3b6be PC	196
73bce518 PB	197	dev = ssi_create_slave_no_init(spi, "n25q128");
	198	if (dinfo) {
	199	qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
	200	&error_fatal);
	201	}
	202	qdev_init_nofail(dev);
	203
de77914e	204	cs_line = qdev_get_gpio_in_named(dev, SSI_GPIO_CS, 0);
acd3b6be PC	205	sysbus_connect_irq(busdev, i+1, cs_line);
	206	}
	207	}
	208
a87310a6 AF	209	/* setup PVR to match kernel settings */
	210	cpu->env.pvr.regs[4] = 0xc56b8000;
	211	cpu->env.pvr.regs[5] = 0xc56be000;
	212	cpu->env.pvr.regs[10] = 0x0e000000; /* virtex 6 */
	213
f55f8852	214	microblaze_load_kernel(cpu, MEMORY_BASEADDR, ram_size,
3ef96221	215	machine->initrd_filename,
d0b022a0	216	BINARY_DEVICE_TREE_FILE,
a87310a6	217	NULL);
00914b7d	218
00914b7d MS	219	}
00914b7d MS	220
e264d29d	221	static void petalogix_ml605_machine_init(MachineClass *mc)
00914b7d	222	{
e264d29d EH	223	mc->desc = "PetaLogix linux refdesign for xilinx ml605 little endian";
	224	mc->init = petalogix_ml605_init;
	225	mc->is_default = 0;
00914b7d MS	226	}
00914b7d MS	227
e264d29d	228	DEFINE_MACHINE("petalogix-ml605", petalogix_ml605_machine_init)