[qemu.git] / hw / arm / xlnx-zynqmp.c

/*
 * Xilinx Zynq MPSoC emulation
 *
 * Copyright (C) 2015 Xilinx Inc
 * Written by Peter Crosthwaite <[email protected]>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
 * for more details.
 */

#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qemu-common.h"
#include "cpu.h"
#include "hw/arm/xlnx-zynqmp.h"
#include "hw/intc/arm_gic_common.h"
#include "exec/address-spaces.h"
#include "sysemu/kvm.h"
#include "kvm_arm.h"

#define GIC_NUM_SPI_INTR 160

#define ARM_PHYS_TIMER_PPI  30
#define ARM_VIRT_TIMER_PPI  27

#define GEM_REVISION        0x40070106

#define GIC_BASE_ADDR       0xf9000000
#define GIC_DIST_ADDR       0xf9010000
#define GIC_CPU_ADDR        0xf9020000

#define SATA_INTR           133
#define SATA_ADDR           0xFD0C0000
#define SATA_NUM_PORTS      2

#define QSPI_ADDR           0xff0f0000
#define LQSPI_ADDR          0xc0000000
#define QSPI_IRQ            15

#define DP_ADDR             0xfd4a0000
#define DP_IRQ              113

#define DPDMA_ADDR          0xfd4c0000
#define DPDMA_IRQ           116

#define IPI_ADDR            0xFF300000
#define IPI_IRQ             64

#define RTC_ADDR            0xffa60000
#define RTC_IRQ             26

#define SDHCI_CAPABILITIES  0x280737ec6481 /* Datasheet: UG1085 (v1.7) */

static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
    0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000,
};

static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = {
    57, 59, 61, 63,
};

static const uint64_t uart_addr[XLNX_ZYNQMP_NUM_UARTS] = {
    0xFF000000, 0xFF010000,
};

static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = {
    21, 22,
};

static const uint64_t sdhci_addr[XLNX_ZYNQMP_NUM_SDHCI] = {
    0xFF160000, 0xFF170000,
};

static const int sdhci_intr[XLNX_ZYNQMP_NUM_SDHCI] = {
    48, 49,
};

static const uint64_t spi_addr[XLNX_ZYNQMP_NUM_SPIS] = {
    0xFF040000, 0xFF050000,
};

static const int spi_intr[XLNX_ZYNQMP_NUM_SPIS] = {
    19, 20,
};

typedef struct XlnxZynqMPGICRegion {
    int region_index;
    uint32_t address;
} XlnxZynqMPGICRegion;

static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = {
    { .region_index = 0, .address = GIC_DIST_ADDR, },
    { .region_index = 1, .address = GIC_CPU_ADDR,  },
};

static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index)
{
    return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index;
}

static void xlnx_zynqmp_create_rpu(XlnxZynqMPState *s, const char *boot_cpu,
                                   Error **errp)
{
    Error *err = NULL;
    int i;
    int num_rpus = MIN(smp_cpus - XLNX_ZYNQMP_NUM_APU_CPUS, XLNX_ZYNQMP_NUM_RPU_CPUS);

    for (i = 0; i < num_rpus; i++) {
        char *name;

        object_initialize(&s->rpu_cpu[i], sizeof(s->rpu_cpu[i]),
                          "cortex-r5-" TYPE_ARM_CPU);
        object_property_add_child(OBJECT(s), "rpu-cpu[*]",
                                  OBJECT(&s->rpu_cpu[i]), &error_abort);

        name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i]));
        if (strcmp(name, boot_cpu)) {
            /* Secondary CPUs start in PSCI powered-down state */
            object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true,
                                     "start-powered-off", &error_abort);
        } else {
            s->boot_cpu_ptr = &s->rpu_cpu[i];
        }
        g_free(name);

        object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "reset-hivecs",
                                 &error_abort);
        object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "realized",
                                 &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
    }
}

static void xlnx_zynqmp_init(Object *obj)
{
    XlnxZynqMPState *s = XLNX_ZYNQMP(obj);
    int i;
    int num_apus = MIN(smp_cpus, XLNX_ZYNQMP_NUM_APU_CPUS);

    for (i = 0; i < num_apus; i++) {
        object_initialize(&s->apu_cpu[i], sizeof(s->apu_cpu[i]),
                          "cortex-a53-" TYPE_ARM_CPU);
        object_property_add_child(obj, "apu-cpu[*]", OBJECT(&s->apu_cpu[i]),
                                  &error_abort);
    }

    object_initialize(&s->gic, sizeof(s->gic), gic_class_name());
    qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default());

    for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
        object_initialize(&s->gem[i], sizeof(s->gem[i]), TYPE_CADENCE_GEM);
        qdev_set_parent_bus(DEVICE(&s->gem[i]), sysbus_get_default());
    }

    for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
        object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_CADENCE_UART);
        qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default());
    }

    object_initialize(&s->sata, sizeof(s->sata), TYPE_SYSBUS_AHCI);
    qdev_set_parent_bus(DEVICE(&s->sata), sysbus_get_default());

    for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
        object_initialize(&s->sdhci[i], sizeof(s->sdhci[i]),
                          TYPE_SYSBUS_SDHCI);
        qdev_set_parent_bus(DEVICE(&s->sdhci[i]),
                            sysbus_get_default());
    }

    for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
        object_initialize(&s->spi[i], sizeof(s->spi[i]),
                          TYPE_XILINX_SPIPS);
        qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
    }

    object_initialize(&s->qspi, sizeof(s->qspi), TYPE_XLNX_ZYNQMP_QSPIPS);
    qdev_set_parent_bus(DEVICE(&s->qspi), sysbus_get_default());

    object_initialize(&s->dp, sizeof(s->dp), TYPE_XLNX_DP);
    qdev_set_parent_bus(DEVICE(&s->dp), sysbus_get_default());

    object_initialize(&s->dpdma, sizeof(s->dpdma), TYPE_XLNX_DPDMA);
    qdev_set_parent_bus(DEVICE(&s->dpdma), sysbus_get_default());

    object_initialize(&s->ipi, sizeof(s->ipi), TYPE_XLNX_ZYNQMP_IPI);
    qdev_set_parent_bus(DEVICE(&s->ipi), sysbus_get_default());

    object_initialize(&s->rtc, sizeof(s->rtc), TYPE_XLNX_ZYNQMP_RTC);
    qdev_set_parent_bus(DEVICE(&s->rtc), sysbus_get_default());
}

static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
{
    XlnxZynqMPState *s = XLNX_ZYNQMP(dev);
    MemoryRegion *system_memory = get_system_memory();
    uint8_t i;
    uint64_t ram_size;
    int num_apus = MIN(smp_cpus, XLNX_ZYNQMP_NUM_APU_CPUS);
    const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]";
    ram_addr_t ddr_low_size, ddr_high_size;
    qemu_irq gic_spi[GIC_NUM_SPI_INTR];
    Error *err = NULL;

    ram_size = memory_region_size(s->ddr_ram);

    /* Create the DDR Memory Regions. User friendly checks should happen at
     * the board level
     */
    if (ram_size > XLNX_ZYNQMP_MAX_LOW_RAM_SIZE) {
        /* The RAM size is above the maximum available for the low DDR.
         * Create the high DDR memory region as well.
         */
        assert(ram_size <= XLNX_ZYNQMP_MAX_RAM_SIZE);
        ddr_low_size = XLNX_ZYNQMP_MAX_LOW_RAM_SIZE;
        ddr_high_size = ram_size - XLNX_ZYNQMP_MAX_LOW_RAM_SIZE;

        memory_region_init_alias(&s->ddr_ram_high, NULL,
                                 "ddr-ram-high", s->ddr_ram,
                                  ddr_low_size, ddr_high_size);
        memory_region_add_subregion(get_system_memory(),
                                    XLNX_ZYNQMP_HIGH_RAM_START,
                                    &s->ddr_ram_high);
    } else {
        /* RAM must be non-zero */
        assert(ram_size);
        ddr_low_size = ram_size;
    }

    memory_region_init_alias(&s->ddr_ram_low, NULL,
                             "ddr-ram-low", s->ddr_ram,
                              0, ddr_low_size);
    memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram_low);

    /* Create the four OCM banks */
    for (i = 0; i < XLNX_ZYNQMP_NUM_OCM_BANKS; i++) {
        char *ocm_name = g_strdup_printf("zynqmp.ocm_ram_bank_%d", i);

        memory_region_init_ram(&s->ocm_ram[i], NULL, ocm_name,
                               XLNX_ZYNQMP_OCM_RAM_SIZE, &error_fatal);
        memory_region_add_subregion(get_system_memory(),
                                    XLNX_ZYNQMP_OCM_RAM_0_ADDRESS +
                                        i * XLNX_ZYNQMP_OCM_RAM_SIZE,
                                    &s->ocm_ram[i]);

        g_free(ocm_name);
    }

    qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32);
    qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
    qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", num_apus);

    /* Realize APUs before realizing the GIC. KVM requires this.  */
    for (i = 0; i < num_apus; i++) {
        char *name;

        object_property_set_int(OBJECT(&s->apu_cpu[i]), QEMU_PSCI_CONDUIT_SMC,
                                "psci-conduit", &error_abort);

        name = object_get_canonical_path_component(OBJECT(&s->apu_cpu[i]));
        if (strcmp(name, boot_cpu)) {
            /* Secondary CPUs start in PSCI powered-down state */
            object_property_set_bool(OBJECT(&s->apu_cpu[i]), true,
                                     "start-powered-off", &error_abort);
        } else {
            s->boot_cpu_ptr = &s->apu_cpu[i];
        }
        g_free(name);

        object_property_set_bool(OBJECT(&s->apu_cpu[i]),
                                 s->secure, "has_el3", NULL);
        object_property_set_bool(OBJECT(&s->apu_cpu[i]),
                                 s->virt, "has_el2", NULL);
        object_property_set_int(OBJECT(&s->apu_cpu[i]), GIC_BASE_ADDR,
                                "reset-cbar", &error_abort);
        object_property_set_int(OBJECT(&s->apu_cpu[i]), num_apus,
                                "core-count", &error_abort);
        object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, "realized",
                                 &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
    }

    object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }

    assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS);
    for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) {
        SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic);
        const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i];
        MemoryRegion *mr = sysbus_mmio_get_region(gic, r->region_index);
        uint32_t addr = r->address;
        int j;

        sysbus_mmio_map(gic, r->region_index, addr);

        for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) {
            MemoryRegion *alias = &s->gic_mr[i][j];

            addr += XLNX_ZYNQMP_GIC_REGION_SIZE;
            memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr,
                                     0, XLNX_ZYNQMP_GIC_REGION_SIZE);
            memory_region_add_subregion(system_memory, addr, alias);
        }
    }

    for (i = 0; i < num_apus; i++) {
        qemu_irq irq;

        sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
                           qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
                                            ARM_CPU_IRQ));
        irq = qdev_get_gpio_in(DEVICE(&s->gic),
                               arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI));
        qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 0, irq);
        irq = qdev_get_gpio_in(DEVICE(&s->gic),
                               arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI));
        qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 1, irq);
    }

    if (s->has_rpu) {
        info_report("The 'has_rpu' property is no longer required, to use the "
                    "RPUs just use -smp 6.");
    }

    xlnx_zynqmp_create_rpu(s, boot_cpu, &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }

    if (!s->boot_cpu_ptr) {
        error_setg(errp, "ZynqMP Boot cpu %s not found", boot_cpu);
        return;
    }

    for (i = 0; i < GIC_NUM_SPI_INTR; i++) {
        gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i);
    }

    for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
        NICInfo *nd = &nd_table[i];

        if (nd->used) {
            qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
            qdev_set_nic_properties(DEVICE(&s->gem[i]), nd);
        }
        object_property_set_int(OBJECT(&s->gem[i]), GEM_REVISION, "revision",
                                &error_abort);
        object_property_set_int(OBJECT(&s->gem[i]), 2, "num-priority-queues",
                                &error_abort);
        object_property_set_bool(OBJECT(&s->gem[i]), true, "realized", &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0,
                           gic_spi[gem_intr[i]]);
    }

    for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
        qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hds[i]);
        object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, uart_addr[i]);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
                           gic_spi[uart_intr[i]]);
    }

    object_property_set_int(OBJECT(&s->sata), SATA_NUM_PORTS, "num-ports",
                            &error_abort);
    object_property_set_bool(OBJECT(&s->sata), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }

    sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SATA_ADDR);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]);

    for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
        char *bus_name = g_strdup_printf("sd-bus%d", i);
        SysBusDevice *sbd = SYS_BUS_DEVICE(&s->sdhci[i]);
        Object *sdhci = OBJECT(&s->sdhci[i]);

        /* Compatible with:
         * - SD Host Controller Specification Version 3.00
         * - SDIO Specification Version 3.0
         * - eMMC Specification Version 4.51
         */
        object_property_set_uint(sdhci, 3, "sd-spec-version", &err);
        object_property_set_uint(sdhci, SDHCI_CAPABILITIES, "capareg", &err);
        object_property_set_uint(sdhci, UHS_I, "uhs", &err);
        object_property_set_bool(sdhci, true, "realized", &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
        sysbus_mmio_map(sbd, 0, sdhci_addr[i]);
        sysbus_connect_irq(sbd, 0, gic_spi[sdhci_intr[i]]);

        /* Alias controller SD bus to the SoC itself */
        object_property_add_alias(OBJECT(s), bus_name, sdhci, "sd-bus",
                                  &error_abort);
        g_free(bus_name);
    }

    for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
        gchar *bus_name;

        object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);

        sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
                           gic_spi[spi_intr[i]]);

        /* Alias controller SPI bus to the SoC itself */
        bus_name = g_strdup_printf("spi%d", i);
        object_property_add_alias(OBJECT(s), bus_name,
                                  OBJECT(&s->spi[i]), "spi0",
                                  &error_abort);
        g_free(bus_name);
    }

    object_property_set_bool(OBJECT(&s->qspi), true, "realized", &err);
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 0, QSPI_ADDR);
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 1, LQSPI_ADDR);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->qspi), 0, gic_spi[QSPI_IRQ]);

    for (i = 0; i < XLNX_ZYNQMP_NUM_QSPI_BUS; i++) {
        gchar *bus_name;
        gchar *target_bus;

        /* Alias controller SPI bus to the SoC itself */
        bus_name = g_strdup_printf("qspi%d", i);
        target_bus = g_strdup_printf("spi%d", i);
        object_property_add_alias(OBJECT(s), bus_name,
                                  OBJECT(&s->qspi), target_bus,
                                  &error_abort);
        g_free(bus_name);
        g_free(target_bus);
    }

    object_property_set_bool(OBJECT(&s->dp), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->dp), 0, DP_ADDR);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->dp), 0, gic_spi[DP_IRQ]);

    object_property_set_bool(OBJECT(&s->dpdma), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    object_property_set_link(OBJECT(&s->dp), OBJECT(&s->dpdma), "dpdma",
                             &error_abort);
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->dpdma), 0, DPDMA_ADDR);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->dpdma), 0, gic_spi[DPDMA_IRQ]);

    object_property_set_bool(OBJECT(&s->ipi), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->ipi), 0, IPI_ADDR);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->ipi), 0, gic_spi[IPI_IRQ]);

    object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, RTC_ADDR);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, gic_spi[RTC_IRQ]);
}

static Property xlnx_zynqmp_props[] = {
    DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu),
    DEFINE_PROP_BOOL("secure", XlnxZynqMPState, secure, false),
    DEFINE_PROP_BOOL("virtualization", XlnxZynqMPState, virt, false),
    DEFINE_PROP_BOOL("has_rpu", XlnxZynqMPState, has_rpu, false),
    DEFINE_PROP_LINK("ddr-ram", XlnxZynqMPState, ddr_ram, TYPE_MEMORY_REGION,
                     MemoryRegion *),
    DEFINE_PROP_END_OF_LIST()
};

static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(oc);

    dc->props = xlnx_zynqmp_props;
    dc->realize = xlnx_zynqmp_realize;
    /* Reason: Uses serial_hds in realize function, thus can't be used twice */
    dc->user_creatable = false;
}

static const TypeInfo xlnx_zynqmp_type_info = {
    .name = TYPE_XLNX_ZYNQMP,
    .parent = TYPE_DEVICE,
    .instance_size = sizeof(XlnxZynqMPState),
    .instance_init = xlnx_zynqmp_init,
    .class_init = xlnx_zynqmp_class_init,
};

static void xlnx_zynqmp_register_types(void)
{
    type_register_static(&xlnx_zynqmp_type_info);
}

type_init(xlnx_zynqmp_register_types)
Commit	Line	Data
f0a902f7 PC	1	/*
	2	* Xilinx Zynq MPSoC emulation
	3	*
	4	* Copyright (C) 2015 Xilinx Inc
	5	* Written by Peter Crosthwaite <[email protected]>
	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms of the GNU General Public License as published by the
	9	* Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful, but WITHOUT
	13	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	14	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	15	* for more details.
	16	*/
	17
12b16722	18	#include "qemu/osdep.h"
da34e65c	19	#include "qapi/error.h"
4771d756 PB	20	#include "qemu-common.h"
4771d756 PB	21	#include "cpu.h"
f0a902f7	22	#include "hw/arm/xlnx-zynqmp.h"
bf4cb109	23	#include "hw/intc/arm_gic_common.h"
7729e1f4	24	#include "exec/address-spaces.h"
2a0ee672 EI	25	#include "sysemu/kvm.h"
2a0ee672 EI	26	#include "kvm_arm.h"
7729e1f4 PC	27
	28	#define GIC_NUM_SPI_INTR 160
	29
bf4cb109 PC	30	#define ARM_PHYS_TIMER_PPI 30
	31	#define ARM_VIRT_TIMER_PPI 27
	32
20bff213 AF	33	#define GEM_REVISION 0x40070106
20bff213 AF	34
7729e1f4 PC	35	#define GIC_BASE_ADDR 0xf9000000
	36	#define GIC_DIST_ADDR 0xf9010000
	37	#define GIC_CPU_ADDR 0xf9020000
	38
6fdf3282 AF	39	#define SATA_INTR 133
	40	#define SATA_ADDR 0xFD0C0000
	41	#define SATA_NUM_PORTS 2
	42
babc1f30 FI	43	#define QSPI_ADDR 0xff0f0000
	44	#define LQSPI_ADDR 0xc0000000
	45	#define QSPI_IRQ 15
	46
b93dbcdd FK	47	#define DP_ADDR 0xfd4a0000
	48	#define DP_IRQ 113
	49
	50	#define DPDMA_ADDR 0xfd4c0000
	51	#define DPDMA_IRQ 116
	52
0ab7bbc7 AF	53	#define IPI_ADDR 0xFF300000
	54	#define IPI_IRQ 64
	55
08b2f15e AF	56	#define RTC_ADDR 0xffa60000
	57	#define RTC_IRQ 26
	58
b630d3d4 PMD	59	#define SDHCI_CAPABILITIES 0x280737ec6481 /* Datasheet: UG1085 (v1.7) */
b630d3d4 PMD	60
14ca2e46 PC	61	static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
	62	0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000,
	63	};
	64
	65	static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = {
	66	57, 59, 61, 63,
	67	};
	68
3bade2a9 PC	69	static const uint64_t uart_addr[XLNX_ZYNQMP_NUM_UARTS] = {
	70	0xFF000000, 0xFF010000,
	71	};
	72
	73	static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = {
	74	21, 22,
	75	};
	76
33108e9f SPB	77	static const uint64_t sdhci_addr[XLNX_ZYNQMP_NUM_SDHCI] = {
	78	0xFF160000, 0xFF170000,
	79	};
	80
	81	static const int sdhci_intr[XLNX_ZYNQMP_NUM_SDHCI] = {
	82	48, 49,
	83	};
	84
02d07eb4 AF	85	static const uint64_t spi_addr[XLNX_ZYNQMP_NUM_SPIS] = {
	86	0xFF040000, 0xFF050000,
	87	};
	88
	89	static const int spi_intr[XLNX_ZYNQMP_NUM_SPIS] = {
	90	19, 20,
	91	};
	92
7729e1f4 PC	93	typedef struct XlnxZynqMPGICRegion {
	94	int region_index;
	95	uint32_t address;
	96	} XlnxZynqMPGICRegion;
	97
	98	static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = {
	99	{ .region_index = 0, .address = GIC_DIST_ADDR, },
	100	{ .region_index = 1, .address = GIC_CPU_ADDR, },
	101	};
f0a902f7	102
bf4cb109 PC	103	static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index)
	104	{
	105	return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index;
	106	}
	107
6ed92b14 EI	108	static void xlnx_zynqmp_create_rpu(XlnxZynqMPState s, const char boot_cpu,
	109	Error **errp)
	110	{
	111	Error *err = NULL;
	112	int i;
6908ec44	113	int num_rpus = MIN(smp_cpus - XLNX_ZYNQMP_NUM_APU_CPUS, XLNX_ZYNQMP_NUM_RPU_CPUS);
6ed92b14	114
6908ec44	115	for (i = 0; i < num_rpus; i++) {
6ed92b14 EI	116	char *name;
	117
	118	object_initialize(&s->rpu_cpu[i], sizeof(s->rpu_cpu[i]),
	119	"cortex-r5-" TYPE_ARM_CPU);
	120	object_property_add_child(OBJECT(s), "rpu-cpu[*]",
	121	OBJECT(&s->rpu_cpu[i]), &error_abort);
	122
	123	name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i]));
	124	if (strcmp(name, boot_cpu)) {
	125	/* Secondary CPUs start in PSCI powered-down state */
	126	object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true,
	127	"start-powered-off", &error_abort);
	128	} else {
	129	s->boot_cpu_ptr = &s->rpu_cpu[i];
	130	}
	131	g_free(name);
	132
	133	object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "reset-hivecs",
	134	&error_abort);
	135	object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "realized",
	136	&err);
	137	if (err) {
	138	error_propagate(errp, err);
	139	return;
	140	}
	141	}
	142	}
	143
f0a902f7 PC	144	static void xlnx_zynqmp_init(Object *obj)
	145	{
	146	XlnxZynqMPState *s = XLNX_ZYNQMP(obj);
	147	int i;
6908ec44	148	int num_apus = MIN(smp_cpus, XLNX_ZYNQMP_NUM_APU_CPUS);
f0a902f7	149
6908ec44	150	for (i = 0; i < num_apus; i++) {
2e5577bc	151	object_initialize(&s->apu_cpu[i], sizeof(s->apu_cpu[i]),
f0a902f7	152	"cortex-a53-" TYPE_ARM_CPU);
2e5577bc	153	object_property_add_child(obj, "apu-cpu[*]", OBJECT(&s->apu_cpu[i]),
f0a902f7 PC	154	&error_abort);
f0a902f7 PC	155	}
7729e1f4	156
2a0ee672	157	object_initialize(&s->gic, sizeof(s->gic), gic_class_name());
7729e1f4	158	qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default());
14ca2e46 PC	159
	160	for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
	161	object_initialize(&s->gem[i], sizeof(s->gem[i]), TYPE_CADENCE_GEM);
	162	qdev_set_parent_bus(DEVICE(&s->gem[i]), sysbus_get_default());
	163	}
3bade2a9 PC	164
	165	for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
	166	object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_CADENCE_UART);
	167	qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default());
	168	}
6fdf3282 AF	169
	170	object_initialize(&s->sata, sizeof(s->sata), TYPE_SYSBUS_AHCI);
	171	qdev_set_parent_bus(DEVICE(&s->sata), sysbus_get_default());
33108e9f SPB	172
	173	for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
	174	object_initialize(&s->sdhci[i], sizeof(s->sdhci[i]),
	175	TYPE_SYSBUS_SDHCI);
	176	qdev_set_parent_bus(DEVICE(&s->sdhci[i]),
	177	sysbus_get_default());
	178	}
02d07eb4 AF	179
	180	for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
	181	object_initialize(&s->spi[i], sizeof(s->spi[i]),
	182	TYPE_XILINX_SPIPS);
	183	qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
	184	}
b93dbcdd	185
babc1f30 FI	186	object_initialize(&s->qspi, sizeof(s->qspi), TYPE_XLNX_ZYNQMP_QSPIPS);
	187	qdev_set_parent_bus(DEVICE(&s->qspi), sysbus_get_default());
	188
b93dbcdd FK	189	object_initialize(&s->dp, sizeof(s->dp), TYPE_XLNX_DP);
	190	qdev_set_parent_bus(DEVICE(&s->dp), sysbus_get_default());
	191
	192	object_initialize(&s->dpdma, sizeof(s->dpdma), TYPE_XLNX_DPDMA);
	193	qdev_set_parent_bus(DEVICE(&s->dpdma), sysbus_get_default());
0ab7bbc7 AF	194
	195	object_initialize(&s->ipi, sizeof(s->ipi), TYPE_XLNX_ZYNQMP_IPI);
	196	qdev_set_parent_bus(DEVICE(&s->ipi), sysbus_get_default());
08b2f15e AF	197
	198	object_initialize(&s->rtc, sizeof(s->rtc), TYPE_XLNX_ZYNQMP_RTC);
	199	qdev_set_parent_bus(DEVICE(&s->rtc), sysbus_get_default());
f0a902f7 PC	200	}
	201
	202	static void xlnx_zynqmp_realize(DeviceState dev, Error *errp)
	203	{
	204	XlnxZynqMPState *s = XLNX_ZYNQMP(dev);
7729e1f4	205	MemoryRegion *system_memory = get_system_memory();
f0a902f7	206	uint8_t i;
dc3b89ef	207	uint64_t ram_size;
6908ec44	208	int num_apus = MIN(smp_cpus, XLNX_ZYNQMP_NUM_APU_CPUS);
6396a193	209	const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]";
dc3b89ef	210	ram_addr_t ddr_low_size, ddr_high_size;
14ca2e46	211	qemu_irq gic_spi[GIC_NUM_SPI_INTR];
f0a902f7 PC	212	Error *err = NULL;
f0a902f7 PC	213
dc3b89ef AF	214	ram_size = memory_region_size(s->ddr_ram);
	215
	216	/* Create the DDR Memory Regions. User friendly checks should happen at
	217	* the board level
	218	*/
	219	if (ram_size > XLNX_ZYNQMP_MAX_LOW_RAM_SIZE) {
	220	/* The RAM size is above the maximum available for the low DDR.
	221	* Create the high DDR memory region as well.
	222	*/
	223	assert(ram_size <= XLNX_ZYNQMP_MAX_RAM_SIZE);
	224	ddr_low_size = XLNX_ZYNQMP_MAX_LOW_RAM_SIZE;
	225	ddr_high_size = ram_size - XLNX_ZYNQMP_MAX_LOW_RAM_SIZE;
	226
	227	memory_region_init_alias(&s->ddr_ram_high, NULL,
	228	"ddr-ram-high", s->ddr_ram,
	229	ddr_low_size, ddr_high_size);
	230	memory_region_add_subregion(get_system_memory(),
	231	XLNX_ZYNQMP_HIGH_RAM_START,
	232	&s->ddr_ram_high);
	233	} else {
	234	/* RAM must be non-zero */
	235	assert(ram_size);
	236	ddr_low_size = ram_size;
	237	}
	238
	239	memory_region_init_alias(&s->ddr_ram_low, NULL,
	240	"ddr-ram-low", s->ddr_ram,
	241	0, ddr_low_size);
	242	memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram_low);
	243
6675d719 AF	244	/* Create the four OCM banks */
	245	for (i = 0; i < XLNX_ZYNQMP_NUM_OCM_BANKS; i++) {
	246	char *ocm_name = g_strdup_printf("zynqmp.ocm_ram_bank_%d", i);
	247
98a99ce0	248	memory_region_init_ram(&s->ocm_ram[i], NULL, ocm_name,
f8ed85ac	249	XLNX_ZYNQMP_OCM_RAM_SIZE, &error_fatal);
6675d719 AF	250	memory_region_add_subregion(get_system_memory(),
	251	XLNX_ZYNQMP_OCM_RAM_0_ADDRESS +
	252	i * XLNX_ZYNQMP_OCM_RAM_SIZE,
	253	&s->ocm_ram[i]);
	254
	255	g_free(ocm_name);
	256	}
	257
7729e1f4 PC	258	qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32);
7729e1f4 PC	259	qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
6908ec44	260	qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", num_apus);
7729e1f4	261
0776d967	262	/* Realize APUs before realizing the GIC. KVM requires this. */
6908ec44	263	for (i = 0; i < num_apus; i++) {
6396a193	264	char *name;
bf4cb109	265
2e5577bc	266	object_property_set_int(OBJECT(&s->apu_cpu[i]), QEMU_PSCI_CONDUIT_SMC,
f0a902f7	267	"psci-conduit", &error_abort);
6396a193 PC	268
	269	name = object_get_canonical_path_component(OBJECT(&s->apu_cpu[i]));
	270	if (strcmp(name, boot_cpu)) {
f0a902f7	271	/* Secondary CPUs start in PSCI powered-down state */
2e5577bc	272	object_property_set_bool(OBJECT(&s->apu_cpu[i]), true,
f0a902f7	273	"start-powered-off", &error_abort);
6396a193 PC	274	} else {
6396a193 PC	275	s->boot_cpu_ptr = &s->apu_cpu[i];
f0a902f7	276	}
5348c62c	277	g_free(name);
f0a902f7	278
37d42473 EI	279	object_property_set_bool(OBJECT(&s->apu_cpu[i]),
37d42473 EI	280	s->secure, "has_el3", NULL);
c25bd18a	281	object_property_set_bool(OBJECT(&s->apu_cpu[i]),
1946809e	282	s->virt, "has_el2", NULL);
2e5577bc	283	object_property_set_int(OBJECT(&s->apu_cpu[i]), GIC_BASE_ADDR,
e1292517	284	"reset-cbar", &error_abort);
8f2ba1f2 AF	285	object_property_set_int(OBJECT(&s->apu_cpu[i]), num_apus,
8f2ba1f2 AF	286	"core-count", &error_abort);
2e5577bc PC	287	object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, "realized",
2e5577bc PC	288	&err);
f0a902f7	289	if (err) {
24cfc8dc	290	error_propagate(errp, err);
f0a902f7 PC	291	return;
f0a902f7 PC	292	}
0776d967 EI	293	}
	294
	295	object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
	296	if (err) {
	297	error_propagate(errp, err);
	298	return;
	299	}
	300
	301	assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) == XLNX_ZYNQMP_GIC_REGIONS);
	302	for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) {
	303	SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic);
	304	const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i];
	305	MemoryRegion *mr = sysbus_mmio_get_region(gic, r->region_index);
	306	uint32_t addr = r->address;
	307	int j;
	308
	309	sysbus_mmio_map(gic, r->region_index, addr);
	310
	311	for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) {
	312	MemoryRegion *alias = &s->gic_mr[i][j];
	313
	314	addr += XLNX_ZYNQMP_GIC_REGION_SIZE;
	315	memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr,
	316	0, XLNX_ZYNQMP_GIC_REGION_SIZE);
	317	memory_region_add_subregion(system_memory, addr, alias);
	318	}
	319	}
	320
6908ec44	321	for (i = 0; i < num_apus; i++) {
0776d967	322	qemu_irq irq;
7729e1f4 PC	323
7729e1f4 PC	324	sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
2e5577bc PC	325	qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
2e5577bc PC	326	ARM_CPU_IRQ));
bf4cb109 PC	327	irq = qdev_get_gpio_in(DEVICE(&s->gic),
bf4cb109 PC	328	arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI));
2e5577bc	329	qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 0, irq);
bf4cb109 PC	330	irq = qdev_get_gpio_in(DEVICE(&s->gic),
bf4cb109 PC	331	arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI));
2e5577bc	332	qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 1, irq);
f0a902f7	333	}
14ca2e46	334
6ed92b14	335	if (s->has_rpu) {
6908ec44 AF	336	info_report("The 'has_rpu' property is no longer required, to use the "
	337	"RPUs just use -smp 6.");
	338	}
	339
	340	xlnx_zynqmp_create_rpu(s, boot_cpu, &err);
	341	if (err) {
	342	error_propagate(errp, err);
	343	return;
b58850e7 PC	344	}
b58850e7 PC	345
6396a193	346	if (!s->boot_cpu_ptr) {
9af9e0fe	347	error_setg(errp, "ZynqMP Boot cpu %s not found", boot_cpu);
6396a193 PC	348	return;
	349	}
	350
14ca2e46 PC	351	for (i = 0; i < GIC_NUM_SPI_INTR; i++) {
	352	gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i);
	353	}
	354
	355	for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) {
	356	NICInfo *nd = &nd_table[i];
	357
	358	if (nd->used) {
	359	qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
	360	qdev_set_nic_properties(DEVICE(&s->gem[i]), nd);
	361	}
20bff213 AF	362	object_property_set_int(OBJECT(&s->gem[i]), GEM_REVISION, "revision",
20bff213 AF	363	&error_abort);
1372fc0b	364	object_property_set_int(OBJECT(&s->gem[i]), 2, "num-priority-queues",
20bff213	365	&error_abort);
14ca2e46 PC	366	object_property_set_bool(OBJECT(&s->gem[i]), true, "realized", &err);
14ca2e46 PC	367	if (err) {
24cfc8dc	368	error_propagate(errp, err);
14ca2e46 PC	369	return;
	370	}
	371	sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]);
	372	sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0,
	373	gic_spi[gem_intr[i]]);
	374	}
3bade2a9 PC	375
3bade2a9 PC	376	for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) {
4be12ea0	377	qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hds[i]);
3bade2a9 PC	378	object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
3bade2a9 PC	379	if (err) {
24cfc8dc	380	error_propagate(errp, err);
3bade2a9 PC	381	return;
	382	}
	383	sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, uart_addr[i]);
	384	sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
	385	gic_spi[uart_intr[i]]);
	386	}
6fdf3282 AF	387
	388	object_property_set_int(OBJECT(&s->sata), SATA_NUM_PORTS, "num-ports",
	389	&error_abort);
	390	object_property_set_bool(OBJECT(&s->sata), true, "realized", &err);
	391	if (err) {
	392	error_propagate(errp, err);
	393	return;
	394	}
	395
	396	sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SATA_ADDR);
	397	sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]);
33108e9f SPB	398
33108e9f SPB	399	for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
b630d3d4 PMD	400	char *bus_name = g_strdup_printf("sd-bus%d", i);
	401	SysBusDevice *sbd = SYS_BUS_DEVICE(&s->sdhci[i]);
	402	Object *sdhci = OBJECT(&s->sdhci[i]);
	403
	404	/* Compatible with:
	405	* - SD Host Controller Specification Version 3.00
	406	* - SDIO Specification Version 3.0
	407	* - eMMC Specification Version 4.51
	408	*/
	409	object_property_set_uint(sdhci, 3, "sd-spec-version", &err);
	410	object_property_set_uint(sdhci, SDHCI_CAPABILITIES, "capareg", &err);
a01c6554	411	object_property_set_uint(sdhci, UHS_I, "uhs", &err);
b630d3d4	412	object_property_set_bool(sdhci, true, "realized", &err);
33108e9f SPB	413	if (err) {
	414	error_propagate(errp, err);
	415	return;
	416	}
b630d3d4 PMD	417	sysbus_mmio_map(sbd, 0, sdhci_addr[i]);
	418	sysbus_connect_irq(sbd, 0, gic_spi[sdhci_intr[i]]);
	419
eb4f566b	420	/* Alias controller SD bus to the SoC itself */
b630d3d4	421	object_property_add_alias(OBJECT(s), bus_name, sdhci, "sd-bus",
eb4f566b PM	422	&error_abort);
eb4f566b PM	423	g_free(bus_name);
33108e9f	424	}
02d07eb4 AF	425
	426	for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
	427	gchar *bus_name;
	428
	429	object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
	430
	431	sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
	432	sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
	433	gic_spi[spi_intr[i]]);
	434
	435	/* Alias controller SPI bus to the SoC itself */
	436	bus_name = g_strdup_printf("spi%d", i);
	437	object_property_add_alias(OBJECT(s), bus_name,
	438	OBJECT(&s->spi[i]), "spi0",
	439	&error_abort);
b93dbcdd FK	440	g_free(bus_name);
	441	}
	442
babc1f30 FI	443	object_property_set_bool(OBJECT(&s->qspi), true, "realized", &err);
	444	sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 0, QSPI_ADDR);
	445	sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 1, LQSPI_ADDR);
	446	sysbus_connect_irq(SYS_BUS_DEVICE(&s->qspi), 0, gic_spi[QSPI_IRQ]);
	447
	448	for (i = 0; i < XLNX_ZYNQMP_NUM_QSPI_BUS; i++) {
	449	gchar *bus_name;
	450	gchar *target_bus;
	451
	452	/* Alias controller SPI bus to the SoC itself */
	453	bus_name = g_strdup_printf("qspi%d", i);
	454	target_bus = g_strdup_printf("spi%d", i);
	455	object_property_add_alias(OBJECT(s), bus_name,
	456	OBJECT(&s->qspi), target_bus,
	457	&error_abort);
	458	g_free(bus_name);
	459	g_free(target_bus);
	460	}
	461
b93dbcdd FK	462	object_property_set_bool(OBJECT(&s->dp), true, "realized", &err);
	463	if (err) {
	464	error_propagate(errp, err);
	465	return;
	466	}
	467	sysbus_mmio_map(SYS_BUS_DEVICE(&s->dp), 0, DP_ADDR);
	468	sysbus_connect_irq(SYS_BUS_DEVICE(&s->dp), 0, gic_spi[DP_IRQ]);
	469
	470	object_property_set_bool(OBJECT(&s->dpdma), true, "realized", &err);
	471	if (err) {
	472	error_propagate(errp, err);
	473	return;
02d07eb4	474	}
b93dbcdd FK	475	object_property_set_link(OBJECT(&s->dp), OBJECT(&s->dpdma), "dpdma",
	476	&error_abort);
	477	sysbus_mmio_map(SYS_BUS_DEVICE(&s->dpdma), 0, DPDMA_ADDR);
	478	sysbus_connect_irq(SYS_BUS_DEVICE(&s->dpdma), 0, gic_spi[DPDMA_IRQ]);
0ab7bbc7 AF	479
	480	object_property_set_bool(OBJECT(&s->ipi), true, "realized", &err);
	481	if (err) {
	482	error_propagate(errp, err);
	483	return;
	484	}
	485	sysbus_mmio_map(SYS_BUS_DEVICE(&s->ipi), 0, IPI_ADDR);
	486	sysbus_connect_irq(SYS_BUS_DEVICE(&s->ipi), 0, gic_spi[IPI_IRQ]);
08b2f15e AF	487
	488	object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err);
	489	if (err) {
	490	error_propagate(errp, err);
	491	return;
	492	}
	493	sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, RTC_ADDR);
	494	sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, gic_spi[RTC_IRQ]);
f0a902f7 PC	495	}
f0a902f7 PC	496
6396a193 PC	497	static Property xlnx_zynqmp_props[] = {
6396a193 PC	498	DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu),
37d42473	499	DEFINE_PROP_BOOL("secure", XlnxZynqMPState, secure, false),
1946809e	500	DEFINE_PROP_BOOL("virtualization", XlnxZynqMPState, virt, false),
6ed92b14	501	DEFINE_PROP_BOOL("has_rpu", XlnxZynqMPState, has_rpu, false),
c3acfa01 FZ	502	DEFINE_PROP_LINK("ddr-ram", XlnxZynqMPState, ddr_ram, TYPE_MEMORY_REGION,
c3acfa01 FZ	503	MemoryRegion *),
6396a193 PC	504	DEFINE_PROP_END_OF_LIST()
	505	};
	506
f0a902f7 PC	507	static void xlnx_zynqmp_class_init(ObjectClass oc, void data)
	508	{
	509	DeviceClass *dc = DEVICE_CLASS(oc);
	510
6396a193	511	dc->props = xlnx_zynqmp_props;
f0a902f7	512	dc->realize = xlnx_zynqmp_realize;
d8589144 TH	513	/* Reason: Uses serial_hds in realize function, thus can't be used twice */
d8589144 TH	514	dc->user_creatable = false;
f0a902f7 PC	515	}
	516
	517	static const TypeInfo xlnx_zynqmp_type_info = {
	518	.name = TYPE_XLNX_ZYNQMP,
	519	.parent = TYPE_DEVICE,
	520	.instance_size = sizeof(XlnxZynqMPState),
	521	.instance_init = xlnx_zynqmp_init,
	522	.class_init = xlnx_zynqmp_class_init,
	523	};
	524
	525	static void xlnx_zynqmp_register_types(void)
	526	{
	527	type_register_static(&xlnx_zynqmp_type_info);
	528	}
	529
	530	type_init(xlnx_zynqmp_register_types)