[qemu.git] / hw / sun4u.c

/*
 * QEMU Sun4u/Sun4v System Emulator
 *
 * Copyright (c) 2005 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "hw.h"
#include "pci.h"
#include "pc.h"
#include "nvram.h"
#include "fdc.h"
#include "net.h"
#include "qemu-timer.h"
#include "sysemu.h"
#include "boards.h"
#include "firmware_abi.h"

#define KERNEL_LOAD_ADDR     0x00404000
#define CMDLINE_ADDR         0x003ff000
#define INITRD_LOAD_ADDR     0x00300000
#define PROM_SIZE_MAX        (4 * 1024 * 1024)
#define PROM_ADDR            0x1fff0000000ULL
#define PROM_VADDR           0x000ffd00000ULL
#define APB_SPECIAL_BASE     0x1fe00000000ULL
#define APB_MEM_BASE         0x1ff00000000ULL
#define VGA_BASE             (APB_MEM_BASE + 0x400000ULL)
#define PROM_FILENAME        "openbios-sparc64"
#define NVRAM_SIZE           0x2000
#define MAX_IDE_BUS          2

struct hwdef {
    const char * const default_cpu_model;
};

int DMA_get_channel_mode (int nchan)
{
    return 0;
}
int DMA_read_memory (int nchan, void *buf, int pos, int size)
{
    return 0;
}
int DMA_write_memory (int nchan, void *buf, int pos, int size)
{
    return 0;
}
void DMA_hold_DREQ (int nchan) {}
void DMA_release_DREQ (int nchan) {}
void DMA_schedule(int nchan) {}
void DMA_run (void) {}
void DMA_init (int high_page_enable) {}
void DMA_register_channel (int nchan,
                           DMA_transfer_handler transfer_handler,
                           void *opaque)
{
}

static int nvram_boot_set(void *opaque, const char *boot_device)
{
    unsigned int i;
    uint8_t image[sizeof(ohwcfg_v3_t)];
    ohwcfg_v3_t *header = (ohwcfg_v3_t *)&image;
    m48t59_t *nvram = (m48t59_t *)opaque;

    for (i = 0; i < sizeof(image); i++)
        image[i] = m48t59_read(nvram, i) & 0xff;

    pstrcpy((char *)header->boot_devices, sizeof(header->boot_devices),
            boot_device);
    header->nboot_devices = strlen(boot_device) & 0xff;
    header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));

    for (i = 0; i < sizeof(image); i++)
        m48t59_write(nvram, i, image[i]);

    return 0;
}

extern int nographic;

static int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
                                   const char *arch,
                                   ram_addr_t RAM_size,
                                   const char *boot_devices,
                                   uint32_t kernel_image, uint32_t kernel_size,
                                   const char *cmdline,
                                   uint32_t initrd_image, uint32_t initrd_size,
                                   uint32_t NVRAM_image,
                                   int width, int height, int depth,
                                   const uint8_t *macaddr)
{
    unsigned int i;
    uint32_t start, end;
    uint8_t image[0x1ff0];
    ohwcfg_v3_t *header = (ohwcfg_v3_t *)&image;
    struct sparc_arch_cfg *sparc_header;
    struct OpenBIOS_nvpart_v1 *part_header;

    memset(image, '\0', sizeof(image));

    // Try to match PPC NVRAM
    pstrcpy((char *)header->struct_ident, sizeof(header->struct_ident),
            "QEMU_BIOS");
    header->struct_version = cpu_to_be32(3); /* structure v3 */

    header->nvram_size = cpu_to_be16(NVRAM_size);
    header->nvram_arch_ptr = cpu_to_be16(sizeof(ohwcfg_v3_t));
    header->nvram_arch_size = cpu_to_be16(sizeof(struct sparc_arch_cfg));
    pstrcpy((char *)header->arch, sizeof(header->arch), arch);
    header->nb_cpus = smp_cpus & 0xff;
    header->RAM0_base = 0;
    header->RAM0_size = cpu_to_be64((uint64_t)RAM_size);
    pstrcpy((char *)header->boot_devices, sizeof(header->boot_devices),
            boot_devices);
    header->nboot_devices = strlen(boot_devices) & 0xff;
    header->kernel_image = cpu_to_be64((uint64_t)kernel_image);
    header->kernel_size = cpu_to_be64((uint64_t)kernel_size);
    if (cmdline) {
        pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, cmdline);
        header->cmdline = cpu_to_be64((uint64_t)CMDLINE_ADDR);
        header->cmdline_size = cpu_to_be64((uint64_t)strlen(cmdline));
    }
    header->initrd_image = cpu_to_be64((uint64_t)initrd_image);
    header->initrd_size = cpu_to_be64((uint64_t)initrd_size);
    header->NVRAM_image = cpu_to_be64((uint64_t)NVRAM_image);

    header->width = cpu_to_be16(width);
    header->height = cpu_to_be16(height);
    header->depth = cpu_to_be16(depth);
    if (nographic)
        header->graphic_flags = cpu_to_be16(OHW_GF_NOGRAPHICS);

    header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));

    // Architecture specific header
    start = sizeof(ohwcfg_v3_t);
    sparc_header = (struct sparc_arch_cfg *)&image[start];
    sparc_header->valid = 0;
    start += sizeof(struct sparc_arch_cfg);

    // OpenBIOS nvram variables
    // Variable partition
    part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
    part_header->signature = OPENBIOS_PART_SYSTEM;
    pstrcpy(part_header->name, sizeof(part_header->name), "system");

    end = start + sizeof(struct OpenBIOS_nvpart_v1);
    for (i = 0; i < nb_prom_envs; i++)
        end = OpenBIOS_set_var(image, end, prom_envs[i]);

    // End marker
    image[end++] = '\0';

    end = start + ((end - start + 15) & ~15);
    OpenBIOS_finish_partition(part_header, end - start);

    // free partition
    start = end;
    part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
    part_header->signature = OPENBIOS_PART_FREE;
    pstrcpy(part_header->name, sizeof(part_header->name), "free");

    end = 0x1fd0;
    OpenBIOS_finish_partition(part_header, end - start);

    Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80);

    for (i = 0; i < sizeof(image); i++)
        m48t59_write(nvram, i, image[i]);

    qemu_register_boot_set(nvram_boot_set, nvram);

    return 0;
}

void pic_info(void)
{
}

void irq_info(void)
{
}

void qemu_system_powerdown(void)
{
}

static void main_cpu_reset(void *opaque)
{
    CPUState *env = opaque;

    cpu_reset(env);
    ptimer_set_limit(env->tick, 0x7fffffffffffffffULL, 1);
    ptimer_run(env->tick, 0);
    ptimer_set_limit(env->stick, 0x7fffffffffffffffULL, 1);
    ptimer_run(env->stick, 0);
    ptimer_set_limit(env->hstick, 0x7fffffffffffffffULL, 1);
    ptimer_run(env->hstick, 0);
}

static void tick_irq(void *opaque)
{
    CPUState *env = opaque;

    cpu_interrupt(env, CPU_INTERRUPT_TIMER);
}

static void stick_irq(void *opaque)
{
    CPUState *env = opaque;

    cpu_interrupt(env, CPU_INTERRUPT_TIMER);
}

static void hstick_irq(void *opaque)
{
    CPUState *env = opaque;

    cpu_interrupt(env, CPU_INTERRUPT_TIMER);
}

static void dummy_cpu_set_irq(void *opaque, int irq, int level)
{
}

static const int ide_iobase[2] = { 0x1f0, 0x170 };
static const int ide_iobase2[2] = { 0x3f6, 0x376 };
static const int ide_irq[2] = { 14, 15 };

static const int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
static const int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };

static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };

static fdctrl_t *floppy_controller;

static void sun4uv_init(ram_addr_t RAM_size, int vga_ram_size,
                        const char *boot_devices, DisplayState *ds,
                        const char *kernel_filename, const char *kernel_cmdline,
                        const char *initrd_filename, const char *cpu_model,
                        const struct hwdef *hwdef)
{
    CPUState *env;
    char buf[1024];
    m48t59_t *nvram;
    int ret, linux_boot;
    unsigned int i;
    long prom_offset, initrd_size, kernel_size;
    PCIBus *pci_bus;
    QEMUBH *bh;
    qemu_irq *irq;
    int drive_index;
    BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
    BlockDriverState *fd[MAX_FD];

    linux_boot = (kernel_filename != NULL);

    /* init CPUs */
    if (!cpu_model)
        cpu_model = hwdef->default_cpu_model;

    env = cpu_init(cpu_model);
    if (!env) {
        fprintf(stderr, "Unable to find Sparc CPU definition\n");
        exit(1);
    }
    bh = qemu_bh_new(tick_irq, env);
    env->tick = ptimer_init(bh);
    ptimer_set_period(env->tick, 1ULL);

    bh = qemu_bh_new(stick_irq, env);
    env->stick = ptimer_init(bh);
    ptimer_set_period(env->stick, 1ULL);

    bh = qemu_bh_new(hstick_irq, env);
    env->hstick = ptimer_init(bh);
    ptimer_set_period(env->hstick, 1ULL);
    qemu_register_reset(main_cpu_reset, env);
    main_cpu_reset(env);

    /* allocate RAM */
    cpu_register_physical_memory(0, RAM_size, 0);

    prom_offset = RAM_size + vga_ram_size;
    cpu_register_physical_memory(PROM_ADDR,
                                 (PROM_SIZE_MAX + TARGET_PAGE_SIZE) &
                                 TARGET_PAGE_MASK,
                                 prom_offset | IO_MEM_ROM);

    if (bios_name == NULL)
        bios_name = PROM_FILENAME;
    snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
    ret = load_elf(buf, PROM_ADDR - PROM_VADDR, NULL, NULL, NULL);
    if (ret < 0) {
        fprintf(stderr, "qemu: could not load prom '%s'\n",
                buf);
        exit(1);
    }

    kernel_size = 0;
    initrd_size = 0;
    if (linux_boot) {
        /* XXX: put correct offset */
        kernel_size = load_elf(kernel_filename, 0, NULL, NULL, NULL);
        if (kernel_size < 0)
            kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
                                    ram_size - KERNEL_LOAD_ADDR);
        if (kernel_size < 0)
            kernel_size = load_image_targphys(kernel_filename,
                                              KERNEL_LOAD_ADDR,
                                              ram_size - KERNEL_LOAD_ADDR);
        if (kernel_size < 0) {
            fprintf(stderr, "qemu: could not load kernel '%s'\n",
                    kernel_filename);
            exit(1);
        }

        /* load initrd */
        if (initrd_filename) {
            initrd_size = load_image_targphys(initrd_filename,
                                              INITRD_LOAD_ADDR,
                                              ram_size - INITRD_LOAD_ADDR);
            if (initrd_size < 0) {
                fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
                        initrd_filename);
                exit(1);
            }
        }
        if (initrd_size > 0) {
            for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
                if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS
                    stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
                    stl_phys(KERNEL_LOAD_ADDR + i + 20, initrd_size);
                    break;
                }
            }
        }
    }
    pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, NULL);
    isa_mem_base = VGA_BASE;
    pci_cirrus_vga_init(pci_bus, ds, phys_ram_base + RAM_size, RAM_size,
                        vga_ram_size);

    for(i = 0; i < MAX_SERIAL_PORTS; i++) {
        if (serial_hds[i]) {
            serial_init(serial_io[i], NULL/*serial_irq[i]*/, 115200,
                        serial_hds[i]);
        }
    }

    for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
        if (parallel_hds[i]) {
            parallel_init(parallel_io[i], NULL/*parallel_irq[i]*/,
                          parallel_hds[i]);
        }
    }

    for(i = 0; i < nb_nics; i++) {
        if (!nd_table[i].model)
            nd_table[i].model = "ne2k_pci";
        pci_nic_init(pci_bus, &nd_table[i], -1);
    }

    irq = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, 32);
    if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
        fprintf(stderr, "qemu: too many IDE bus\n");
        exit(1);
    }
    for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
        drive_index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS,
                                      i % MAX_IDE_DEVS);
       if (drive_index != -1)
           hd[i] = drives_table[drive_index].bdrv;
       else
           hd[i] = NULL;
    }

    // XXX pci_cmd646_ide_init(pci_bus, hd, 1);
    pci_piix3_ide_init(pci_bus, hd, -1, irq);
    /* FIXME: wire up interrupts.  */
    i8042_init(NULL/*1*/, NULL/*12*/, 0x60);
    for(i = 0; i < MAX_FD; i++) {
        drive_index = drive_get_index(IF_FLOPPY, 0, i);
       if (drive_index != -1)
           fd[i] = drives_table[drive_index].bdrv;
       else
           fd[i] = NULL;
    }
    floppy_controller = fdctrl_init(NULL/*6*/, 2, 0, 0x3f0, fd);
    nvram = m48t59_init(NULL/*8*/, 0, 0x0074, NVRAM_SIZE, 59);
    sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", RAM_size, boot_devices,
                           KERNEL_LOAD_ADDR, kernel_size,
                           kernel_cmdline,
                           INITRD_LOAD_ADDR, initrd_size,
                           /* XXX: need an option to load a NVRAM image */
                           0,
                           graphic_width, graphic_height, graphic_depth,
                           (uint8_t *)&nd_table[0].macaddr);

}

static const struct hwdef hwdefs[] = {
    /* Sun4u generic PC-like machine */
    {
        .default_cpu_model = "TI UltraSparc II",
    },
    /* Sun4v generic PC-like machine */
    {
        .default_cpu_model = "Sun UltraSparc T1",
    },
};

/* Sun4u hardware initialisation */
static void sun4u_init(ram_addr_t RAM_size, int vga_ram_size,
                       const char *boot_devices, DisplayState *ds,
                       const char *kernel_filename, const char *kernel_cmdline,
                       const char *initrd_filename, const char *cpu_model)
{
    sun4uv_init(RAM_size, vga_ram_size, boot_devices, ds, kernel_filename,
                kernel_cmdline, initrd_filename, cpu_model, &hwdefs[0]);
}

/* Sun4v hardware initialisation */
static void sun4v_init(ram_addr_t RAM_size, int vga_ram_size,
                       const char *boot_devices, DisplayState *ds,
                       const char *kernel_filename, const char *kernel_cmdline,
                       const char *initrd_filename, const char *cpu_model)
{
    sun4uv_init(RAM_size, vga_ram_size, boot_devices, ds, kernel_filename,
                kernel_cmdline, initrd_filename, cpu_model, &hwdefs[1]);
}

QEMUMachine sun4u_machine = {
    .name = "sun4u",
    .desc = "Sun4u platform",
    .init = sun4u_init,
    .ram_require = PROM_SIZE_MAX + VGA_RAM_SIZE,
    .nodisk_ok = 1,
};

QEMUMachine sun4v_machine = {
    .name = "sun4v",
    .desc = "Sun4v platform",
    .init = sun4v_init,
    .ram_require = PROM_SIZE_MAX + VGA_RAM_SIZE,
    .nodisk_ok = 1,
};
Commit	Line	Data
3475187d	1	/*
c7ba218d	2	* QEMU Sun4u/Sun4v System Emulator
5fafdf24	3	*
3475187d	4	* Copyright (c) 2005 Fabrice Bellard
5fafdf24	5	*
3475187d FB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
87ecb68b PB	24	#include "hw.h"
	25	#include "pci.h"
	26	#include "pc.h"
	27	#include "nvram.h"
	28	#include "fdc.h"
	29	#include "net.h"
	30	#include "qemu-timer.h"
	31	#include "sysemu.h"
	32	#include "boards.h"
d2c63fc1	33	#include "firmware_abi.h"
3475187d	34
83469015 FB	35	#define KERNEL_LOAD_ADDR 0x00404000
	36	#define CMDLINE_ADDR 0x003ff000
	37	#define INITRD_LOAD_ADDR 0x00300000
ac2e9d66	38	#define PROM_SIZE_MAX (4 * 1024 * 1024)
f930d07e BS	39	#define PROM_ADDR 0x1fff0000000ULL
f930d07e BS	40	#define PROM_VADDR 0x000ffd00000ULL
83469015	41	#define APB_SPECIAL_BASE 0x1fe00000000ULL
f930d07e BS	42	#define APB_MEM_BASE 0x1ff00000000ULL
	43	#define VGA_BASE (APB_MEM_BASE + 0x400000ULL)
	44	#define PROM_FILENAME "openbios-sparc64"
83469015	45	#define NVRAM_SIZE 0x2000
e4bcb14c	46	#define MAX_IDE_BUS 2
3475187d	47
c7ba218d BS	48	struct hwdef {
	49	const char * const default_cpu_model;
	50	};
	51
3475187d FB	52	int DMA_get_channel_mode (int nchan)
	53	{
	54	return 0;
	55	}
	56	int DMA_read_memory (int nchan, void *buf, int pos, int size)
	57	{
	58	return 0;
	59	}
	60	int DMA_write_memory (int nchan, void *buf, int pos, int size)
	61	{
	62	return 0;
	63	}
	64	void DMA_hold_DREQ (int nchan) {}
	65	void DMA_release_DREQ (int nchan) {}
	66	void DMA_schedule(int nchan) {}
	67	void DMA_run (void) {}
	68	void DMA_init (int high_page_enable) {}
	69	void DMA_register_channel (int nchan,
	70	DMA_transfer_handler transfer_handler,
	71	void *opaque)
	72	{
	73	}
	74
81864572 BS	75	static int nvram_boot_set(void opaque, const char boot_device)
	76	{
	77	unsigned int i;
	78	uint8_t image[sizeof(ohwcfg_v3_t)];
	79	ohwcfg_v3_t header = (ohwcfg_v3_t )&image;
	80	m48t59_t nvram = (m48t59_t )opaque;
	81
	82	for (i = 0; i < sizeof(image); i++)
	83	image[i] = m48t59_read(nvram, i) & 0xff;
	84
363a37d5 BS	85	pstrcpy((char *)header->boot_devices, sizeof(header->boot_devices),
363a37d5 BS	86	boot_device);
81864572 BS	87	header->nboot_devices = strlen(boot_device) & 0xff;
	88	header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
	89
	90	for (i = 0; i < sizeof(image); i++)
	91	m48t59_write(nvram, i, image[i]);
	92
	93	return 0;
	94	}
	95
3475187d FB	96	extern int nographic;
3475187d FB	97
d2c63fc1	98	static int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
e7fb1406	99	const char *arch,
77f193da BS	100	ram_addr_t RAM_size,
77f193da BS	101	const char *boot_devices,
d2c63fc1 BS	102	uint32_t kernel_image, uint32_t kernel_size,
	103	const char *cmdline,
	104	uint32_t initrd_image, uint32_t initrd_size,
	105	uint32_t NVRAM_image,
0d31cb99 BS	106	int width, int height, int depth,
0d31cb99 BS	107	const uint8_t *macaddr)
83469015	108	{
66508601 BS	109	unsigned int i;
66508601 BS	110	uint32_t start, end;
d2c63fc1 BS	111	uint8_t image[0x1ff0];
	112	ohwcfg_v3_t header = (ohwcfg_v3_t )&image;
	113	struct sparc_arch_cfg *sparc_header;
	114	struct OpenBIOS_nvpart_v1 *part_header;
	115
	116	memset(image, '\0', sizeof(image));
	117
	118	// Try to match PPC NVRAM
363a37d5 BS	119	pstrcpy((char *)header->struct_ident, sizeof(header->struct_ident),
363a37d5 BS	120	"QEMU_BIOS");
d2c63fc1 BS	121	header->struct_version = cpu_to_be32(3); /* structure v3 */
	122
	123	header->nvram_size = cpu_to_be16(NVRAM_size);
	124	header->nvram_arch_ptr = cpu_to_be16(sizeof(ohwcfg_v3_t));
	125	header->nvram_arch_size = cpu_to_be16(sizeof(struct sparc_arch_cfg));
363a37d5	126	pstrcpy((char *)header->arch, sizeof(header->arch), arch);
d2c63fc1 BS	127	header->nb_cpus = smp_cpus & 0xff;
	128	header->RAM0_base = 0;
	129	header->RAM0_size = cpu_to_be64((uint64_t)RAM_size);
363a37d5 BS	130	pstrcpy((char *)header->boot_devices, sizeof(header->boot_devices),
363a37d5 BS	131	boot_devices);
d2c63fc1 BS	132	header->nboot_devices = strlen(boot_devices) & 0xff;
	133	header->kernel_image = cpu_to_be64((uint64_t)kernel_image);
	134	header->kernel_size = cpu_to_be64((uint64_t)kernel_size);
3475187d	135	if (cmdline) {
293f78bc	136	pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, cmdline);
d2c63fc1 BS	137	header->cmdline = cpu_to_be64((uint64_t)CMDLINE_ADDR);
d2c63fc1 BS	138	header->cmdline_size = cpu_to_be64((uint64_t)strlen(cmdline));
3475187d	139	}
d2c63fc1 BS	140	header->initrd_image = cpu_to_be64((uint64_t)initrd_image);
	141	header->initrd_size = cpu_to_be64((uint64_t)initrd_size);
	142	header->NVRAM_image = cpu_to_be64((uint64_t)NVRAM_image);
	143
	144	header->width = cpu_to_be16(width);
	145	header->height = cpu_to_be16(height);
	146	header->depth = cpu_to_be16(depth);
	147	if (nographic)
	148	header->graphic_flags = cpu_to_be16(OHW_GF_NOGRAPHICS);
83469015	149
d2c63fc1 BS	150	header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
	151
	152	// Architecture specific header
	153	start = sizeof(ohwcfg_v3_t);
	154	sparc_header = (struct sparc_arch_cfg *)&image[start];
	155	sparc_header->valid = 0;
	156	start += sizeof(struct sparc_arch_cfg);
83469015	157
66508601 BS	158	// OpenBIOS nvram variables
66508601 BS	159	// Variable partition
d2c63fc1 BS	160	part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
d2c63fc1 BS	161	part_header->signature = OPENBIOS_PART_SYSTEM;
363a37d5	162	pstrcpy(part_header->name, sizeof(part_header->name), "system");
66508601	163
d2c63fc1	164	end = start + sizeof(struct OpenBIOS_nvpart_v1);
66508601	165	for (i = 0; i < nb_prom_envs; i++)
d2c63fc1 BS	166	end = OpenBIOS_set_var(image, end, prom_envs[i]);
	167
	168	// End marker
	169	image[end++] = '\0';
66508601	170
66508601	171	end = start + ((end - start + 15) & ~15);
d2c63fc1	172	OpenBIOS_finish_partition(part_header, end - start);
66508601 BS	173
	174	// free partition
	175	start = end;
d2c63fc1 BS	176	part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
d2c63fc1 BS	177	part_header->signature = OPENBIOS_PART_FREE;
363a37d5	178	pstrcpy(part_header->name, sizeof(part_header->name), "free");
66508601 BS	179
66508601 BS	180	end = 0x1fd0;
d2c63fc1 BS	181	OpenBIOS_finish_partition(part_header, end - start);
d2c63fc1 BS	182
0d31cb99 BS	183	Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80);
0d31cb99 BS	184
d2c63fc1 BS	185	for (i = 0; i < sizeof(image); i++)
d2c63fc1 BS	186	m48t59_write(nvram, i, image[i]);
66508601	187
81864572 BS	188	qemu_register_boot_set(nvram_boot_set, nvram);
81864572 BS	189
83469015	190	return 0;
3475187d FB	191	}
3475187d FB	192
22548760	193	void pic_info(void)
3475187d FB	194	{
	195	}
	196
22548760	197	void irq_info(void)
3475187d FB	198	{
	199	}
	200
83469015	201	void qemu_system_powerdown(void)
3475187d FB	202	{
	203	}
	204
c68ea704 FB	205	static void main_cpu_reset(void *opaque)
	206	{
	207	CPUState *env = opaque;
20c9f095	208
c68ea704	209	cpu_reset(env);
20c9f095 BS	210	ptimer_set_limit(env->tick, 0x7fffffffffffffffULL, 1);
	211	ptimer_run(env->tick, 0);
	212	ptimer_set_limit(env->stick, 0x7fffffffffffffffULL, 1);
	213	ptimer_run(env->stick, 0);
	214	ptimer_set_limit(env->hstick, 0x7fffffffffffffffULL, 1);
	215	ptimer_run(env->hstick, 0);
	216	}
	217
22548760	218	static void tick_irq(void *opaque)
20c9f095 BS	219	{
	220	CPUState *env = opaque;
	221
	222	cpu_interrupt(env, CPU_INTERRUPT_TIMER);
	223	}
	224
22548760	225	static void stick_irq(void *opaque)
20c9f095 BS	226	{
	227	CPUState *env = opaque;
	228
	229	cpu_interrupt(env, CPU_INTERRUPT_TIMER);
	230	}
	231
22548760	232	static void hstick_irq(void *opaque)
20c9f095 BS	233	{
	234	CPUState *env = opaque;
	235
	236	cpu_interrupt(env, CPU_INTERRUPT_TIMER);
c68ea704 FB	237	}
c68ea704 FB	238
f19e918d BS	239	static void dummy_cpu_set_irq(void *opaque, int irq, int level)
	240	{
	241	}
	242
83469015 FB	243	static const int ide_iobase[2] = { 0x1f0, 0x170 };
	244	static const int ide_iobase2[2] = { 0x3f6, 0x376 };
	245	static const int ide_irq[2] = { 14, 15 };
3475187d	246
83469015 FB	247	static const int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
	248	static const int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
	249
	250	static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
	251	static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
	252
	253	static fdctrl_t *floppy_controller;
3475187d	254
c7ba218d BS	255	static void sun4uv_init(ram_addr_t RAM_size, int vga_ram_size,
	256	const char boot_devices, DisplayState ds,
	257	const char kernel_filename, const char kernel_cmdline,
	258	const char initrd_filename, const char cpu_model,
	259	const struct hwdef *hwdef)
3475187d	260	{
c68ea704	261	CPUState *env;
3475187d	262	char buf[1024];
83469015	263	m48t59_t *nvram;
3475187d FB	264	int ret, linux_boot;
3475187d FB	265	unsigned int i;
83469015 FB	266	long prom_offset, initrd_size, kernel_size;
83469015 FB	267	PCIBus *pci_bus;
20c9f095	268	QEMUBH *bh;
f19e918d	269	qemu_irq *irq;
22548760	270	int drive_index;
e4bcb14c TS	271	BlockDriverState hd[MAX_IDE_BUS MAX_IDE_DEVS];
e4bcb14c TS	272	BlockDriverState *fd[MAX_FD];
3475187d FB	273
	274	linux_boot = (kernel_filename != NULL);
	275
62724a37	276	/* init CPUs */
c7ba218d BS	277	if (!cpu_model)
	278	cpu_model = hwdef->default_cpu_model;
	279
aaed909a FB	280	env = cpu_init(cpu_model);
aaed909a FB	281	if (!env) {
62724a37 BS	282	fprintf(stderr, "Unable to find Sparc CPU definition\n");
	283	exit(1);
	284	}
20c9f095 BS	285	bh = qemu_bh_new(tick_irq, env);
	286	env->tick = ptimer_init(bh);
	287	ptimer_set_period(env->tick, 1ULL);
	288
	289	bh = qemu_bh_new(stick_irq, env);
	290	env->stick = ptimer_init(bh);
	291	ptimer_set_period(env->stick, 1ULL);
	292
	293	bh = qemu_bh_new(hstick_irq, env);
	294	env->hstick = ptimer_init(bh);
	295	ptimer_set_period(env->hstick, 1ULL);
c68ea704	296	qemu_register_reset(main_cpu_reset, env);
20c9f095	297	main_cpu_reset(env);
c68ea704	298
3475187d	299	/* allocate RAM */
22548760	300	cpu_register_physical_memory(0, RAM_size, 0);
3475187d	301
22548760	302	prom_offset = RAM_size + vga_ram_size;
5fafdf24	303	cpu_register_physical_memory(PROM_ADDR,
77f193da BS	304	(PROM_SIZE_MAX + TARGET_PAGE_SIZE) &
77f193da BS	305	TARGET_PAGE_MASK,
b3783731	306	prom_offset \| IO_MEM_ROM);
3475187d	307
1192dad8 JM	308	if (bios_name == NULL)
	309	bios_name = PROM_FILENAME;
	310	snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
f19e918d	311	ret = load_elf(buf, PROM_ADDR - PROM_VADDR, NULL, NULL, NULL);
3475187d	312	if (ret < 0) {
f930d07e BS	313	fprintf(stderr, "qemu: could not load prom '%s'\n",
	314	buf);
	315	exit(1);
3475187d	316	}
3475187d FB	317
3475187d FB	318	kernel_size = 0;
83469015	319	initrd_size = 0;
3475187d	320	if (linux_boot) {
b3783731	321	/* XXX: put correct offset */
74287114	322	kernel_size = load_elf(kernel_filename, 0, NULL, NULL, NULL);
3475187d	323	if (kernel_size < 0)
293f78bc BS	324	kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
293f78bc BS	325	ram_size - KERNEL_LOAD_ADDR);
f930d07e	326	if (kernel_size < 0)
293f78bc BS	327	kernel_size = load_image_targphys(kernel_filename,
	328	KERNEL_LOAD_ADDR,
	329	ram_size - KERNEL_LOAD_ADDR);
3475187d	330	if (kernel_size < 0) {
5fafdf24	331	fprintf(stderr, "qemu: could not load kernel '%s'\n",
3475187d	332	kernel_filename);
f930d07e	333	exit(1);
3475187d FB	334	}
	335
	336	/* load initrd */
3475187d	337	if (initrd_filename) {
293f78bc BS	338	initrd_size = load_image_targphys(initrd_filename,
	339	INITRD_LOAD_ADDR,
	340	ram_size - INITRD_LOAD_ADDR);
3475187d	341	if (initrd_size < 0) {
5fafdf24	342	fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
3475187d FB	343	initrd_filename);
	344	exit(1);
	345	}
	346	}
	347	if (initrd_size > 0) {
f930d07e	348	for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
293f78bc BS	349	if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS
	350	stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
	351	stl_phys(KERNEL_LOAD_ADDR + i + 20, initrd_size);
f930d07e BS	352	break;
	353	}
	354	}
3475187d FB	355	}
3475187d FB	356	}
502a5395	357	pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, NULL);
83469015	358	isa_mem_base = VGA_BASE;
77f193da BS	359	pci_cirrus_vga_init(pci_bus, ds, phys_ram_base + RAM_size, RAM_size,
77f193da BS	360	vga_ram_size);
83469015 FB	361
	362	for(i = 0; i < MAX_SERIAL_PORTS; i++) {
	363	if (serial_hds[i]) {
cbf5c748 BS	364	serial_init(serial_io[i], NULL/serial_irq[i]/, 115200,
cbf5c748 BS	365	serial_hds[i]);
83469015 FB	366	}
	367	}
	368
	369	for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
	370	if (parallel_hds[i]) {
77f193da BS	371	parallel_init(parallel_io[i], NULL/parallel_irq[i]/,
77f193da BS	372	parallel_hds[i]);
83469015 FB	373	}
	374	}
	375
	376	for(i = 0; i < nb_nics; i++) {
a41b2ff2 PB	377	if (!nd_table[i].model)
a41b2ff2 PB	378	nd_table[i].model = "ne2k_pci";
f930d07e	379	pci_nic_init(pci_bus, &nd_table[i], -1);
83469015 FB	380	}
83469015 FB	381
f19e918d	382	irq = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, 32);
e4bcb14c TS	383	if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
	384	fprintf(stderr, "qemu: too many IDE bus\n");
	385	exit(1);
	386	}
	387	for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
22548760 BS	388	drive_index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS,
	389	i % MAX_IDE_DEVS);
	390	if (drive_index != -1)
	391	hd[i] = drives_table[drive_index].bdrv;
e4bcb14c TS	392	else
	393	hd[i] = NULL;
	394	}
	395
	396	// XXX pci_cmd646_ide_init(pci_bus, hd, 1);
	397	pci_piix3_ide_init(pci_bus, hd, -1, irq);
d537cf6c PB	398	/* FIXME: wire up interrupts. */
d537cf6c PB	399	i8042_init(NULL/1/, NULL/12/, 0x60);
e4bcb14c	400	for(i = 0; i < MAX_FD; i++) {
22548760 BS	401	drive_index = drive_get_index(IF_FLOPPY, 0, i);
	402	if (drive_index != -1)
	403	fd[i] = drives_table[drive_index].bdrv;
e4bcb14c TS	404	else
	405	fd[i] = NULL;
	406	}
	407	floppy_controller = fdctrl_init(NULL/6/, 2, 0, 0x3f0, fd);
d537cf6c	408	nvram = m48t59_init(NULL/8/, 0, 0x0074, NVRAM_SIZE, 59);
22548760	409	sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", RAM_size, boot_devices,
0d31cb99 BS	410	KERNEL_LOAD_ADDR, kernel_size,
	411	kernel_cmdline,
	412	INITRD_LOAD_ADDR, initrd_size,
	413	/* XXX: need an option to load a NVRAM image */
	414	0,
	415	graphic_width, graphic_height, graphic_depth,
	416	(uint8_t *)&nd_table[0].macaddr);
83469015	417
3475187d FB	418	}
3475187d FB	419
c7ba218d BS	420	static const struct hwdef hwdefs[] = {
	421	/* Sun4u generic PC-like machine */
	422	{
	423	.default_cpu_model = "TI UltraSparc II",
	424	},
	425	/* Sun4v generic PC-like machine */
	426	{
	427	.default_cpu_model = "Sun UltraSparc T1",
	428	},
	429	};
	430
	431	/* Sun4u hardware initialisation */
	432	static void sun4u_init(ram_addr_t RAM_size, int vga_ram_size,
	433	const char boot_devices, DisplayState ds,
	434	const char kernel_filename, const char kernel_cmdline,
	435	const char initrd_filename, const char cpu_model)
	436	{
	437	sun4uv_init(RAM_size, vga_ram_size, boot_devices, ds, kernel_filename,
	438	kernel_cmdline, initrd_filename, cpu_model, &hwdefs[0]);
	439	}
	440
	441	/* Sun4v hardware initialisation */
	442	static void sun4v_init(ram_addr_t RAM_size, int vga_ram_size,
	443	const char boot_devices, DisplayState ds,
	444	const char kernel_filename, const char kernel_cmdline,
	445	const char initrd_filename, const char cpu_model)
	446	{
	447	sun4uv_init(RAM_size, vga_ram_size, boot_devices, ds, kernel_filename,
	448	kernel_cmdline, initrd_filename, cpu_model, &hwdefs[1]);
	449	}
	450
3475187d	451	QEMUMachine sun4u_machine = {
66de733b BS	452	.name = "sun4u",
	453	.desc = "Sun4u platform",
	454	.init = sun4u_init,
	455	.ram_require = PROM_SIZE_MAX + VGA_RAM_SIZE,
f88e4b91	456	.nodisk_ok = 1,
3475187d	457	};
c7ba218d BS	458
c7ba218d BS	459	QEMUMachine sun4v_machine = {
66de733b BS	460	.name = "sun4v",
	461	.desc = "Sun4v platform",
	462	.init = sun4v_init,
	463	.ram_require = PROM_SIZE_MAX + VGA_RAM_SIZE,
f88e4b91	464	.nodisk_ok = 1,
c7ba218d	465	};