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[qemu.git] / hw / net / pcnet.c
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e3c2613f
FB		 1/*
2 * QEMU AMD PC-Net II (Am79C970A) emulation
5fafdf24 3 *
e3c2613f 4 * Copyright (c) 2004 Antony T Curtis
5fafdf24 5 *
e3c2613f
FB		 6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
5fafdf24 24
e3c2613f
FB		 25/* This software was written to be compatible with the specification:
26 * AMD Am79C970A PCnet-PCI II Ethernet Controller Data-Sheet
27 * AMD Publication# 19436 Rev:E Amendment/0 Issue Date: June 2000
28 */
5fafdf24 29
91cc0295
FB		 30/*
31 * On Sparc32, this is the Lance (Am7990) part of chip STP2000 (Master I/O), also
32 * produced as NCR89C100. See
33 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
34 * and
35 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR92C990.txt
36 */
37
83c9f4ca 38#include "hw/qdev.h"
1422e32d 39#include "net/net.h"
1de7afc9
PB		 40#include "qemu/timer.h"
41#include "qemu/sockets.h"
9c17d615 42#include "sysemu/sysemu.h"
e3c2613f 43
47b43a1f 44#include "pcnet.h"
94e1a912 45
e3c2613f
FB		 46//#define PCNET_DEBUG
47//#define PCNET_DEBUG_IO
48//#define PCNET_DEBUG_BCR
49//#define PCNET_DEBUG_CSR
50//#define PCNET_DEBUG_RMD
51//#define PCNET_DEBUG_TMD
52//#define PCNET_DEBUG_MATCH
53
54
219fb125
FB		 55struct qemu_ether_header {
56 uint8_t ether_dhost[6];
57 uint8_t ether_shost[6];
58 uint16_t ether_type;
59};
60
e3c2613f
FB		 61#define CSR_INIT(S) !!(((S)->csr[0])&0x0001)
62#define CSR_STRT(S) !!(((S)->csr[0])&0x0002)
63#define CSR_STOP(S) !!(((S)->csr[0])&0x0004)
64#define CSR_TDMD(S) !!(((S)->csr[0])&0x0008)
65#define CSR_TXON(S) !!(((S)->csr[0])&0x0010)
66#define CSR_RXON(S) !!(((S)->csr[0])&0x0020)
67#define CSR_INEA(S) !!(((S)->csr[0])&0x0040)
9b94dc32 68#define CSR_BSWP(S) !!(((S)->csr[3])&0x0004)
e3c2613f
FB		 69#define CSR_LAPPEN(S) !!(((S)->csr[3])&0x0020)
70#define CSR_DXSUFLO(S) !!(((S)->csr[3])&0x0040)
71#define CSR_ASTRP_RCV(S) !!(((S)->csr[4])&0x0800)
72#define CSR_DPOLL(S) !!(((S)->csr[4])&0x1000)
73#define CSR_SPND(S) !!(((S)->csr[5])&0x0001)
74#define CSR_LTINTEN(S) !!(((S)->csr[5])&0x4000)
75#define CSR_TOKINTD(S) !!(((S)->csr[5])&0x8000)
76#define CSR_DRX(S) !!(((S)->csr[15])&0x0001)
77#define CSR_DTX(S) !!(((S)->csr[15])&0x0002)
78#define CSR_LOOP(S) !!(((S)->csr[15])&0x0004)
89b190a2 79#define CSR_DXMTFCS(S) !!(((S)->csr[15])&0x0008)
ef45c914 80#define CSR_INTL(S) !!(((S)->csr[15])&0x0040)
e3c2613f
FB		 81#define CSR_DRCVPA(S) !!(((S)->csr[15])&0x2000)
82#define CSR_DRCVBC(S) !!(((S)->csr[15])&0x4000)
83#define CSR_PROM(S) !!(((S)->csr[15])&0x8000)
84
85#define CSR_CRBC(S) ((S)->csr[40])
86#define CSR_CRST(S) ((S)->csr[41])
87#define CSR_CXBC(S) ((S)->csr[42])
88#define CSR_CXST(S) ((S)->csr[43])
89#define CSR_NRBC(S) ((S)->csr[44])
90#define CSR_NRST(S) ((S)->csr[45])
91#define CSR_POLL(S) ((S)->csr[46])
92#define CSR_PINT(S) ((S)->csr[47])
93#define CSR_RCVRC(S) ((S)->csr[72])
94#define CSR_XMTRC(S) ((S)->csr[74])
95#define CSR_RCVRL(S) ((S)->csr[76])
96#define CSR_XMTRL(S) ((S)->csr[78])
97#define CSR_MISSC(S) ((S)->csr[112])
98
366c9332
MB		 99#define CSR_IADR(S) ((S)->csr[ 1] | ((uint32_t)(S)->csr[ 2] << 16))
100#define CSR_CRBA(S) ((S)->csr[18] | ((uint32_t)(S)->csr[19] << 16))
101#define CSR_CXBA(S) ((S)->csr[20] | ((uint32_t)(S)->csr[21] << 16))
102#define CSR_NRBA(S) ((S)->csr[22] | ((uint32_t)(S)->csr[23] << 16))
103#define CSR_BADR(S) ((S)->csr[24] | ((uint32_t)(S)->csr[25] << 16))
104#define CSR_NRDA(S) ((S)->csr[26] | ((uint32_t)(S)->csr[27] << 16))
105#define CSR_CRDA(S) ((S)->csr[28] | ((uint32_t)(S)->csr[29] << 16))
106#define CSR_BADX(S) ((S)->csr[30] | ((uint32_t)(S)->csr[31] << 16))
107#define CSR_NXDA(S) ((S)->csr[32] | ((uint32_t)(S)->csr[33] << 16))
108#define CSR_CXDA(S) ((S)->csr[34] | ((uint32_t)(S)->csr[35] << 16))
109#define CSR_NNRD(S) ((S)->csr[36] | ((uint32_t)(S)->csr[37] << 16))
110#define CSR_NNXD(S) ((S)->csr[38] | ((uint32_t)(S)->csr[39] << 16))
111#define CSR_PXDA(S) ((S)->csr[60] | ((uint32_t)(S)->csr[61] << 16))
112#define CSR_NXBA(S) ((S)->csr[64] | ((uint32_t)(S)->csr[65] << 16))
e3c2613f
FB		 113
114#define PHYSADDR(S,A) \
366c9332 115 (BCR_SSIZE32(S) ? (A) : (A) | ((0xff00 & (uint32_t)(S)->csr[2])<<16))
e3c2613f
FB		 116
117struct pcnet_initblk16 {
118 uint16_t mode;
91cc0295
FB		 119 uint16_t padr[3];
120 uint16_t ladrf[4];
121 uint32_t rdra;
122 uint32_t tdra;
e3c2613f
FB		 123};
124
125struct pcnet_initblk32 {
126 uint16_t mode;
91cc0295
FB		 127 uint8_t rlen;
128 uint8_t tlen;
129 uint16_t padr[3];
e3c2613f 130 uint16_t _res;
91cc0295 131 uint16_t ladrf[4];
e3c2613f
FB		 132 uint32_t rdra;
133 uint32_t tdra;
134};
135
136struct pcnet_TMD {
6d2980f5
TS		 137 uint32_t tbadr;
138 int16_t length;
139 int16_t status;
140 uint32_t misc;
141 uint32_t res;
e3c2613f
FB		 142};
143
6d2980f5
TS		 144#define TMDL_BCNT_MASK 0x0fff
145#define TMDL_BCNT_SH 0
146#define TMDL_ONES_MASK 0xf000
147#define TMDL_ONES_SH 12
148
149#define TMDS_BPE_MASK 0x0080
150#define TMDS_BPE_SH 7
151#define TMDS_ENP_MASK 0x0100
152#define TMDS_ENP_SH 8
153#define TMDS_STP_MASK 0x0200
154#define TMDS_STP_SH 9
155#define TMDS_DEF_MASK 0x0400
156#define TMDS_DEF_SH 10
157#define TMDS_ONE_MASK 0x0800
158#define TMDS_ONE_SH 11
159#define TMDS_LTINT_MASK 0x1000
160#define TMDS_LTINT_SH 12
161#define TMDS_NOFCS_MASK 0x2000
162#define TMDS_NOFCS_SH 13
89b190a2
AJ		 163#define TMDS_ADDFCS_MASK TMDS_NOFCS_MASK
164#define TMDS_ADDFCS_SH TMDS_NOFCS_SH
6d2980f5
TS		 165#define TMDS_ERR_MASK 0x4000
166#define TMDS_ERR_SH 14
167#define TMDS_OWN_MASK 0x8000
168#define TMDS_OWN_SH 15
169
170#define TMDM_TRC_MASK 0x0000000f
171#define TMDM_TRC_SH 0
172#define TMDM_TDR_MASK 0x03ff0000
173#define TMDM_TDR_SH 16
174#define TMDM_RTRY_MASK 0x04000000
175#define TMDM_RTRY_SH 26
176#define TMDM_LCAR_MASK 0x08000000
177#define TMDM_LCAR_SH 27
178#define TMDM_LCOL_MASK 0x10000000
179#define TMDM_LCOL_SH 28
180#define TMDM_EXDEF_MASK 0x20000000
181#define TMDM_EXDEF_SH 29
182#define TMDM_UFLO_MASK 0x40000000
183#define TMDM_UFLO_SH 30
184#define TMDM_BUFF_MASK 0x80000000
185#define TMDM_BUFF_SH 31
186
e3c2613f 187struct pcnet_RMD {
6d2980f5
TS		 188 uint32_t rbadr;
189 int16_t buf_length;
190 int16_t status;
191 uint32_t msg_length;
192 uint32_t res;
e3c2613f
FB		 193};
194
6d2980f5
TS		 195#define RMDL_BCNT_MASK 0x0fff
196#define RMDL_BCNT_SH 0
197#define RMDL_ONES_MASK 0xf000
198#define RMDL_ONES_SH 12
199
200#define RMDS_BAM_MASK 0x0010
201#define RMDS_BAM_SH 4
202#define RMDS_LFAM_MASK 0x0020
203#define RMDS_LFAM_SH 5
204#define RMDS_PAM_MASK 0x0040
205#define RMDS_PAM_SH 6
206#define RMDS_BPE_MASK 0x0080
207#define RMDS_BPE_SH 7
208#define RMDS_ENP_MASK 0x0100
209#define RMDS_ENP_SH 8
210#define RMDS_STP_MASK 0x0200
211#define RMDS_STP_SH 9
212#define RMDS_BUFF_MASK 0x0400
213#define RMDS_BUFF_SH 10
214#define RMDS_CRC_MASK 0x0800
215#define RMDS_CRC_SH 11
216#define RMDS_OFLO_MASK 0x1000
217#define RMDS_OFLO_SH 12
218#define RMDS_FRAM_MASK 0x2000
219#define RMDS_FRAM_SH 13
220#define RMDS_ERR_MASK 0x4000
221#define RMDS_ERR_SH 14
222#define RMDS_OWN_MASK 0x8000
223#define RMDS_OWN_SH 15
224
225#define RMDM_MCNT_MASK 0x00000fff
226#define RMDM_MCNT_SH 0
227#define RMDM_ZEROS_MASK 0x0000f000
228#define RMDM_ZEROS_SH 12
229#define RMDM_RPC_MASK 0x00ff0000
230#define RMDM_RPC_SH 16
231#define RMDM_RCC_MASK 0xff000000
232#define RMDM_RCC_SH 24
233
234#define SET_FIELD(regp, name, field, value) \
235 (*(regp) = (*(regp) & ~(name ## _ ## field ## _MASK)) \
236 | ((value) << name ## _ ## field ## _SH))
237
238#define GET_FIELD(reg, name, field) \
239 (((reg) & name ## _ ## field ## _MASK) >> name ## _ ## field ## _SH)
240
241#define PRINT_TMD(T) printf( \
242 "TMD0 : TBADR=0x%08x\n" \
e3c2613f
FB		 243 "TMD1 : OWN=%d, ERR=%d, FCS=%d, LTI=%d, " \
244 "ONE=%d, DEF=%d, STP=%d, ENP=%d,\n" \
245 " BPE=%d, BCNT=%d\n" \
246 "TMD2 : BUF=%d, UFL=%d, EXD=%d, LCO=%d, " \
247 "LCA=%d, RTR=%d,\n" \
248 " TDR=%d, TRC=%d\n", \
6d2980f5
TS		 249 (T)->tbadr, \
250 GET_FIELD((T)->status, TMDS, OWN), \
251 GET_FIELD((T)->status, TMDS, ERR), \
252 GET_FIELD((T)->status, TMDS, NOFCS), \
253 GET_FIELD((T)->status, TMDS, LTINT), \
254 GET_FIELD((T)->status, TMDS, ONE), \
255 GET_FIELD((T)->status, TMDS, DEF), \
256 GET_FIELD((T)->status, TMDS, STP), \
257 GET_FIELD((T)->status, TMDS, ENP), \
258 GET_FIELD((T)->status, TMDS, BPE), \
259 4096-GET_FIELD((T)->length, TMDL, BCNT), \
260 GET_FIELD((T)->misc, TMDM, BUFF), \
261 GET_FIELD((T)->misc, TMDM, UFLO), \
262 GET_FIELD((T)->misc, TMDM, EXDEF), \
263 GET_FIELD((T)->misc, TMDM, LCOL), \
264 GET_FIELD((T)->misc, TMDM, LCAR), \
265 GET_FIELD((T)->misc, TMDM, RTRY), \
266 GET_FIELD((T)->misc, TMDM, TDR), \
267 GET_FIELD((T)->misc, TMDM, TRC))
268
269#define PRINT_RMD(R) printf( \
270 "RMD0 : RBADR=0x%08x\n" \
e3c2613f
FB		 271 "RMD1 : OWN=%d, ERR=%d, FRAM=%d, OFLO=%d, " \
272 "CRC=%d, BUFF=%d, STP=%d, ENP=%d,\n " \
6d2980f5 273 "BPE=%d, PAM=%d, LAFM=%d, BAM=%d, ONES=%d, BCNT=%d\n" \
e3c2613f 274 "RMD2 : RCC=%d, RPC=%d, MCNT=%d, ZEROS=%d\n", \
6d2980f5
TS		 275 (R)->rbadr, \
276 GET_FIELD((R)->status, RMDS, OWN), \
277 GET_FIELD((R)->status, RMDS, ERR), \
278 GET_FIELD((R)->status, RMDS, FRAM), \
279 GET_FIELD((R)->status, RMDS, OFLO), \
280 GET_FIELD((R)->status, RMDS, CRC), \
281 GET_FIELD((R)->status, RMDS, BUFF), \
282 GET_FIELD((R)->status, RMDS, STP), \
283 GET_FIELD((R)->status, RMDS, ENP), \
284 GET_FIELD((R)->status, RMDS, BPE), \
285 GET_FIELD((R)->status, RMDS, PAM), \
286 GET_FIELD((R)->status, RMDS, LFAM), \
287 GET_FIELD((R)->status, RMDS, BAM), \
288 GET_FIELD((R)->buf_length, RMDL, ONES), \
289 4096-GET_FIELD((R)->buf_length, RMDL, BCNT), \
290 GET_FIELD((R)->msg_length, RMDM, RCC), \
291 GET_FIELD((R)->msg_length, RMDM, RPC), \
292 GET_FIELD((R)->msg_length, RMDM, MCNT), \
293 GET_FIELD((R)->msg_length, RMDM, ZEROS))
294
295static inline void pcnet_tmd_load(PCNetState *s, struct pcnet_TMD *tmd,
a8170e5e 296 hwaddr addr)
e3c2613f 297{
6d2980f5
TS		 298 if (!BCR_SSIZE32(s)) {
299 struct {
300 uint32_t tbadr;
301 int16_t length;
302 int16_t status;
303 } xda;
304 s->phys_mem_read(s->dma_opaque, addr, (void *)&xda, sizeof(xda), 0);
305 tmd->tbadr = le32_to_cpu(xda.tbadr) & 0xffffff;
306 tmd->length = le16_to_cpu(xda.length);
307 tmd->status = (le32_to_cpu(xda.tbadr) >> 16) & 0xff00;
308 tmd->misc = le16_to_cpu(xda.status) << 16;
309 tmd->res = 0;
03c18475 310 } else {
6d2980f5
TS		 311 s->phys_mem_read(s->dma_opaque, addr, (void *)tmd, sizeof(*tmd), 0);
312 le32_to_cpus(&tmd->tbadr);
69b34976
TS		 313 le16_to_cpus((uint16_t *)&tmd->length);
314 le16_to_cpus((uint16_t *)&tmd->status);
6d2980f5
TS		 315 le32_to_cpus(&tmd->misc);
316 le32_to_cpus(&tmd->res);
317 if (BCR_SWSTYLE(s) == 3) {
318 uint32_t tmp = tmd->tbadr;
319 tmd->tbadr = tmd->misc;
320 tmd->misc = tmp;
03c18475 321 }
e3c2613f
FB		 322 }
323}
324
6d2980f5 325static inline void pcnet_tmd_store(PCNetState *s, const struct pcnet_TMD *tmd,
a8170e5e 326 hwaddr addr)
e3c2613f 327{
6d2980f5
TS		 328 if (!BCR_SSIZE32(s)) {
329 struct {
330 uint32_t tbadr;
331 int16_t length;
332 int16_t status;
333 } xda;
334 xda.tbadr = cpu_to_le32((tmd->tbadr & 0xffffff) |
335 ((tmd->status & 0xff00) << 16));
336 xda.length = cpu_to_le16(tmd->length);
337 xda.status = cpu_to_le16(tmd->misc >> 16);
338 s->phys_mem_write(s->dma_opaque, addr, (void *)&xda, sizeof(xda), 0);
03c18475 339 } else {
6d2980f5
TS		 340 struct {
341 uint32_t tbadr;
342 int16_t length;
343 int16_t status;
344 uint32_t misc;
345 uint32_t res;
346 } xda;
347 xda.tbadr = cpu_to_le32(tmd->tbadr);
348 xda.length = cpu_to_le16(tmd->length);
349 xda.status = cpu_to_le16(tmd->status);
350 xda.misc = cpu_to_le32(tmd->misc);
351 xda.res = cpu_to_le32(tmd->res);
352 if (BCR_SWSTYLE(s) == 3) {
353 uint32_t tmp = xda.tbadr;
354 xda.tbadr = xda.misc;
355 xda.misc = tmp;
03c18475 356 }
6d2980f5 357 s->phys_mem_write(s->dma_opaque, addr, (void *)&xda, sizeof(xda), 0);
e3c2613f
FB		 358 }
359}
360
6d2980f5 361static inline void pcnet_rmd_load(PCNetState *s, struct pcnet_RMD *rmd,
a8170e5e 362 hwaddr addr)
e3c2613f 363{
6d2980f5
TS		 364 if (!BCR_SSIZE32(s)) {
365 struct {
366 uint32_t rbadr;
367 int16_t buf_length;
368 int16_t msg_length;
369 } rda;
370 s->phys_mem_read(s->dma_opaque, addr, (void *)&rda, sizeof(rda), 0);
371 rmd->rbadr = le32_to_cpu(rda.rbadr) & 0xffffff;
372 rmd->buf_length = le16_to_cpu(rda.buf_length);
373 rmd->status = (le32_to_cpu(rda.rbadr) >> 16) & 0xff00;
374 rmd->msg_length = le16_to_cpu(rda.msg_length);
375 rmd->res = 0;
03c18475 376 } else {
6d2980f5
TS		 377 s->phys_mem_read(s->dma_opaque, addr, (void *)rmd, sizeof(*rmd), 0);
378 le32_to_cpus(&rmd->rbadr);
69b34976
TS		 379 le16_to_cpus((uint16_t *)&rmd->buf_length);
380 le16_to_cpus((uint16_t *)&rmd->status);
6d2980f5
TS		 381 le32_to_cpus(&rmd->msg_length);
382 le32_to_cpus(&rmd->res);
383 if (BCR_SWSTYLE(s) == 3) {
384 uint32_t tmp = rmd->rbadr;
385 rmd->rbadr = rmd->msg_length;
386 rmd->msg_length = tmp;
03c18475 387 }
e3c2613f
FB		 388 }
389}
390
6d2980f5 391static inline void pcnet_rmd_store(PCNetState *s, struct pcnet_RMD *rmd,
a8170e5e 392 hwaddr addr)
e3c2613f 393{
6d2980f5
TS		 394 if (!BCR_SSIZE32(s)) {
395 struct {
396 uint32_t rbadr;
397 int16_t buf_length;
398 int16_t msg_length;
399 } rda;
400 rda.rbadr = cpu_to_le32((rmd->rbadr & 0xffffff) |
401 ((rmd->status & 0xff00) << 16));
402 rda.buf_length = cpu_to_le16(rmd->buf_length);
403 rda.msg_length = cpu_to_le16(rmd->msg_length);
404 s->phys_mem_write(s->dma_opaque, addr, (void *)&rda, sizeof(rda), 0);
03c18475 405 } else {
6d2980f5
TS		 406 struct {
407 uint32_t rbadr;
408 int16_t buf_length;
409 int16_t status;
410 uint32_t msg_length;
411 uint32_t res;
412 } rda;
413 rda.rbadr = cpu_to_le32(rmd->rbadr);
414 rda.buf_length = cpu_to_le16(rmd->buf_length);
415 rda.status = cpu_to_le16(rmd->status);
416 rda.msg_length = cpu_to_le32(rmd->msg_length);
417 rda.res = cpu_to_le32(rmd->res);
418 if (BCR_SWSTYLE(s) == 3) {
419 uint32_t tmp = rda.rbadr;
420 rda.rbadr = rda.msg_length;
421 rda.msg_length = tmp;
e3c2613f 422 }
6d2980f5 423 s->phys_mem_write(s->dma_opaque, addr, (void *)&rda, sizeof(rda), 0);
e3c2613f
FB		 424 }
425}
426
427
428#define TMDLOAD(TMD,ADDR) pcnet_tmd_load(s,TMD,ADDR)
429
430#define TMDSTORE(TMD,ADDR) pcnet_tmd_store(s,TMD,ADDR)
431
432#define RMDLOAD(RMD,ADDR) pcnet_rmd_load(s,RMD,ADDR)
433
434#define RMDSTORE(RMD,ADDR) pcnet_rmd_store(s,RMD,ADDR)
435
436#if 1
437
438#define CHECK_RMD(ADDR,RES) do { \
439 struct pcnet_RMD rmd; \
440 RMDLOAD(&rmd,(ADDR)); \
6d2980f5
TS		 441 (RES) |= (GET_FIELD(rmd.buf_length, RMDL, ONES) != 15) \
442 || (GET_FIELD(rmd.msg_length, RMDM, ZEROS) != 0); \
e3c2613f
FB		 443} while (0)
444
445#define CHECK_TMD(ADDR,RES) do { \
446 struct pcnet_TMD tmd; \
447 TMDLOAD(&tmd,(ADDR)); \
6d2980f5 448 (RES) |= (GET_FIELD(tmd.length, TMDL, ONES) != 15); \
e3c2613f
FB		 449} while (0)
450
451#else
452
453#define CHECK_RMD(ADDR,RES) do { \
454 switch (BCR_SWSTYLE(s)) { \
455 case 0x00: \
456 do { \
457 uint16_t rda[4]; \
6d2980f5
TS		 458 s->phys_mem_read(s->dma_opaque, (ADDR), \
459 (void *)&rda[0], sizeof(rda), 0); \
e3c2613f
FB		 460 (RES) |= (rda[2] & 0xf000)!=0xf000; \
461 (RES) |= (rda[3] & 0xf000)!=0x0000; \
462 } while (0); \
463 break; \
464 case 0x01: \
465 case 0x02: \
466 do { \
467 uint32_t rda[4]; \
6d2980f5 468 s->phys_mem_read(s->dma_opaque, (ADDR), \
9b94dc32 469 (void *)&rda[0], sizeof(rda), 0); \
e3c2613f
FB		 470 (RES) |= (rda[1] & 0x0000f000L)!=0x0000f000L; \
471 (RES) |= (rda[2] & 0x0000f000L)!=0x00000000L; \
472 } while (0); \
473 break; \
474 case 0x03: \
475 do { \
476 uint32_t rda[4]; \
6d2980f5 477 s->phys_mem_read(s->dma_opaque, (ADDR), \
9b94dc32 478 (void *)&rda[0], sizeof(rda), 0); \
e3c2613f
FB		 479 (RES) |= (rda[0] & 0x0000f000L)!=0x00000000L; \
480 (RES) |= (rda[1] & 0x0000f000L)!=0x0000f000L; \
481 } while (0); \
482 break; \
483 } \
484} while (0)
485
486#define CHECK_TMD(ADDR,RES) do { \
487 switch (BCR_SWSTYLE(s)) { \
488 case 0x00: \
489 do { \
490 uint16_t xda[4]; \
6d2980f5
TS		 491 s->phys_mem_read(s->dma_opaque, (ADDR), \
492 (void *)&xda[0], sizeof(xda), 0); \
493 (RES) |= (xda[2] & 0xf000)!=0xf000; \
e3c2613f
FB		 494 } while (0); \
495 break; \
496 case 0x01: \
497 case 0x02: \
498 case 0x03: \
499 do { \
500 uint32_t xda[4]; \
6d2980f5
TS		 501 s->phys_mem_read(s->dma_opaque, (ADDR), \
502 (void *)&xda[0], sizeof(xda), 0); \
e3c2613f
FB		 503 (RES) |= (xda[1] & 0x0000f000L)!=0x0000f000L; \
504 } while (0); \
505 break; \
506 } \
507} while (0)
508
509#endif
510
511#define PRINT_PKTHDR(BUF) do { \
6d2980f5
TS		 512 struct qemu_ether_header *hdr = (void *)(BUF); \
513 printf("packet dhost=%02x:%02x:%02x:%02x:%02x:%02x, " \
514 "shost=%02x:%02x:%02x:%02x:%02x:%02x, " \
515 "type=0x%04x\n", \
e3c2613f
FB		 516 hdr->ether_dhost[0],hdr->ether_dhost[1],hdr->ether_dhost[2], \
517 hdr->ether_dhost[3],hdr->ether_dhost[4],hdr->ether_dhost[5], \
518 hdr->ether_shost[0],hdr->ether_shost[1],hdr->ether_shost[2], \
519 hdr->ether_shost[3],hdr->ether_shost[4],hdr->ether_shost[5], \
6d2980f5 520 be16_to_cpu(hdr->ether_type)); \
e3c2613f
FB		 521} while (0)
522
523#define MULTICAST_FILTER_LEN 8
524
525static inline uint32_t lnc_mchash(const uint8_t *ether_addr)
526{
527#define LNC_POLYNOMIAL 0xEDB88320UL
528 uint32_t crc = 0xFFFFFFFF;
529 int idx, bit;
530 uint8_t data;
531
219fb125 532 for (idx = 0; idx < 6; idx++) {
e3c2613f
FB		 533 for (data = *ether_addr++, bit = 0; bit < MULTICAST_FILTER_LEN; bit++) {
534 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? LNC_POLYNOMIAL : 0);
535 data >>= 1;
536 }
537 }
538 return crc;
539#undef LNC_POLYNOMIAL
540}
541
542#define CRC(crc, ch) (crc = (crc >> 8) ^ crctab[(crc ^ (ch)) & 0xff])
543
544/* generated using the AUTODIN II polynomial
545 * x^32 + x^26 + x^23 + x^22 + x^16 +
546 * x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x^1 + 1
547 */
548static const uint32_t crctab[256] = {
549 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba,
550 0x076dc419, 0x706af48f, 0xe963a535, 0x9e6495a3,
551 0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988,
552 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91,
553 0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de,
554 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7,
555 0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec,
556 0x14015c4f, 0x63066cd9, 0xfa0f3d63, 0x8d080df5,
557 0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172,
558 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b,
559 0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940,
560 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59,
561 0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116,
562 0x21b4f4b5, 0x56b3c423, 0xcfba9599, 0xb8bda50f,
563 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924,
564 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d,
565 0x76dc4190, 0x01db7106, 0x98d220bc, 0xefd5102a,
566 0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433,
567 0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818,
568 0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01,
569 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e,
570 0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457,
571 0x65b0d9c6, 0x12b7e950, 0x8bbeb8ea, 0xfcb9887c,
572 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65,
573 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2,
574 0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb,
575 0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0,
576 0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9,
577 0x5005713c, 0x270241aa, 0xbe0b1010, 0xc90c2086,
578 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f,
579 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4,
580 0x59b33d17, 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad,
581 0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a,
582 0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683,
583 0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8,
584 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1,
585 0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe,
586 0xf762575d, 0x806567cb, 0x196c3671, 0x6e6b06e7,
587 0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc,
588 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5,
589 0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252,
590 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b,
591 0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60,
592 0xdf60efc3, 0xa867df55, 0x316e8eef, 0x4669be79,
593 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236,
594 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f,
595 0xc5ba3bbe, 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04,
596 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d,
597 0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a,
598 0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713,
599 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38,
600 0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21,
601 0x86d3d2d4, 0xf1d4e242, 0x68ddb3f8, 0x1fda836e,
602 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777,
603 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c,
604 0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45,
605 0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2,
606 0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db,
607 0xaed16a4a, 0xd9d65adc, 0x40df0b66, 0x37d83bf0,
608 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9,
609 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6,
610 0xbad03605, 0xcdd70693, 0x54de5729, 0x23d967bf,
611 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94,
612 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d,
613};
614
615static inline int padr_match(PCNetState *s, const uint8_t *buf, int size)
616{
219fb125 617 struct qemu_ether_header *hdr = (void *)buf;
5fafdf24 618 uint8_t padr[6] = {
e3c2613f
FB		 619 s->csr[12] & 0xff, s->csr[12] >> 8,
620 s->csr[13] & 0xff, s->csr[13] >> 8,
5fafdf24 621 s->csr[14] & 0xff, s->csr[14] >> 8
e3c2613f 622 };
29b9a345 623 int result = (!CSR_DRCVPA(s)) && !memcmp(hdr->ether_dhost, padr, 6);
e3c2613f
FB		 624#ifdef PCNET_DEBUG_MATCH
625 printf("packet dhost=%02x:%02x:%02x:%02x:%02x:%02x, "
626 "padr=%02x:%02x:%02x:%02x:%02x:%02x\n",
627 hdr->ether_dhost[0],hdr->ether_dhost[1],hdr->ether_dhost[2],
628 hdr->ether_dhost[3],hdr->ether_dhost[4],hdr->ether_dhost[5],
629 padr[0],padr[1],padr[2],padr[3],padr[4],padr[5]);
630 printf("padr_match result=%d\n", result);
631#endif
632 return result;
633}
634
635static inline int padr_bcast(PCNetState *s, const uint8_t *buf, int size)
636{
9b94dc32 637 static const uint8_t BCAST[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
219fb125 638 struct qemu_ether_header *hdr = (void *)buf;
29b9a345 639 int result = !CSR_DRCVBC(s) && !memcmp(hdr->ether_dhost, BCAST, 6);
e3c2613f
FB		 640#ifdef PCNET_DEBUG_MATCH
641 printf("padr_bcast result=%d\n", result);
642#endif
643 return result;
644}
645
646static inline int ladr_match(PCNetState *s, const uint8_t *buf, int size)
647{
219fb125 648 struct qemu_ether_header *hdr = (void *)buf;
5fafdf24 649 if ((*(hdr->ether_dhost)&0x01) &&
e3c2613f 650 ((uint64_t *)&s->csr[8])[0] != 0LL) {
5fafdf24 651 uint8_t ladr[8] = {
e3c2613f
FB		 652 s->csr[8] & 0xff, s->csr[8] >> 8,
653 s->csr[9] & 0xff, s->csr[9] >> 8,
5fafdf24
TS		 654 s->csr[10] & 0xff, s->csr[10] >> 8,
655 s->csr[11] & 0xff, s->csr[11] >> 8
e3c2613f
FB		 656 };
657 int index = lnc_mchash(hdr->ether_dhost) >> 26;
658 return !!(ladr[index >> 3] & (1 << (index & 7)));
659 }
660 return 0;
661}
662
a8170e5e 663static inline hwaddr pcnet_rdra_addr(PCNetState *s, int idx)
e3c2613f
FB		 664{
665 while (idx < 1) idx += CSR_RCVRL(s);
666 return s->rdra + ((CSR_RCVRL(s) - idx) * (BCR_SWSTYLE(s) ? 16 : 8));
667}
668
669static inline int64_t pcnet_get_next_poll_time(PCNetState *s, int64_t current_time)
670{
5fafdf24
TS		 671 int64_t next_time = current_time +
672 muldiv64(65536 - (CSR_SPND(s) ? 0 : CSR_POLL(s)),
6ee093c9 673 get_ticks_per_sec(), 33000000L);
e3c2613f
FB		 674 if (next_time <= current_time)
675 next_time = current_time + 1;
676 return next_time;
677}
678
679static void pcnet_poll(PCNetState *s);
680static void pcnet_poll_timer(void *opaque);
681
682static uint32_t pcnet_csr_readw(PCNetState *s, uint32_t rap);
683static void pcnet_csr_writew(PCNetState *s, uint32_t rap, uint32_t new_value);
684static void pcnet_bcr_writew(PCNetState *s, uint32_t rap, uint32_t val);
e3c2613f
FB		 685
686static void pcnet_s_reset(PCNetState *s)
687{
688#ifdef PCNET_DEBUG
689 printf("pcnet_s_reset\n");
690#endif
691
e3c2613f
FB		 692 s->rdra = 0;
693 s->tdra = 0;
694 s->rap = 0;
3b46e624 695
e3c2613f
FB		 696 s->bcr[BCR_BSBC] &= ~0x0080;
697
698 s->csr[0] = 0x0004;
699 s->csr[3] = 0x0000;
700 s->csr[4] = 0x0115;
701 s->csr[5] = 0x0000;
702 s->csr[6] = 0x0000;
703 s->csr[8] = 0;
704 s->csr[9] = 0;
705 s->csr[10] = 0;
706 s->csr[11] = 0;
707 s->csr[12] = le16_to_cpu(((uint16_t *)&s->prom[0])[0]);
708 s->csr[13] = le16_to_cpu(((uint16_t *)&s->prom[0])[1]);
709 s->csr[14] = le16_to_cpu(((uint16_t *)&s->prom[0])[2]);
710 s->csr[15] &= 0x21c4;
711 s->csr[72] = 1;
712 s->csr[74] = 1;
713 s->csr[76] = 1;
714 s->csr[78] = 1;
715 s->csr[80] = 0x1410;
716 s->csr[88] = 0x1003;
717 s->csr[89] = 0x0262;
718 s->csr[94] = 0x0000;
719 s->csr[100] = 0x0200;
720 s->csr[103] = 0x0105;
e3c2613f
FB		 721 s->csr[112] = 0x0000;
722 s->csr[114] = 0x0000;
723 s->csr[122] = 0x0000;
724 s->csr[124] = 0x0000;
ec607da7
FB		 725
726 s->tx_busy = 0;
e3c2613f
FB		 727}
728
729static void pcnet_update_irq(PCNetState *s)
730{
731 int isr = 0;
732 s->csr[0] &= ~0x0080;
3b46e624 733
e3c2613f
FB		 734#if 1
735 if (((s->csr[0] & ~s->csr[3]) & 0x5f00) ||
736 (((s->csr[4]>>1) & ~s->csr[4]) & 0x0115) ||
737 (((s->csr[5]>>1) & s->csr[5]) & 0x0048))
738#else
739 if ((!(s->csr[3] & 0x4000) && !!(s->csr[0] & 0x4000)) /* BABL */ ||
740 (!(s->csr[3] & 0x1000) && !!(s->csr[0] & 0x1000)) /* MISS */ ||
741 (!(s->csr[3] & 0x0100) && !!(s->csr[0] & 0x0100)) /* IDON */ ||
742 (!(s->csr[3] & 0x0200) && !!(s->csr[0] & 0x0200)) /* TINT */ ||
743 (!(s->csr[3] & 0x0400) && !!(s->csr[0] & 0x0400)) /* RINT */ ||
744 (!(s->csr[3] & 0x0800) && !!(s->csr[0] & 0x0800)) /* MERR */ ||
745 (!(s->csr[4] & 0x0001) && !!(s->csr[4] & 0x0002)) /* JAB */ ||
746 (!(s->csr[4] & 0x0004) && !!(s->csr[4] & 0x0008)) /* TXSTRT */ ||
747 (!(s->csr[4] & 0x0010) && !!(s->csr[4] & 0x0020)) /* RCVO */ ||
748 (!(s->csr[4] & 0x0100) && !!(s->csr[4] & 0x0200)) /* MFCO */ ||
749 (!!(s->csr[5] & 0x0040) && !!(s->csr[5] & 0x0080)) /* EXDINT */ ||
750 (!!(s->csr[5] & 0x0008) && !!(s->csr[5] & 0x0010)) /* MPINT */)
751#endif
752 {
3b46e624 753
e3c2613f
FB		 754 isr = CSR_INEA(s);
755 s->csr[0] |= 0x0080;
756 }
3b46e624 757
e3c2613f
FB		 758 if (!!(s->csr[4] & 0x0080) && CSR_INEA(s)) { /* UINT */
759 s->csr[4] &= ~0x0080;
760 s->csr[4] |= 0x0040;
761 s->csr[0] |= 0x0080;
762 isr = 1;
763#ifdef PCNET_DEBUG
764 printf("pcnet user int\n");
765#endif
766 }
767
768#if 1
5fafdf24 769 if (((s->csr[5]>>1) & s->csr[5]) & 0x0500)
e3c2613f
FB		 770#else
771 if ((!!(s->csr[5] & 0x0400) && !!(s->csr[5] & 0x0800)) /* SINT */ ||
772 (!!(s->csr[5] & 0x0100) && !!(s->csr[5] & 0x0200)) /* SLPINT */ )
773#endif
774 {
775 isr = 1;
776 s->csr[0] |= 0x0080;
777 }
778
779 if (isr != s->isr) {
780#ifdef PCNET_DEBUG
781 printf("pcnet: INTA=%d\n", isr);
782#endif
783 }
d537cf6c 784 qemu_set_irq(s->irq, isr);
91cc0295 785 s->isr = isr;
e3c2613f
FB		 786}
787
788static void pcnet_init(PCNetState *s)
789{
91cc0295 790 int rlen, tlen;
6d2980f5 791 uint16_t padr[3], ladrf[4], mode;
91cc0295
FB		 792 uint32_t rdra, tdra;
793
e3c2613f
FB		 794#ifdef PCNET_DEBUG
795 printf("pcnet_init init_addr=0x%08x\n", PHYSADDR(s,CSR_IADR(s)));
796#endif
3b46e624 797
e3c2613f
FB		 798 if (BCR_SSIZE32(s)) {
799 struct pcnet_initblk32 initblk;
91cc0295 800 s->phys_mem_read(s->dma_opaque, PHYSADDR(s,CSR_IADR(s)),
9b94dc32 801 (uint8_t *)&initblk, sizeof(initblk), 0);
6d2980f5 802 mode = le16_to_cpu(initblk.mode);
91cc0295
FB		 803 rlen = initblk.rlen >> 4;
804 tlen = initblk.tlen >> 4;
6d2980f5
TS		 805 ladrf[0] = le16_to_cpu(initblk.ladrf[0]);
806 ladrf[1] = le16_to_cpu(initblk.ladrf[1]);
807 ladrf[2] = le16_to_cpu(initblk.ladrf[2]);
808 ladrf[3] = le16_to_cpu(initblk.ladrf[3]);
809 padr[0] = le16_to_cpu(initblk.padr[0]);
810 padr[1] = le16_to_cpu(initblk.padr[1]);
811 padr[2] = le16_to_cpu(initblk.padr[2]);
9b94dc32
FB		 812 rdra = le32_to_cpu(initblk.rdra);
813 tdra = le32_to_cpu(initblk.tdra);
e3c2613f
FB		 814 } else {
815 struct pcnet_initblk16 initblk;
91cc0295 816 s->phys_mem_read(s->dma_opaque, PHYSADDR(s,CSR_IADR(s)),
9b94dc32 817 (uint8_t *)&initblk, sizeof(initblk), 0);
6d2980f5
TS		 818 mode = le16_to_cpu(initblk.mode);
819 ladrf[0] = le16_to_cpu(initblk.ladrf[0]);
820 ladrf[1] = le16_to_cpu(initblk.ladrf[1]);
821 ladrf[2] = le16_to_cpu(initblk.ladrf[2]);
822 ladrf[3] = le16_to_cpu(initblk.ladrf[3]);
823 padr[0] = le16_to_cpu(initblk.padr[0]);
824 padr[1] = le16_to_cpu(initblk.padr[1]);
825 padr[2] = le16_to_cpu(initblk.padr[2]);
9b94dc32
FB		 826 rdra = le32_to_cpu(initblk.rdra);
827 tdra = le32_to_cpu(initblk.tdra);
91cc0295
FB		 828 rlen = rdra >> 29;
829 tlen = tdra >> 29;
830 rdra &= 0x00ffffff;
831 tdra &= 0x00ffffff;
832 }
6d2980f5 833
91cc0295 834#if defined(PCNET_DEBUG)
6d2980f5 835 printf("rlen=%d tlen=%d\n", rlen, tlen);
e3c2613f 836#endif
6d2980f5 837
91cc0295
FB		 838 CSR_RCVRL(s) = (rlen < 9) ? (1 << rlen) : 512;
839 CSR_XMTRL(s) = (tlen < 9) ? (1 << tlen) : 512;
840 s->csr[ 6] = (tlen << 12) | (rlen << 8);
6d2980f5
TS		 841 s->csr[15] = mode;
842 s->csr[ 8] = ladrf[0];
843 s->csr[ 9] = ladrf[1];
844 s->csr[10] = ladrf[2];
845 s->csr[11] = ladrf[3];
846 s->csr[12] = padr[0];
847 s->csr[13] = padr[1];
848 s->csr[14] = padr[2];
91cc0295
FB		 849 s->rdra = PHYSADDR(s, rdra);
850 s->tdra = PHYSADDR(s, tdra);
e3c2613f
FB		 851
852 CSR_RCVRC(s) = CSR_RCVRL(s);
853 CSR_XMTRC(s) = CSR_XMTRL(s);
854
855#ifdef PCNET_DEBUG
5fafdf24 856 printf("pcnet ss32=%d rdra=0x%08x[%d] tdra=0x%08x[%d]\n",
e3c2613f
FB		 857 BCR_SSIZE32(s),
858 s->rdra, CSR_RCVRL(s), s->tdra, CSR_XMTRL(s));
859#endif
860
3b46e624 861 s->csr[0] |= 0x0101;
e3c2613f 862 s->csr[0] &= ~0x0004; /* clear STOP bit */
ee76c1f8
JK		 863
864 qemu_flush_queued_packets(qemu_get_queue(s->nic));
e3c2613f
FB		 865}
866
867static void pcnet_start(PCNetState *s)
868{
869#ifdef PCNET_DEBUG
870 printf("pcnet_start\n");
871#endif
872
873 if (!CSR_DTX(s))
874 s->csr[0] |= 0x0010; /* set TXON */
3b46e624 875
e3c2613f
FB		 876 if (!CSR_DRX(s))
877 s->csr[0] |= 0x0020; /* set RXON */
878
879 s->csr[0] &= ~0x0004; /* clear STOP bit */
880 s->csr[0] |= 0x0002;
ad323081 881 pcnet_poll_timer(s);
ee76c1f8
JK		 882
883 qemu_flush_queued_packets(qemu_get_queue(s->nic));
e3c2613f
FB		 884}
885
886static void pcnet_stop(PCNetState *s)
887{
888#ifdef PCNET_DEBUG
889 printf("pcnet_stop\n");
890#endif
6655124d 891 s->csr[0] &= ~0xffeb;
e3c2613f
FB		 892 s->csr[0] |= 0x0014;
893 s->csr[4] &= ~0x02c2;
894 s->csr[5] &= ~0x0011;
895 pcnet_poll_timer(s);
896}
897
898static void pcnet_rdte_poll(PCNetState *s)
899{
900 s->csr[28] = s->csr[29] = 0;
901 if (s->rdra) {
902 int bad = 0;
903#if 1
a8170e5e
AK		 904 hwaddr crda = pcnet_rdra_addr(s, CSR_RCVRC(s));
905 hwaddr nrda = pcnet_rdra_addr(s, -1 + CSR_RCVRC(s));
906 hwaddr nnrd = pcnet_rdra_addr(s, -2 + CSR_RCVRC(s));
e3c2613f 907#else
a8170e5e 908 hwaddr crda = s->rdra +
e3c2613f
FB		 909 (CSR_RCVRL(s) - CSR_RCVRC(s)) *
910 (BCR_SWSTYLE(s) ? 16 : 8 );
911 int nrdc = CSR_RCVRC(s)<=1 ? CSR_RCVRL(s) : CSR_RCVRC(s)-1;
a8170e5e 912 hwaddr nrda = s->rdra +
e3c2613f
FB		 913 (CSR_RCVRL(s) - nrdc) *
914 (BCR_SWSTYLE(s) ? 16 : 8 );
915 int nnrc = nrdc<=1 ? CSR_RCVRL(s) : nrdc-1;
a8170e5e 916 hwaddr nnrd = s->rdra +
e3c2613f
FB		 917 (CSR_RCVRL(s) - nnrc) *
918 (BCR_SWSTYLE(s) ? 16 : 8 );
919#endif
920
f1afe02a 921 CHECK_RMD(crda, bad);
e3c2613f 922 if (!bad) {
f1afe02a 923 CHECK_RMD(nrda, bad);
e3c2613f 924 if (bad || (nrda == crda)) nrda = 0;
f1afe02a 925 CHECK_RMD(nnrd, bad);
e3c2613f
FB		 926 if (bad || (nnrd == crda)) nnrd = 0;
927
928 s->csr[28] = crda & 0xffff;
929 s->csr[29] = crda >> 16;
930 s->csr[26] = nrda & 0xffff;
931 s->csr[27] = nrda >> 16;
932 s->csr[36] = nnrd & 0xffff;
933 s->csr[37] = nnrd >> 16;
934#ifdef PCNET_DEBUG
935 if (bad) {
cb3df91a 936 printf("pcnet: BAD RMD RECORDS AFTER 0x" TARGET_FMT_plx "\n",
f1afe02a 937 crda);
e3c2613f
FB		 938 }
939 } else {
cb3df91a 940 printf("pcnet: BAD RMD RDA=0x" TARGET_FMT_plx "\n",
f1afe02a 941 crda);
e3c2613f
FB		 942#endif
943 }
944 }
3b46e624 945
e3c2613f
FB		 946 if (CSR_CRDA(s)) {
947 struct pcnet_RMD rmd;
948 RMDLOAD(&rmd, PHYSADDR(s,CSR_CRDA(s)));
6d2980f5
TS		 949 CSR_CRBC(s) = GET_FIELD(rmd.buf_length, RMDL, BCNT);
950 CSR_CRST(s) = rmd.status;
e3c2613f 951#ifdef PCNET_DEBUG_RMD_X
6d2980f5 952 printf("CRDA=0x%08x CRST=0x%04x RCVRC=%d RMDL=0x%04x RMDS=0x%04x RMDM=0x%08x\n",
e3c2613f 953 PHYSADDR(s,CSR_CRDA(s)), CSR_CRST(s), CSR_RCVRC(s),
6d2980f5 954 rmd.buf_length, rmd.status, rmd.msg_length);
e3c2613f
FB		 955 PRINT_RMD(&rmd);
956#endif
957 } else {
958 CSR_CRBC(s) = CSR_CRST(s) = 0;
959 }
3b46e624 960
e3c2613f
FB		 961 if (CSR_NRDA(s)) {
962 struct pcnet_RMD rmd;
963 RMDLOAD(&rmd, PHYSADDR(s,CSR_NRDA(s)));
6d2980f5
TS		 964 CSR_NRBC(s) = GET_FIELD(rmd.buf_length, RMDL, BCNT);
965 CSR_NRST(s) = rmd.status;
e3c2613f
FB		 966 } else {
967 CSR_NRBC(s) = CSR_NRST(s) = 0;
968 }
969
970}
971
972static int pcnet_tdte_poll(PCNetState *s)
973{
974 s->csr[34] = s->csr[35] = 0;
975 if (s->tdra) {
a8170e5e 976 hwaddr cxda = s->tdra +
e3c2613f 977 (CSR_XMTRL(s) - CSR_XMTRC(s)) *
6d2980f5 978 (BCR_SWSTYLE(s) ? 16 : 8);
e3c2613f 979 int bad = 0;
f1afe02a 980 CHECK_TMD(cxda, bad);
e3c2613f
FB		 981 if (!bad) {
982 if (CSR_CXDA(s) != cxda) {
983 s->csr[60] = s->csr[34];
984 s->csr[61] = s->csr[35];
985 s->csr[62] = CSR_CXBC(s);
986 s->csr[63] = CSR_CXST(s);
987 }
988 s->csr[34] = cxda & 0xffff;
989 s->csr[35] = cxda >> 16;
6d2980f5 990#ifdef PCNET_DEBUG_X
f1afe02a 991 printf("pcnet: BAD TMD XDA=0x%08x\n", cxda);
e3c2613f
FB		 992#endif
993 }
994 }
995
996 if (CSR_CXDA(s)) {
997 struct pcnet_TMD tmd;
998
3b46e624 999 TMDLOAD(&tmd, PHYSADDR(s,CSR_CXDA(s)));
e3c2613f 1000
6d2980f5
TS		 1001 CSR_CXBC(s) = GET_FIELD(tmd.length, TMDL, BCNT);
1002 CSR_CXST(s) = tmd.status;
e3c2613f
FB		 1003 } else {
1004 CSR_CXBC(s) = CSR_CXST(s) = 0;
1005 }
3b46e624 1006
e3c2613f
FB		 1007 return !!(CSR_CXST(s) & 0x8000);
1008}
1009
4e68f7a0 1010int pcnet_can_receive(NetClientState *nc)
e3c2613f 1011{
cc1f0f45 1012 PCNetState *s = qemu_get_nic_opaque(nc);
e3c2613f
FB		 1013 if (CSR_STOP(s) || CSR_SPND(s))
1014 return 0;
3b46e624 1015
e3c2613f
FB		 1016 return sizeof(s->buffer)-16;
1017}
1018
1019#define MIN_BUF_SIZE 60
1020
4e68f7a0 1021ssize_t pcnet_receive(NetClientState *nc, const uint8_t *buf, size_t size_)
e3c2613f 1022{
cc1f0f45 1023 PCNetState *s = qemu_get_nic_opaque(nc);
e3c2613f
FB		 1024 int is_padr = 0, is_bcast = 0, is_ladr = 0;
1025 uint8_t buf1[60];
89b190a2
AJ		 1026 int remaining;
1027 int crc_err = 0;
4f1c942b 1028 int size = size_;
e3c2613f 1029
c1ded3dc
JK		 1030 if (CSR_DRX(s) || CSR_STOP(s) || CSR_SPND(s) || !size ||
1031 (CSR_LOOP(s) && !s->looptest)) {
4f1c942b 1032 return -1;
c1ded3dc 1033 }
e3c2613f
FB		 1034#ifdef PCNET_DEBUG
1035 printf("pcnet_receive size=%d\n", size);
1036#endif
1037
1038 /* if too small buffer, then expand it */
1039 if (size < MIN_BUF_SIZE) {
1040 memcpy(buf1, buf, size);
1041 memset(buf1 + size, 0, MIN_BUF_SIZE - size);
1042 buf = buf1;
1043 size = MIN_BUF_SIZE;
1044 }
1045
5fafdf24
TS		 1046 if (CSR_PROM(s)
1047 || (is_padr=padr_match(s, buf, size))
e3c2613f
FB		 1048 || (is_bcast=padr_bcast(s, buf, size))
1049 || (is_ladr=ladr_match(s, buf, size))) {
1050
1051 pcnet_rdte_poll(s);
1052
1053 if (!(CSR_CRST(s) & 0x8000) && s->rdra) {
1054 struct pcnet_RMD rmd;
1055 int rcvrc = CSR_RCVRC(s)-1,i;
a8170e5e 1056 hwaddr nrda;
e3c2613f
FB		 1057 for (i = CSR_RCVRL(s)-1; i > 0; i--, rcvrc--) {
1058 if (rcvrc <= 1)
1059 rcvrc = CSR_RCVRL(s);
1060 nrda = s->rdra +
1061 (CSR_RCVRL(s) - rcvrc) *
1062 (BCR_SWSTYLE(s) ? 16 : 8 );
f1afe02a 1063 RMDLOAD(&rmd, nrda);
6d2980f5 1064 if (GET_FIELD(rmd.status, RMDS, OWN)) {
e3c2613f 1065#ifdef PCNET_DEBUG_RMD
5fafdf24 1066 printf("pcnet - scan buffer: RCVRC=%d PREV_RCVRC=%d\n",
e3c2613f
FB		 1067 rcvrc, CSR_RCVRC(s));
1068#endif
1069 CSR_RCVRC(s) = rcvrc;
1070 pcnet_rdte_poll(s);
1071 break;
1072 }
1073 }
1074 }
1075
1076 if (!(CSR_CRST(s) & 0x8000)) {
1077#ifdef PCNET_DEBUG_RMD
1078 printf("pcnet - no buffer: RCVRC=%d\n", CSR_RCVRC(s));
1079#endif
1080 s->csr[0] |= 0x1000; /* Set MISS flag */
1081 CSR_MISSC(s)++;
1082 } else {
89b190a2 1083 uint8_t *src = s->buffer;
a8170e5e 1084 hwaddr crda = CSR_CRDA(s);
e3c2613f
FB		 1085 struct pcnet_RMD rmd;
1086 int pktcount = 0;
1087
89b190a2
AJ		 1088 if (!s->looptest) {
1089 memcpy(src, buf, size);
1090 /* no need to compute the CRC */
1091 src[size] = 0;
1092 src[size + 1] = 0;
1093 src[size + 2] = 0;
1094 src[size + 3] = 0;
1095 size += 4;
1096 } else if (s->looptest == PCNET_LOOPTEST_CRC ||
1097 !CSR_DXMTFCS(s) || size < MIN_BUF_SIZE+4) {
e3c2613f 1098 uint32_t fcs = ~0;
e3c2613f 1099 uint8_t *p = src;
e3c2613f 1100
89b190a2
AJ		 1101 while (p != &src[size])
1102 CRC(fcs, *p++);
1103 *(uint32_t *)p = htonl(fcs);
1104 size += 4;
1105 } else {
1106 uint32_t fcs = ~0;
1107 uint8_t *p = src;
3b46e624 1108
89b190a2 1109 while (p != &src[size-4])
e3c2613f 1110 CRC(fcs, *p++);
89b190a2
AJ		 1111 crc_err = (*(uint32_t *)p != htonl(fcs));
1112 }
e3c2613f
FB		 1113
1114#ifdef PCNET_DEBUG_MATCH
1115 PRINT_PKTHDR(buf);
1116#endif
1117
1118 RMDLOAD(&rmd, PHYSADDR(s,crda));
1119 /*if (!CSR_LAPPEN(s))*/
6d2980f5 1120 SET_FIELD(&rmd.status, RMDS, STP, 1);
e3c2613f
FB		 1121
1122#define PCNET_RECV_STORE() do { \
89b190a2 1123 int count = MIN(4096 - GET_FIELD(rmd.buf_length, RMDL, BCNT),remaining); \
a8170e5e 1124 hwaddr rbadr = PHYSADDR(s, rmd.rbadr); \
6d2980f5 1125 s->phys_mem_write(s->dma_opaque, rbadr, src, count, CSR_BSWP(s)); \
89b190a2 1126 src += count; remaining -= count; \
6d2980f5 1127 SET_FIELD(&rmd.status, RMDS, OWN, 0); \
e3c2613f
FB		 1128 RMDSTORE(&rmd, PHYSADDR(s,crda)); \
1129 pktcount++; \
1130} while (0)
1131
89b190a2 1132 remaining = size;
e3c2613f 1133 PCNET_RECV_STORE();
89b190a2 1134 if ((remaining > 0) && CSR_NRDA(s)) {
a8170e5e 1135 hwaddr nrda = CSR_NRDA(s);
89b190a2
AJ		 1136#ifdef PCNET_DEBUG_RMD
1137 PRINT_RMD(&rmd);
1138#endif
e3c2613f 1139 RMDLOAD(&rmd, PHYSADDR(s,nrda));
6d2980f5 1140 if (GET_FIELD(rmd.status, RMDS, OWN)) {
e3c2613f
FB		 1141 crda = nrda;
1142 PCNET_RECV_STORE();
89b190a2
AJ		 1143#ifdef PCNET_DEBUG_RMD
1144 PRINT_RMD(&rmd);
1145#endif
1146 if ((remaining > 0) && (nrda=CSR_NNRD(s))) {
e3c2613f 1147 RMDLOAD(&rmd, PHYSADDR(s,nrda));
6d2980f5 1148 if (GET_FIELD(rmd.status, RMDS, OWN)) {
e3c2613f
FB		 1149 crda = nrda;
1150 PCNET_RECV_STORE();
1151 }
1152 }
3b46e624 1153 }
e3c2613f
FB		 1154 }
1155
1156#undef PCNET_RECV_STORE
1157
1158 RMDLOAD(&rmd, PHYSADDR(s,crda));
89b190a2
AJ		 1159 if (remaining == 0) {
1160 SET_FIELD(&rmd.msg_length, RMDM, MCNT, size);
6d2980f5
TS		 1161 SET_FIELD(&rmd.status, RMDS, ENP, 1);
1162 SET_FIELD(&rmd.status, RMDS, PAM, !CSR_PROM(s) && is_padr);
1163 SET_FIELD(&rmd.status, RMDS, LFAM, !CSR_PROM(s) && is_ladr);
1164 SET_FIELD(&rmd.status, RMDS, BAM, !CSR_PROM(s) && is_bcast);
89b190a2
AJ		 1165 if (crc_err) {
1166 SET_FIELD(&rmd.status, RMDS, CRC, 1);
1167 SET_FIELD(&rmd.status, RMDS, ERR, 1);
1168 }
e3c2613f 1169 } else {
6d2980f5
TS		 1170 SET_FIELD(&rmd.status, RMDS, OFLO, 1);
1171 SET_FIELD(&rmd.status, RMDS, BUFF, 1);
1172 SET_FIELD(&rmd.status, RMDS, ERR, 1);
e3c2613f
FB		 1173 }
1174 RMDSTORE(&rmd, PHYSADDR(s,crda));
1175 s->csr[0] |= 0x0400;
1176
1177#ifdef PCNET_DEBUG
5fafdf24 1178 printf("RCVRC=%d CRDA=0x%08x BLKS=%d\n",
e3c2613f
FB		 1179 CSR_RCVRC(s), PHYSADDR(s,CSR_CRDA(s)), pktcount);
1180#endif
1181#ifdef PCNET_DEBUG_RMD
1182 PRINT_RMD(&rmd);
3b46e624 1183#endif
e3c2613f
FB		 1184
1185 while (pktcount--) {
1186 if (CSR_RCVRC(s) <= 1)
1187 CSR_RCVRC(s) = CSR_RCVRL(s);
1188 else
3b46e624 1189 CSR_RCVRC(s)--;
e3c2613f 1190 }
3b46e624 1191
e3c2613f
FB		 1192 pcnet_rdte_poll(s);
1193
3b46e624 1194 }
e3c2613f
FB		 1195 }
1196
1197 pcnet_poll(s);
3b46e624 1198 pcnet_update_irq(s);
4f1c942b
MM		 1199
1200 return size_;
e3c2613f
FB		 1201}
1202
4e68f7a0 1203void pcnet_set_link_status(NetClientState *nc)
e1c2008a 1204{
cc1f0f45 1205 PCNetState *d = qemu_get_nic_opaque(nc);
e1c2008a
JK		 1206
1207 d->lnkst = nc->link_down ? 0 : 0x40;
1208}
1209
e3c2613f
FB		 1210static void pcnet_transmit(PCNetState *s)
1211{
a8170e5e 1212 hwaddr xmit_cxda = 0;
e3c2613f 1213 int count = CSR_XMTRL(s)-1;
89b190a2
AJ		 1214 int add_crc = 0;
1215
e3c2613f 1216 s->xmit_pos = -1;
3b46e624 1217
e3c2613f
FB		 1218 if (!CSR_TXON(s)) {
1219 s->csr[0] &= ~0x0008;
1220 return;
1221 }
ec607da7
FB		 1222
1223 s->tx_busy = 1;
1224
e3c2613f
FB		 1225 txagain:
1226 if (pcnet_tdte_poll(s)) {
1227 struct pcnet_TMD tmd;
1228
6d2980f5 1229 TMDLOAD(&tmd, PHYSADDR(s,CSR_CXDA(s)));
e3c2613f
FB		 1230
1231#ifdef PCNET_DEBUG_TMD
1232 printf(" TMDLOAD 0x%08x\n", PHYSADDR(s,CSR_CXDA(s)));
1233 PRINT_TMD(&tmd);
1234#endif
6d2980f5
TS		 1235 if (GET_FIELD(tmd.status, TMDS, STP)) {
1236 s->xmit_pos = 0;
e3c2613f 1237 xmit_cxda = PHYSADDR(s,CSR_CXDA(s));
89b190a2
AJ		 1238 if (BCR_SWSTYLE(s) != 1)
1239 add_crc = GET_FIELD(tmd.status, TMDS, ADDFCS);
e3c2613f 1240 }
ef45c914
JK		 1241 if (s->lnkst == 0 &&
1242 (!CSR_LOOP(s) || (!CSR_INTL(s) && !BCR_TMAULOOP(s)))) {
1243 SET_FIELD(&tmd.misc, TMDM, LCAR, 1);
1244 SET_FIELD(&tmd.status, TMDS, ERR, 1);
1245 SET_FIELD(&tmd.status, TMDS, OWN, 0);
1246 s->csr[0] |= 0xa000; /* ERR | CERR */
1247 s->xmit_pos = -1;
1248 goto txdone;
1249 }
9bd0d294
BS		 1250 if (!GET_FIELD(tmd.status, TMDS, ENP)) {
1251 int bcnt = 4096 - GET_FIELD(tmd.length, TMDL, BCNT);
1252 s->phys_mem_read(s->dma_opaque, PHYSADDR(s, tmd.tbadr),
1253 s->buffer + s->xmit_pos, bcnt, CSR_BSWP(s));
1254 s->xmit_pos += bcnt;
1255 } else if (s->xmit_pos >= 0) {
6d2980f5
TS		 1256 int bcnt = 4096 - GET_FIELD(tmd.length, TMDL, BCNT);
1257 s->phys_mem_read(s->dma_opaque, PHYSADDR(s, tmd.tbadr),
1258 s->buffer + s->xmit_pos, bcnt, CSR_BSWP(s));
1259 s->xmit_pos += bcnt;
e3c2613f
FB		 1260#ifdef PCNET_DEBUG
1261 printf("pcnet_transmit size=%d\n", s->xmit_pos);
6d2980f5 1262#endif
89b190a2
AJ		 1263 if (CSR_LOOP(s)) {
1264 if (BCR_SWSTYLE(s) == 1)
1265 add_crc = !GET_FIELD(tmd.status, TMDS, NOFCS);
1266 s->looptest = add_crc ? PCNET_LOOPTEST_CRC : PCNET_LOOPTEST_NOCRC;
b356f76d 1267 pcnet_receive(qemu_get_queue(s->nic), s->buffer, s->xmit_pos);
89b190a2
AJ		 1268 s->looptest = 0;
1269 } else
1fa51482 1270 if (s->nic)
b356f76d
JW		 1271 qemu_send_packet(qemu_get_queue(s->nic), s->buffer,
1272 s->xmit_pos);
e3c2613f
FB		 1273
1274 s->csr[0] &= ~0x0008; /* clear TDMD */
1275 s->csr[4] |= 0x0004; /* set TXSTRT */
1276 s->xmit_pos = -1;
1277 }
1278
ef45c914 1279 txdone:
6d2980f5 1280 SET_FIELD(&tmd.status, TMDS, OWN, 0);
e3c2613f 1281 TMDSTORE(&tmd, PHYSADDR(s,CSR_CXDA(s)));
6d2980f5 1282 if (!CSR_TOKINTD(s) || (CSR_LTINTEN(s) && GET_FIELD(tmd.status, TMDS, LTINT)))
e3c2613f
FB		 1283 s->csr[0] |= 0x0200; /* set TINT */
1284
1285 if (CSR_XMTRC(s)<=1)
1286 CSR_XMTRC(s) = CSR_XMTRL(s);
1287 else
1288 CSR_XMTRC(s)--;
1289 if (count--)
1290 goto txagain;
1291
5fafdf24 1292 } else
e3c2613f
FB		 1293 if (s->xmit_pos >= 0) {
1294 struct pcnet_TMD tmd;
f1afe02a 1295 TMDLOAD(&tmd, xmit_cxda);
6d2980f5
TS		 1296 SET_FIELD(&tmd.misc, TMDM, BUFF, 1);
1297 SET_FIELD(&tmd.misc, TMDM, UFLO, 1);
1298 SET_FIELD(&tmd.status, TMDS, ERR, 1);
1299 SET_FIELD(&tmd.status, TMDS, OWN, 0);
f1afe02a 1300 TMDSTORE(&tmd, xmit_cxda);
e3c2613f
FB		 1301 s->csr[0] |= 0x0200; /* set TINT */
1302 if (!CSR_DXSUFLO(s)) {
1303 s->csr[0] &= ~0x0010;
1304 } else
1305 if (count--)
1306 goto txagain;
1307 }
ec607da7
FB		 1308
1309 s->tx_busy = 0;
e3c2613f
FB		 1310}
1311
1312static void pcnet_poll(PCNetState *s)
1313{
1314 if (CSR_RXON(s)) {
1315 pcnet_rdte_poll(s);
1316 }
1317
5fafdf24 1318 if (CSR_TDMD(s) ||
e3c2613f 1319 (CSR_TXON(s) && !CSR_DPOLL(s) && pcnet_tdte_poll(s)))
ec607da7
FB		 1320 {
1321 /* prevent recursion */
1322 if (s->tx_busy)
1323 return;
1324
e3c2613f 1325 pcnet_transmit(s);
ec607da7 1326 }
e3c2613f
FB		 1327}
1328
1329static void pcnet_poll_timer(void *opaque)
1330{
1331 PCNetState *s = opaque;
1332
bc72ad67 1333 timer_del(s->poll_timer);
e3c2613f
FB		 1334
1335 if (CSR_TDMD(s)) {
1336 pcnet_transmit(s);
1337 }
1338
3b46e624 1339 pcnet_update_irq(s);
e3c2613f
FB		 1340
1341 if (!CSR_STOP(s) && !CSR_SPND(s) && !CSR_DPOLL(s)) {
bc72ad67 1342 uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) * 33;
e3c2613f
FB		 1343 if (!s->timer || !now)
1344 s->timer = now;
1345 else {
1346 uint64_t t = now - s->timer + CSR_POLL(s);
1347 if (t > 0xffffLL) {
1348 pcnet_poll(s);
1349 CSR_POLL(s) = CSR_PINT(s);
1350 } else
1351 CSR_POLL(s) = t;
1352 }
bc72ad67
AB		 1353 timer_mod(s->poll_timer,
1354 pcnet_get_next_poll_time(s,qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)));
e3c2613f
FB		 1355 }
1356}
1357
1358
1359static void pcnet_csr_writew(PCNetState *s, uint32_t rap, uint32_t new_value)
1360{
1361 uint16_t val = new_value;
1362#ifdef PCNET_DEBUG_CSR
1363 printf("pcnet_csr_writew rap=%d val=0x%04x\n", rap, val);
1364#endif
1365 switch (rap) {
1366 case 0:
1367 s->csr[0] &= ~(val & 0x7f00); /* Clear any interrupt flags */
1368
1369 s->csr[0] = (s->csr[0] & ~0x0040) | (val & 0x0048);
1370
1371 val = (val & 0x007f) | (s->csr[0] & 0x7f00);
1372
1373 /* IFF STOP, STRT and INIT are set, clear STRT and INIT */
1374 if ((val&7) == 7)
1375 val &= ~3;
1376
1377 if (!CSR_STOP(s) && (val & 4))
1378 pcnet_stop(s);
1379
1380 if (!CSR_INIT(s) && (val & 1))
1381 pcnet_init(s);
1382
1383 if (!CSR_STRT(s) && (val & 2))
1384 pcnet_start(s);
1385
5fafdf24 1386 if (CSR_TDMD(s))
e3c2613f
FB		 1387 pcnet_transmit(s);
1388
1389 return;
1390 case 1:
1391 case 2:
1392 case 8:
1393 case 9:
1394 case 10:
1395 case 11:
1396 case 12:
1397 case 13:
1398 case 14:
1399 case 15:
1400 case 18: /* CRBAL */
1401 case 19: /* CRBAU */
1402 case 20: /* CXBAL */
1403 case 21: /* CXBAU */
1404 case 22: /* NRBAU */
1405 case 23: /* NRBAU */
1406 case 24:
1407 case 25:
1408 case 26:
1409 case 27:
1410 case 28:
1411 case 29:
1412 case 30:
1413 case 31:
1414 case 32:
1415 case 33:
1416 case 34:
1417 case 35:
1418 case 36:
1419 case 37:
1420 case 38:
1421 case 39:
1422 case 40: /* CRBC */
1423 case 41:
1424 case 42: /* CXBC */
1425 case 43:
1426 case 44:
1427 case 45:
1428 case 46: /* POLL */
1429 case 47: /* POLLINT */
1430 case 72:
1431 case 74:
1432 case 76: /* RCVRL */
1433 case 78: /* XMTRL */
1434 case 112:
1435 if (CSR_STOP(s) || CSR_SPND(s))
1436 break;
1437 return;
1438 case 3:
1439 break;
1440 case 4:
5fafdf24 1441 s->csr[4] &= ~(val & 0x026a);
e3c2613f
FB		 1442 val &= ~0x026a; val |= s->csr[4] & 0x026a;
1443 break;
1444 case 5:
5fafdf24 1445 s->csr[5] &= ~(val & 0x0a90);
e3c2613f
FB		 1446 val &= ~0x0a90; val |= s->csr[5] & 0x0a90;
1447 break;
1448 case 16:
1449 pcnet_csr_writew(s,1,val);
1450 return;
1451 case 17:
1452 pcnet_csr_writew(s,2,val);
1453 return;
1454 case 58:
1455 pcnet_bcr_writew(s,BCR_SWS,val);
1456 break;
1457 default:
1458 return;
1459 }
1460 s->csr[rap] = val;
1461}
1462
1463static uint32_t pcnet_csr_readw(PCNetState *s, uint32_t rap)
1464{
1465 uint32_t val;
1466 switch (rap) {
1467 case 0:
1468 pcnet_update_irq(s);
1469 val = s->csr[0];
1470 val |= (val & 0x7800) ? 0x8000 : 0;
1471 break;
1472 case 16:
1473 return pcnet_csr_readw(s,1);
1474 case 17:
1475 return pcnet_csr_readw(s,2);
1476 case 58:
1477 return pcnet_bcr_readw(s,BCR_SWS);
1478 case 88:
1479 val = s->csr[89];
1480 val <<= 16;
1481 val |= s->csr[88];
1482 break;
1483 default:
1484 val = s->csr[rap];
1485 }
1486#ifdef PCNET_DEBUG_CSR
1487 printf("pcnet_csr_readw rap=%d val=0x%04x\n", rap, val);
1488#endif
1489 return val;
1490}
1491
1492static void pcnet_bcr_writew(PCNetState *s, uint32_t rap, uint32_t val)
1493{
1494 rap &= 127;
1495#ifdef PCNET_DEBUG_BCR
1496 printf("pcnet_bcr_writew rap=%d val=0x%04x\n", rap, val);
1497#endif
1498 switch (rap) {
1499 case BCR_SWS:
1500 if (!(CSR_STOP(s) || CSR_SPND(s)))
1501 return;
1502 val &= ~0x0300;
1503 switch (val & 0x00ff) {
1504 case 0:
1505 val |= 0x0200;
1506 break;
1507 case 1:
1508 val |= 0x0100;
1509 break;
1510 case 2:
1511 case 3:
1512 val |= 0x0300;
1513 break;
1514 default:
1515 printf("Bad SWSTYLE=0x%02x\n", val & 0xff);
1516 val = 0x0200;
1517 break;
1518 }
1519#ifdef PCNET_DEBUG
1520 printf("BCR_SWS=0x%04x\n", val);
1521#endif
0b0404bf 1522 /* fall through */
e3c2613f
FB		 1523 case BCR_LNKST:
1524 case BCR_LED1:
1525 case BCR_LED2:
1526 case BCR_LED3:
1527 case BCR_MC:
1528 case BCR_FDC:
1529 case BCR_BSBC:
1530 case BCR_EECAS:
1531 case BCR_PLAT:
1532 s->bcr[rap] = val;
1533 break;
1534 default:
1535 break;
1536 }
1537}
1538
a4c75a21 1539uint32_t pcnet_bcr_readw(PCNetState *s, uint32_t rap)
e3c2613f
FB		 1540{
1541 uint32_t val;
1542 rap &= 127;
1543 switch (rap) {
1544 case BCR_LNKST:
1545 case BCR_LED1:
1546 case BCR_LED2:
1547 case BCR_LED3:
1548 val = s->bcr[rap] & ~0x8000;
1549 val |= (val & 0x017f & s->lnkst) ? 0x8000 : 0;
1550 break;
1551 default:
1552 val = rap < 32 ? s->bcr[rap] : 0;
1553 break;
1554 }
1555#ifdef PCNET_DEBUG_BCR
1556 printf("pcnet_bcr_readw rap=%d val=0x%04x\n", rap, val);
1557#endif
1558 return val;
1559}
1560
94e1a912 1561void pcnet_h_reset(void *opaque)
e3c2613f 1562{
91cc0295 1563 PCNetState *s = opaque;
e3c2613f
FB		 1564
1565 s->bcr[BCR_MSRDA] = 0x0005;
1566 s->bcr[BCR_MSWRA] = 0x0005;
1567 s->bcr[BCR_MC ] = 0x0002;
1568 s->bcr[BCR_LNKST] = 0x00c0;
1569 s->bcr[BCR_LED1 ] = 0x0084;
1570 s->bcr[BCR_LED2 ] = 0x0088;
1571 s->bcr[BCR_LED3 ] = 0x0090;
1572 s->bcr[BCR_FDC ] = 0x0000;
1573 s->bcr[BCR_BSBC ] = 0x9001;
1574 s->bcr[BCR_EECAS] = 0x0002;
1575 s->bcr[BCR_SWS ] = 0x0200;
1576 s->bcr[BCR_PLAT ] = 0xff06;
1577
1578 pcnet_s_reset(s);
de41ac92
JK		 1579 pcnet_update_irq(s);
1580 pcnet_poll_timer(s);
e3c2613f
FB		 1581}
1582
94e1a912 1583void pcnet_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
e3c2613f
FB		 1584{
1585 PCNetState *s = opaque;
1586 pcnet_poll_timer(s);
1587#ifdef PCNET_DEBUG_IO
1588 printf("pcnet_ioport_writew addr=0x%08x val=0x%04x\n", addr, val);
1589#endif
1590 if (!BCR_DWIO(s)) {
1591 switch (addr & 0x0f) {
1592 case 0x00: /* RDP */
1593 pcnet_csr_writew(s, s->rap, val);
1594 break;
1595 case 0x02:
1596 s->rap = val & 0x7f;
1597 break;
1598 case 0x06:
1599 pcnet_bcr_writew(s, s->rap, val);
1600 break;
1601 }
1602 }
1603 pcnet_update_irq(s);
1604}
1605
94e1a912 1606uint32_t pcnet_ioport_readw(void *opaque, uint32_t addr)
e3c2613f
FB		 1607{
1608 PCNetState *s = opaque;
1609 uint32_t val = -1;
1610 pcnet_poll_timer(s);
1611 if (!BCR_DWIO(s)) {
1612 switch (addr & 0x0f) {
1613 case 0x00: /* RDP */
1614 val = pcnet_csr_readw(s, s->rap);
1615 break;
1616 case 0x02:
1617 val = s->rap;
1618 break;
1619 case 0x04:
1620 pcnet_s_reset(s);
1621 val = 0;
1622 break;
1623 case 0x06:
1624 val = pcnet_bcr_readw(s, s->rap);
1625 break;
1626 }
1627 }
1628 pcnet_update_irq(s);
1629#ifdef PCNET_DEBUG_IO
1630 printf("pcnet_ioport_readw addr=0x%08x val=0x%04x\n", addr, val & 0xffff);
1631#endif
1632 return val;
1633}
1634
a4c75a21 1635void pcnet_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
e3c2613f
FB		 1636{
1637 PCNetState *s = opaque;
1638 pcnet_poll_timer(s);
1639#ifdef PCNET_DEBUG_IO
1640 printf("pcnet_ioport_writel addr=0x%08x val=0x%08x\n", addr, val);
1641#endif
1642 if (BCR_DWIO(s)) {
1643 switch (addr & 0x0f) {
1644 case 0x00: /* RDP */
1645 pcnet_csr_writew(s, s->rap, val & 0xffff);
1646 break;
1647 case 0x04:
1648 s->rap = val & 0x7f;
1649 break;
1650 case 0x0c:
1651 pcnet_bcr_writew(s, s->rap, val & 0xffff);
1652 break;
1653 }
1654 } else
1655 if ((addr & 0x0f) == 0) {
1656 /* switch device to dword i/o mode */
1657 pcnet_bcr_writew(s, BCR_BSBC, pcnet_bcr_readw(s, BCR_BSBC) | 0x0080);
1658#ifdef PCNET_DEBUG_IO
1659 printf("device switched into dword i/o mode\n");
3b46e624 1660#endif
e3c2613f
FB		 1661 }
1662 pcnet_update_irq(s);
1663}
1664
a4c75a21 1665uint32_t pcnet_ioport_readl(void *opaque, uint32_t addr)
e3c2613f
FB		 1666{
1667 PCNetState *s = opaque;
1668 uint32_t val = -1;
1669 pcnet_poll_timer(s);
3b46e624 1670 if (BCR_DWIO(s)) {
e3c2613f
FB		 1671 switch (addr & 0x0f) {
1672 case 0x00: /* RDP */
1673 val = pcnet_csr_readw(s, s->rap);
1674 break;
1675 case 0x04:
1676 val = s->rap;
1677 break;
1678 case 0x08:
1679 pcnet_s_reset(s);
1680 val = 0;
1681 break;
1682 case 0x0c:
1683 val = pcnet_bcr_readw(s, s->rap);
1684 break;
1685 }
1686 }
1687 pcnet_update_irq(s);
1688#ifdef PCNET_DEBUG_IO
1689 printf("pcnet_ioport_readl addr=0x%08x val=0x%08x\n", addr, val);
1690#endif
1691 return val;
1692}
1693
3d865059 1694static bool is_version_2(void *opaque, int version_id)
91cc0295 1695{
3d865059 1696 return version_id == 2;
91cc0295
FB		 1697}
1698
3d865059
JQ		 1699const VMStateDescription vmstate_pcnet = {
1700 .name = "pcnet",
1701 .version_id = 3,
1702 .minimum_version_id = 2,
1703 .minimum_version_id_old = 2,
1704 .fields = (VMStateField []) {
1705 VMSTATE_INT32(rap, PCNetState),
1706 VMSTATE_INT32(isr, PCNetState),
1707 VMSTATE_INT32(lnkst, PCNetState),
1708 VMSTATE_UINT32(rdra, PCNetState),
1709 VMSTATE_UINT32(tdra, PCNetState),
1710 VMSTATE_BUFFER(prom, PCNetState),
1711 VMSTATE_UINT16_ARRAY(csr, PCNetState, 128),
1712 VMSTATE_UINT16_ARRAY(bcr, PCNetState, 32),
1713 VMSTATE_UINT64(timer, PCNetState),
1714 VMSTATE_INT32(xmit_pos, PCNetState),
1715 VMSTATE_BUFFER(buffer, PCNetState),
1716 VMSTATE_UNUSED_TEST(is_version_2, 4),
1717 VMSTATE_INT32(tx_busy, PCNetState),
1718 VMSTATE_TIMER(poll_timer, PCNetState),
1719 VMSTATE_END_OF_LIST()
efb56cf7 1720 }
3d865059 1721};
0abaa7c1 1722
94e1a912 1723void pcnet_common_cleanup(PCNetState *d)
b946a153 1724{
1fa51482 1725 d->nic = NULL;
b946a153
AL		 1726}
1727
1fa51482 1728int pcnet_common_init(DeviceState *dev, PCNetState *s, NetClientInfo *info)
91cc0295 1729{
7165448a
WD		 1730 int i;
1731 uint16_t checksum;
1732
bc72ad67 1733 s->poll_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, pcnet_poll_timer, s);
9d07d757 1734
76224833 1735 qemu_macaddr_default_if_unset(&s->conf.macaddr);
f79f2bfc 1736 s->nic = qemu_new_nic(info, &s->conf, object_get_typename(OBJECT(dev)), dev->id, s);
b356f76d 1737 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
1ca4d09a
GN		 1738
1739 add_boot_device_path(s->conf.bootindex, dev, "/ethernet-phy@0");
1740
7165448a
WD		 1741 /* Initialize the PROM */
1742
1743 /*
1744 Datasheet: http://pdfdata.datasheetsite.com/web/24528/AM79C970A.pdf
1745 page 95
1746 */
1747 memcpy(s->prom, s->conf.macaddr.a, 6);
1748 /* Reserved Location: must be 00h */
1749 s->prom[6] = s->prom[7] = 0x00;
1750 /* Reserved Location: must be 00h */
1751 s->prom[8] = 0x00;
1752 /* Hardware ID: must be 11h if compatibility to AMD drivers is desired */
1753 s->prom[9] = 0x11;
1754 /* User programmable space, init with 0 */
1755 s->prom[10] = s->prom[11] = 0x00;
1756 /* LSByte of two-byte checksum, which is the sum of bytes 00h-0Bh
1757 and bytes 0Eh and 0Fh, must therefore be initialized with 0! */
1758 s->prom[12] = s->prom[13] = 0x00;
1759 /* Must be ASCII W (57h) if compatibility to AMD
1760 driver software is desired */
1761 s->prom[14] = s->prom[15] = 0x57;
1762
1763 for (i = 0, checksum = 0; i < 16; i++) {
1764 checksum += s->prom[i];
1765 }
1766 *(uint16_t *)&s->prom[12] = cpu_to_le16(checksum);
1767
9f2a8d7a
JK		 1768 s->lnkst = 0x40; /* initial link state: up */
1769
81a322d4 1770 return 0;
91cc0295 1771}
Empty description
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