]> Git Repo - qemu.git/blame - include/hw/pci-host/spapr.h
Merge remote-tracking branch 'remotes/weil/tags/pull-tci-20150826' into staging
[qemu.git] / include / hw / pci-host / spapr.h
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1/*
2 * QEMU SPAPR PCI BUS definitions
3 *
4 * Copyright (c) 2011 Alexey Kardashevskiy <[email protected]>
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19#if !defined(__HW_SPAPR_H__)
20#error Please include spapr.h before this file!
21#endif
22
23#if !defined(__HW_SPAPR_PCI_H__)
24#define __HW_SPAPR_PCI_H__
25
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26#include "hw/pci/pci.h"
27#include "hw/pci/pci_host.h"
0d09e41a 28#include "hw/ppc/xics.h"
3384f95c 29
8c9f64df 30#define TYPE_SPAPR_PCI_HOST_BRIDGE "spapr-pci-host-bridge"
9fc34ada 31#define TYPE_SPAPR_PCI_VFIO_HOST_BRIDGE "spapr-pci-vfio-host-bridge"
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32
33#define SPAPR_PCI_HOST_BRIDGE(obj) \
34 OBJECT_CHECK(sPAPRPHBState, (obj), TYPE_SPAPR_PCI_HOST_BRIDGE)
35
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36#define SPAPR_PCI_VFIO_HOST_BRIDGE(obj) \
37 OBJECT_CHECK(sPAPRPHBVFIOState, (obj), TYPE_SPAPR_PCI_VFIO_HOST_BRIDGE)
38
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39#define SPAPR_PCI_HOST_BRIDGE_CLASS(klass) \
40 OBJECT_CLASS_CHECK(sPAPRPHBClass, (klass), TYPE_SPAPR_PCI_HOST_BRIDGE)
41#define SPAPR_PCI_HOST_BRIDGE_GET_CLASS(obj) \
42 OBJECT_GET_CLASS(sPAPRPHBClass, (obj), TYPE_SPAPR_PCI_HOST_BRIDGE)
43
44typedef struct sPAPRPHBClass sPAPRPHBClass;
45typedef struct sPAPRPHBState sPAPRPHBState;
9fc34ada 46typedef struct sPAPRPHBVFIOState sPAPRPHBVFIOState;
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47
48struct sPAPRPHBClass {
49 PCIHostBridgeClass parent_class;
50
51 void (*finish_realize)(sPAPRPHBState *sphb, Error **errp);
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52 int (*eeh_set_option)(sPAPRPHBState *sphb, unsigned int addr, int option);
53 int (*eeh_get_state)(sPAPRPHBState *sphb, int *state);
54 int (*eeh_reset)(sPAPRPHBState *sphb, int option);
55 int (*eeh_configure)(sPAPRPHBState *sphb);
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56};
57
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58typedef struct spapr_pci_msi {
59 uint32_t first_irq;
60 uint32_t num;
61} spapr_pci_msi;
62
63typedef struct spapr_pci_msi_mig {
64 uint32_t key;
65 spapr_pci_msi value;
66} spapr_pci_msi_mig;
67
da6ccee4 68struct sPAPRPHBState {
67c332fd 69 PCIHostState parent_obj;
3384f95c 70
3e4ac968 71 uint32_t index;
3384f95c 72 uint64_t buid;
298a9710 73 char *dtbusname;
7619c7b0 74 bool dr_enabled;
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75
76 MemoryRegion memspace, iospace;
a8170e5e 77 hwaddr mem_win_addr, mem_win_size, io_win_addr, io_win_size;
8c46f7ec 78 MemoryRegion memwindow, iowindow, msiwindow;
0ee2c058 79
5c4cbcf2 80 uint32_t dma_liobn;
e00387d5 81 AddressSpace iommu_as;
cca7fad5 82 MemoryRegion iommu_root;
3384f95c 83
1112cf94 84 struct spapr_pci_lsi {
a307d594 85 uint32_t irq;
7fb0bd34 86 } lsi_table[PCI_NUM_PINS];
3384f95c 87
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88 GHashTable *msi;
89 /* Temporary cache for migration purposes */
90 int32_t msi_devs_num;
91 spapr_pci_msi_mig *msi_devs;
0ee2c058 92
3384f95c 93 QLIST_ENTRY(sPAPRPHBState) list;
da6ccee4 94};
3384f95c 95
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96struct sPAPRPHBVFIOState {
97 sPAPRPHBState phb;
98
99 int32_t iommugroupid;
100};
101
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102#define SPAPR_PCI_MAX_INDEX 255
103
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104#define SPAPR_PCI_BASE_BUID 0x800000020000000ULL
105
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106#define SPAPR_PCI_MEM_WIN_BUS_OFFSET 0x80000000ULL
107
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108#define SPAPR_PCI_WINDOW_BASE 0x10000000000ULL
109#define SPAPR_PCI_WINDOW_SPACING 0x1000000000ULL
110#define SPAPR_PCI_MMIO_WIN_OFF 0xA0000000
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111#define SPAPR_PCI_MMIO_WIN_SIZE (SPAPR_PCI_WINDOW_SPACING - \
112 SPAPR_PCI_MEM_WIN_BUS_OFFSET)
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113#define SPAPR_PCI_IO_WIN_OFF 0x80000000
114#define SPAPR_PCI_IO_WIN_SIZE 0x10000
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115
116#define SPAPR_PCI_MSI_WINDOW 0x40000000000ULL
caae58cb 117
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118#define SPAPR_PCI_DMA32_SIZE 0x40000000
119
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120static inline qemu_irq spapr_phb_lsi_qirq(struct sPAPRPHBState *phb, int pin)
121{
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122 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
123
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124 return xics_get_qirq(spapr->icp, phb->lsi_table[pin].irq);
125}
126
28e02042 127PCIHostState *spapr_create_phb(sPAPRMachineState *spapr, int index);
3384f95c 128
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129int spapr_populate_pci_dt(sPAPRPHBState *phb,
130 uint32_t xics_phandle,
131 void *fdt);
3384f95c 132
28e02042 133void spapr_pci_msi_init(sPAPRMachineState *spapr, hwaddr addr);
f1c2dc7c 134
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135void spapr_pci_rtas_init(void);
136
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137sPAPRPHBState *spapr_pci_find_phb(sPAPRMachineState *spapr, uint64_t buid);
138PCIDevice *spapr_pci_find_dev(sPAPRMachineState *spapr, uint64_t buid,
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139 uint32_t config_addr);
140
3384f95c 141#endif /* __HW_SPAPR_PCI_H__ */
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