]> Git Repo - qemu.git/blame - target/lm32/cpu.c
Merge remote-tracking branch 'remotes/stefanberger/tags/pull-tpm-2017-10-24-1' into...
[qemu.git] / target / lm32 / cpu.c
CommitLineData
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1/*
2 * QEMU LatticeMico32 CPU
3 *
4 * Copyright (c) 2012 SUSE LINUX Products GmbH
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see
18 * <http://www.gnu.org/licenses/lgpl-2.1.html>
19 */
20
ea99dde1 21#include "qemu/osdep.h"
da34e65c 22#include "qapi/error.h"
0347d689 23#include "cpu.h"
fc0ced2f 24#include "qemu-common.h"
63c91552 25#include "exec/exec-all.h"
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26
27
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28static void lm32_cpu_set_pc(CPUState *cs, vaddr value)
29{
30 LM32CPU *cpu = LM32_CPU(cs);
31
32 cpu->env.pc = value;
33}
34
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35/* Sort alphabetically by type name. */
36static gint lm32_cpu_list_compare(gconstpointer a, gconstpointer b)
37{
38 ObjectClass *class_a = (ObjectClass *)a;
39 ObjectClass *class_b = (ObjectClass *)b;
40 const char *name_a, *name_b;
41
42 name_a = object_class_get_name(class_a);
43 name_b = object_class_get_name(class_b);
44 return strcmp(name_a, name_b);
45}
46
47static void lm32_cpu_list_entry(gpointer data, gpointer user_data)
48{
49 ObjectClass *oc = data;
50 CPUListState *s = user_data;
51 const char *typename = object_class_get_name(oc);
52 char *name;
53
54 name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_LM32_CPU));
55 (*s->cpu_fprintf)(s->file, " %s\n", name);
56 g_free(name);
57}
58
59
60void lm32_cpu_list(FILE *f, fprintf_function cpu_fprintf)
61{
62 CPUListState s = {
63 .file = f,
64 .cpu_fprintf = cpu_fprintf,
65 };
66 GSList *list;
67
68 list = object_class_get_list(TYPE_LM32_CPU, false);
69 list = g_slist_sort(list, lm32_cpu_list_compare);
70 (*cpu_fprintf)(f, "Available CPUs:\n");
71 g_slist_foreach(list, lm32_cpu_list_entry, &s);
72 g_slist_free(list);
73}
74
75static void lm32_cpu_init_cfg_reg(LM32CPU *cpu)
76{
77 CPULM32State *env = &cpu->env;
78 uint32_t cfg = 0;
79
80 if (cpu->features & LM32_FEATURE_MULTIPLY) {
81 cfg |= CFG_M;
82 }
83
84 if (cpu->features & LM32_FEATURE_DIVIDE) {
85 cfg |= CFG_D;
86 }
87
88 if (cpu->features & LM32_FEATURE_SHIFT) {
89 cfg |= CFG_S;
90 }
91
92 if (cpu->features & LM32_FEATURE_SIGN_EXTEND) {
93 cfg |= CFG_X;
94 }
95
96 if (cpu->features & LM32_FEATURE_I_CACHE) {
97 cfg |= CFG_IC;
98 }
99
100 if (cpu->features & LM32_FEATURE_D_CACHE) {
101 cfg |= CFG_DC;
102 }
103
104 if (cpu->features & LM32_FEATURE_CYCLE_COUNT) {
105 cfg |= CFG_CC;
106 }
107
108 cfg |= (cpu->num_interrupts << CFG_INT_SHIFT);
109 cfg |= (cpu->num_breakpoints << CFG_BP_SHIFT);
110 cfg |= (cpu->num_watchpoints << CFG_WP_SHIFT);
111 cfg |= (cpu->revision << CFG_REV_SHIFT);
112
113 env->cfg = cfg;
114}
115
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116static bool lm32_cpu_has_work(CPUState *cs)
117{
118 return cs->interrupt_request & CPU_INTERRUPT_HARD;
119}
120
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121/* CPUClass::reset() */
122static void lm32_cpu_reset(CPUState *s)
123{
124 LM32CPU *cpu = LM32_CPU(s);
125 LM32CPUClass *lcc = LM32_CPU_GET_CLASS(cpu);
126 CPULM32State *env = &cpu->env;
127
128 lcc->parent_reset(s);
129
3eab1690 130 /* reset cpu state */
1f5c00cf 131 memset(env, 0, offsetof(CPULM32State, end_reset_fields));
a5b0f6d5 132
34f4aa83 133 lm32_cpu_init_cfg_reg(cpu);
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134}
135
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136static void lm32_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
137{
138 info->mach = bfd_mach_lm32;
139 info->print_insn = print_insn_lm32;
140}
141
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142static void lm32_cpu_realizefn(DeviceState *dev, Error **errp)
143{
14a10fc3 144 CPUState *cs = CPU(dev);
9c23169e 145 LM32CPUClass *lcc = LM32_CPU_GET_CLASS(dev);
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146 Error *local_err = NULL;
147
148 cpu_exec_realizefn(cs, &local_err);
149 if (local_err != NULL) {
150 error_propagate(errp, local_err);
151 return;
152 }
9c23169e 153
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154 cpu_reset(cs);
155
156 qemu_init_vcpu(cs);
9c23169e 157
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158 lcc->parent_realize(dev, errp);
159}
160
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161static void lm32_cpu_initfn(Object *obj)
162{
c05efcb1 163 CPUState *cs = CPU(obj);
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164 LM32CPU *cpu = LM32_CPU(obj);
165 CPULM32State *env = &cpu->env;
166
c05efcb1 167 cs->env_ptr = env;
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168
169 env->flags = 0;
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170}
171
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172static void lm32_basic_cpu_initfn(Object *obj)
173{
174 LM32CPU *cpu = LM32_CPU(obj);
175
176 cpu->revision = 3;
177 cpu->num_interrupts = 32;
178 cpu->num_breakpoints = 4;
179 cpu->num_watchpoints = 4;
180 cpu->features = LM32_FEATURE_SHIFT
181 | LM32_FEATURE_SIGN_EXTEND
182 | LM32_FEATURE_CYCLE_COUNT;
183}
184
185static void lm32_standard_cpu_initfn(Object *obj)
186{
187 LM32CPU *cpu = LM32_CPU(obj);
188
189 cpu->revision = 3;
190 cpu->num_interrupts = 32;
191 cpu->num_breakpoints = 4;
192 cpu->num_watchpoints = 4;
193 cpu->features = LM32_FEATURE_MULTIPLY
194 | LM32_FEATURE_DIVIDE
195 | LM32_FEATURE_SHIFT
196 | LM32_FEATURE_SIGN_EXTEND
197 | LM32_FEATURE_I_CACHE
198 | LM32_FEATURE_CYCLE_COUNT;
199}
200
201static void lm32_full_cpu_initfn(Object *obj)
202{
203 LM32CPU *cpu = LM32_CPU(obj);
204
205 cpu->revision = 3;
206 cpu->num_interrupts = 32;
207 cpu->num_breakpoints = 4;
208 cpu->num_watchpoints = 4;
209 cpu->features = LM32_FEATURE_MULTIPLY
210 | LM32_FEATURE_DIVIDE
211 | LM32_FEATURE_SHIFT
212 | LM32_FEATURE_SIGN_EXTEND
213 | LM32_FEATURE_I_CACHE
214 | LM32_FEATURE_D_CACHE
215 | LM32_FEATURE_CYCLE_COUNT;
216}
217
218typedef struct LM32CPUInfo {
219 const char *name;
220 void (*initfn)(Object *obj);
221} LM32CPUInfo;
222
223static const LM32CPUInfo lm32_cpus[] = {
224 {
225 .name = "lm32-basic",
226 .initfn = lm32_basic_cpu_initfn,
227 },
228 {
229 .name = "lm32-standard",
230 .initfn = lm32_standard_cpu_initfn,
231 },
232 {
233 .name = "lm32-full",
234 .initfn = lm32_full_cpu_initfn,
235 },
236};
237
238static ObjectClass *lm32_cpu_class_by_name(const char *cpu_model)
239{
240 ObjectClass *oc;
241 char *typename;
242
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243 typename = g_strdup_printf("%s-" TYPE_LM32_CPU, cpu_model);
244 oc = object_class_by_name(typename);
245 g_free(typename);
246 if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_LM32_CPU) ||
247 object_class_is_abstract(oc))) {
248 oc = NULL;
249 }
250 return oc;
251}
252
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253static void lm32_cpu_class_init(ObjectClass *oc, void *data)
254{
255 LM32CPUClass *lcc = LM32_CPU_CLASS(oc);
256 CPUClass *cc = CPU_CLASS(oc);
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257 DeviceClass *dc = DEVICE_CLASS(oc);
258
259 lcc->parent_realize = dc->realize;
260 dc->realize = lm32_cpu_realizefn;
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261
262 lcc->parent_reset = cc->reset;
263 cc->reset = lm32_cpu_reset;
97a8ea5a 264
34f4aa83 265 cc->class_by_name = lm32_cpu_class_by_name;
8c2e1b00 266 cc->has_work = lm32_cpu_has_work;
97a8ea5a 267 cc->do_interrupt = lm32_cpu_do_interrupt;
e9854c39 268 cc->cpu_exec_interrupt = lm32_cpu_exec_interrupt;
878096ee 269 cc->dump_state = lm32_cpu_dump_state;
f45748f1 270 cc->set_pc = lm32_cpu_set_pc;
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271 cc->gdb_read_register = lm32_cpu_gdb_read_register;
272 cc->gdb_write_register = lm32_cpu_gdb_write_register;
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273#ifdef CONFIG_USER_ONLY
274 cc->handle_mmu_fault = lm32_cpu_handle_mmu_fault;
275#else
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276 cc->get_phys_page_debug = lm32_cpu_get_phys_page_debug;
277 cc->vmsd = &vmstate_lm32_cpu;
278#endif
a0e372f0 279 cc->gdb_num_core_regs = 32 + 7;
2472b6c0 280 cc->gdb_stop_before_watchpoint = true;
86025ee4 281 cc->debug_excp_handler = lm32_debug_excp_handler;
20984673 282 cc->disas_set_info = lm32_cpu_disas_set_info;
55c3ceef 283 cc->tcg_initialize = lm32_translate_init;
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284}
285
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286static void lm32_register_cpu_type(const LM32CPUInfo *info)
287{
288 TypeInfo type_info = {
289 .parent = TYPE_LM32_CPU,
290 .instance_init = info->initfn,
291 };
292
293 type_info.name = g_strdup_printf("%s-" TYPE_LM32_CPU, info->name);
294 type_register(&type_info);
295 g_free((void *)type_info.name);
296}
297
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298static const TypeInfo lm32_cpu_type_info = {
299 .name = TYPE_LM32_CPU,
300 .parent = TYPE_CPU,
301 .instance_size = sizeof(LM32CPU),
8d7d505a 302 .instance_init = lm32_cpu_initfn,
34f4aa83 303 .abstract = true,
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304 .class_size = sizeof(LM32CPUClass),
305 .class_init = lm32_cpu_class_init,
306};
307
308static void lm32_cpu_register_types(void)
309{
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310 int i;
311
fc0ced2f 312 type_register_static(&lm32_cpu_type_info);
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313 for (i = 0; i < ARRAY_SIZE(lm32_cpus); i++) {
314 lm32_register_cpu_type(&lm32_cpus[i]);
315 }
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316}
317
318type_init(lm32_cpu_register_types)
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