[qemu.git] / target-microblaze / mmu.c

/*
 *  Microblaze MMU emulation for qemu.
 *
 *  Copyright (c) 2009 Edgar E. Iglesias
 *  Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "cpu.h"

#define D(x)

static unsigned int tlb_decode_size(unsigned int f)
{
    static const unsigned int sizes[] = {
        1 * 1024, 4 * 1024, 16 * 1024, 64 * 1024, 256 * 1024,
        1 * 1024 * 1024, 4 * 1024 * 1024, 16 * 1024 * 1024
    };
    assert(f < ARRAY_SIZE(sizes));
    return sizes[f];
}

static void mmu_flush_idx(CPUMBState *env, unsigned int idx)
{
    CPUState *cs = CPU(mb_env_get_cpu(env));
    struct microblaze_mmu *mmu = &env->mmu;
    unsigned int tlb_size;
    uint32_t tlb_tag, end, t;

    t = mmu->rams[RAM_TAG][idx];
    if (!(t & TLB_VALID))
        return;

    tlb_tag = t & TLB_EPN_MASK;
    tlb_size = tlb_decode_size((t & TLB_PAGESZ_MASK) >> 7);
    end = tlb_tag + tlb_size;

    while (tlb_tag < end) {
        tlb_flush_page(cs, tlb_tag);
        tlb_tag += TARGET_PAGE_SIZE;
    }
}

static void mmu_change_pid(CPUMBState *env, unsigned int newpid) 
{
    struct microblaze_mmu *mmu = &env->mmu;
    unsigned int i;
    uint32_t t;

    if (newpid & ~0xff)
        qemu_log("Illegal rpid=%x\n", newpid);

    for (i = 0; i < ARRAY_SIZE(mmu->rams[RAM_TAG]); i++) {
        /* Lookup and decode.  */
        t = mmu->rams[RAM_TAG][i];
        if (t & TLB_VALID) {
            if (mmu->tids[i] && ((mmu->regs[MMU_R_PID] & 0xff) == mmu->tids[i]))
                mmu_flush_idx(env, i);
        }
    }
}

/* rw - 0 = read, 1 = write, 2 = fetch.  */
unsigned int mmu_translate(struct microblaze_mmu *mmu,
                           struct microblaze_mmu_lookup *lu,
                           target_ulong vaddr, int rw, int mmu_idx)
{
    unsigned int i, hit = 0;
    unsigned int tlb_ex = 0, tlb_wr = 0, tlb_zsel;
    unsigned int tlb_size;
    uint32_t tlb_tag, tlb_rpn, mask, t0;

    lu->err = ERR_MISS;
    for (i = 0; i < ARRAY_SIZE(mmu->rams[RAM_TAG]); i++) {
        uint32_t t, d;

        /* Lookup and decode.  */
        t = mmu->rams[RAM_TAG][i];
        D(qemu_log("TLB %d valid=%d\n", i, t & TLB_VALID));
        if (t & TLB_VALID) {
            tlb_size = tlb_decode_size((t & TLB_PAGESZ_MASK) >> 7);
            if (tlb_size < TARGET_PAGE_SIZE) {
                qemu_log("%d pages not supported\n", tlb_size);
                abort();
            }

            mask = ~(tlb_size - 1);
            tlb_tag = t & TLB_EPN_MASK;
            if ((vaddr & mask) != (tlb_tag & mask)) {
                D(qemu_log("TLB %d vaddr=%x != tag=%x\n",
                           i, vaddr & mask, tlb_tag & mask));
                continue;
            }
            if (mmu->tids[i]
                && ((mmu->regs[MMU_R_PID] & 0xff) != mmu->tids[i])) {
                D(qemu_log("TLB %d pid=%x != tid=%x\n",
                           i, mmu->regs[MMU_R_PID], mmu->tids[i]));
                continue;
            }

            /* Bring in the data part.  */
            d = mmu->rams[RAM_DATA][i];
            tlb_ex = d & TLB_EX;
            tlb_wr = d & TLB_WR;

            /* Now let's see if there is a zone that overrides the protbits.  */
            tlb_zsel = (d >> 4) & 0xf;
            t0 = mmu->regs[MMU_R_ZPR] >> (30 - (tlb_zsel * 2));
            t0 &= 0x3;

            if (tlb_zsel > mmu->c_mmu_zones) {
                qemu_log("tlb zone select out of range! %d\n", tlb_zsel);
                t0 = 1; /* Ignore.  */
            }

            if (mmu->c_mmu == 1) {
                t0 = 1; /* Zones are disabled.  */
            }

            switch (t0) {
                case 0:
                    if (mmu_idx == MMU_USER_IDX)
                        continue;
                    break;
                case 2:
                    if (mmu_idx != MMU_USER_IDX) {
                        tlb_ex = 1;
                        tlb_wr = 1;
                    }
                    break;
                case 3:
                    tlb_ex = 1;
                    tlb_wr = 1;
                    break;
                default: break;
            }

            lu->err = ERR_PROT;
            lu->prot = PAGE_READ;
            if (tlb_wr)
                lu->prot |= PAGE_WRITE;
            else if (rw == 1)
                goto done;
            if (tlb_ex)
                lu->prot |=PAGE_EXEC;
            else if (rw == 2) {
                goto done;
            }

            tlb_rpn = d & TLB_RPN_MASK;

            lu->vaddr = tlb_tag;
            lu->paddr = tlb_rpn;
            lu->size = tlb_size;
            lu->err = ERR_HIT;
            lu->idx = i;
            hit = 1;
            goto done;
        }
    }
done:
    D(qemu_log("MMU vaddr=%x rw=%d tlb_wr=%d tlb_ex=%d hit=%d\n",
              vaddr, rw, tlb_wr, tlb_ex, hit));
    return hit;
}

/* Writes/reads to the MMU's special regs end up here.  */
uint32_t mmu_read(CPUMBState *env, uint32_t rn)
{
    unsigned int i;
    uint32_t r;

    if (env->mmu.c_mmu < 2 || !env->mmu.c_mmu_tlb_access) {
        qemu_log("MMU access on MMU-less system\n");
        return 0;
    }

    switch (rn) {
        /* Reads to HI/LO trig reads from the mmu rams.  */
        case MMU_R_TLBLO:
        case MMU_R_TLBHI:
            if (!(env->mmu.c_mmu_tlb_access & 1)) {
                qemu_log("Invalid access to MMU reg %d\n", rn);
                return 0;
            }

            i = env->mmu.regs[MMU_R_TLBX] & 0xff;
            r = env->mmu.rams[rn & 1][i];
            if (rn == MMU_R_TLBHI)
                env->mmu.regs[MMU_R_PID] = env->mmu.tids[i];
            break;
        case MMU_R_PID:
        case MMU_R_ZPR:
            if (!(env->mmu.c_mmu_tlb_access & 1)) {
                qemu_log("Invalid access to MMU reg %d\n", rn);
                return 0;
            }
            r = env->mmu.regs[rn];
            break;
        default:
            r = env->mmu.regs[rn];
            break;
    }
    D(qemu_log("%s rn=%d=%x\n", __func__, rn, r));
    return r;
}

void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
{
    unsigned int i;
    D(qemu_log("%s rn=%d=%x old=%x\n", __func__, rn, v, env->mmu.regs[rn]));

    if (env->mmu.c_mmu < 2 || !env->mmu.c_mmu_tlb_access) {
        qemu_log("MMU access on MMU-less system\n");
        return;
    }

    switch (rn) {
        /* Writes to HI/LO trig writes to the mmu rams.  */
        case MMU_R_TLBLO:
        case MMU_R_TLBHI:
            i = env->mmu.regs[MMU_R_TLBX] & 0xff;
            if (rn == MMU_R_TLBHI) {
                if (i < 3 && !(v & TLB_VALID) && qemu_loglevel_mask(~0))
                    qemu_log("invalidating index %x at pc=%x\n",
                             i, env->sregs[SR_PC]);
                env->mmu.tids[i] = env->mmu.regs[MMU_R_PID] & 0xff;
                mmu_flush_idx(env, i);
            }
            env->mmu.rams[rn & 1][i] = v;

            D(qemu_log("%s ram[%d][%d]=%x\n", __func__, rn & 1, i, v));
            break;
        case MMU_R_ZPR:
            if (env->mmu.c_mmu_tlb_access <= 1) {
                qemu_log("Invalid access to MMU reg %d\n", rn);
                return;
            }

            /* Changes to the zone protection reg flush the QEMU TLB.
               Fortunately, these are very uncommon.  */
            if (v != env->mmu.regs[rn]) {
                tlb_flush(env, 1);
            }
            env->mmu.regs[rn] = v;
            break;
        case MMU_R_PID:
            if (env->mmu.c_mmu_tlb_access <= 1) {
                qemu_log("Invalid access to MMU reg %d\n", rn);
                return;
            }

            if (v != env->mmu.regs[rn]) {
                mmu_change_pid(env, v);
                env->mmu.regs[rn] = v;
            }
            break;
        case MMU_R_TLBSX:
        {
            struct microblaze_mmu_lookup lu;
            int hit;

            if (env->mmu.c_mmu_tlb_access <= 1) {
                qemu_log("Invalid access to MMU reg %d\n", rn);
                return;
            }

            hit = mmu_translate(&env->mmu, &lu,
                                v & TLB_EPN_MASK, 0, cpu_mmu_index(env));
            if (hit) {
                env->mmu.regs[MMU_R_TLBX] = lu.idx;
            } else
                env->mmu.regs[MMU_R_TLBX] |= 0x80000000;
            break;
        }
        default:
            env->mmu.regs[rn] = v;
            break;
   }
}

void mmu_init(struct microblaze_mmu *mmu)
{
    int i;
    for (i = 0; i < ARRAY_SIZE(mmu->regs); i++) {
        mmu->regs[i] = 0;
    }
}
Commit	Line	Data
afeeceb0 EI	1	/*
	2	* Microblaze MMU emulation for qemu.
	3	*
	4	* Copyright (c) 2009 Edgar E. Iglesias
dadc1064	5	* Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
afeeceb0 EI	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* Lesser General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
8167ee88	18	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
afeeceb0	19	*/
afeeceb0	20
afeeceb0	21	#include "cpu.h"
afeeceb0 EI	22
	23	#define D(x)
	24
	25	static unsigned int tlb_decode_size(unsigned int f)
	26	{
	27	static const unsigned int sizes[] = {
	28	1 * 1024, 4 * 1024, 16 * 1024, 64 * 1024, 256 * 1024,
	29	1 * 1024 * 1024, 4 * 1024 * 1024, 16 * 1024 * 1024
	30	};
	31	assert(f < ARRAY_SIZE(sizes));
	32	return sizes[f];
	33	}
	34
68cee38a	35	static void mmu_flush_idx(CPUMBState *env, unsigned int idx)
afeeceb0	36	{
31b030d4	37	CPUState *cs = CPU(mb_env_get_cpu(env));
afeeceb0 EI	38	struct microblaze_mmu *mmu = &env->mmu;
	39	unsigned int tlb_size;
	40	uint32_t tlb_tag, end, t;
	41
	42	t = mmu->rams[RAM_TAG][idx];
	43	if (!(t & TLB_VALID))
	44	return;
	45
	46	tlb_tag = t & TLB_EPN_MASK;
	47	tlb_size = tlb_decode_size((t & TLB_PAGESZ_MASK) >> 7);
	48	end = tlb_tag + tlb_size;
	49
	50	while (tlb_tag < end) {
31b030d4	51	tlb_flush_page(cs, tlb_tag);
afeeceb0 EI	52	tlb_tag += TARGET_PAGE_SIZE;
	53	}
	54	}
	55
68cee38a	56	static void mmu_change_pid(CPUMBState *env, unsigned int newpid)
afeeceb0 EI	57	{
	58	struct microblaze_mmu *mmu = &env->mmu;
	59	unsigned int i;
183aa454	60	uint32_t t;
afeeceb0 EI	61
	62	if (newpid & ~0xff)
	63	qemu_log("Illegal rpid=%x\n", newpid);
	64
	65	for (i = 0; i < ARRAY_SIZE(mmu->rams[RAM_TAG]); i++) {
	66	/* Lookup and decode. */
	67	t = mmu->rams[RAM_TAG][i];
	68	if (t & TLB_VALID) {
afeeceb0 EI	69	if (mmu->tids[i] && ((mmu->regs[MMU_R_PID] & 0xff) == mmu->tids[i]))
	70	mmu_flush_idx(env, i);
	71	}
	72	}
	73	}
	74
	75	/* rw - 0 = read, 1 = write, 2 = fetch. */
	76	unsigned int mmu_translate(struct microblaze_mmu *mmu,
	77	struct microblaze_mmu_lookup *lu,
	78	target_ulong vaddr, int rw, int mmu_idx)
	79	{
	80	unsigned int i, hit = 0;
	81	unsigned int tlb_ex = 0, tlb_wr = 0, tlb_zsel;
	82	unsigned int tlb_size;
	83	uint32_t tlb_tag, tlb_rpn, mask, t0;
	84
	85	lu->err = ERR_MISS;
	86	for (i = 0; i < ARRAY_SIZE(mmu->rams[RAM_TAG]); i++) {
	87	uint32_t t, d;
	88
	89	/* Lookup and decode. */
	90	t = mmu->rams[RAM_TAG][i];
	91	D(qemu_log("TLB %d valid=%d\n", i, t & TLB_VALID));
	92	if (t & TLB_VALID) {
	93	tlb_size = tlb_decode_size((t & TLB_PAGESZ_MASK) >> 7);
	94	if (tlb_size < TARGET_PAGE_SIZE) {
	95	qemu_log("%d pages not supported\n", tlb_size);
	96	abort();
	97	}
	98
	99	mask = ~(tlb_size - 1);
	100	tlb_tag = t & TLB_EPN_MASK;
	101	if ((vaddr & mask) != (tlb_tag & mask)) {
	102	D(qemu_log("TLB %d vaddr=%x != tag=%x\n",
	103	i, vaddr & mask, tlb_tag & mask));
	104	continue;
	105	}
	106	if (mmu->tids[i]
	107	&& ((mmu->regs[MMU_R_PID] & 0xff) != mmu->tids[i])) {
	108	D(qemu_log("TLB %d pid=%x != tid=%x\n",
	109	i, mmu->regs[MMU_R_PID], mmu->tids[i]));
	110	continue;
	111	}
	112
	113	/* Bring in the data part. */
	114	d = mmu->rams[RAM_DATA][i];
	115	tlb_ex = d & TLB_EX;
	116	tlb_wr = d & TLB_WR;
	117
e03ba136	118	/* Now let's see if there is a zone that overrides the protbits. */
afeeceb0 EI	119	tlb_zsel = (d >> 4) & 0xf;
	120	t0 = mmu->regs[MMU_R_ZPR] >> (30 - (tlb_zsel * 2));
	121	t0 &= 0x3;
3c50a71f EI	122
	123	if (tlb_zsel > mmu->c_mmu_zones) {
	124	qemu_log("tlb zone select out of range! %d\n", tlb_zsel);
	125	t0 = 1; /* Ignore. */
	126	}
	127
	128	if (mmu->c_mmu == 1) {
	129	t0 = 1; /* Zones are disabled. */
	130	}
	131
afeeceb0 EI	132	switch (t0) {
	133	case 0:
	134	if (mmu_idx == MMU_USER_IDX)
	135	continue;
	136	break;
	137	case 2:
	138	if (mmu_idx != MMU_USER_IDX) {
	139	tlb_ex = 1;
	140	tlb_wr = 1;
	141	}
	142	break;
	143	case 3:
	144	tlb_ex = 1;
	145	tlb_wr = 1;
	146	break;
3c50a71f	147	default: break;
afeeceb0 EI	148	}
afeeceb0 EI	149
afeeceb0 EI	150	lu->err = ERR_PROT;
	151	lu->prot = PAGE_READ;
	152	if (tlb_wr)
	153	lu->prot \|= PAGE_WRITE;
	154	else if (rw == 1)
	155	goto done;
	156	if (tlb_ex)
	157	lu->prot \|=PAGE_EXEC;
	158	else if (rw == 2) {
	159	goto done;
	160	}
	161
	162	tlb_rpn = d & TLB_RPN_MASK;
	163
	164	lu->vaddr = tlb_tag;
	165	lu->paddr = tlb_rpn;
	166	lu->size = tlb_size;
	167	lu->err = ERR_HIT;
	168	lu->idx = i;
	169	hit = 1;
	170	goto done;
	171	}
	172	}
	173	done:
	174	D(qemu_log("MMU vaddr=%x rw=%d tlb_wr=%d tlb_ex=%d hit=%d\n",
	175	vaddr, rw, tlb_wr, tlb_ex, hit));
	176	return hit;
	177	}
	178
	179	/* Writes/reads to the MMU's special regs end up here. */
68cee38a	180	uint32_t mmu_read(CPUMBState *env, uint32_t rn)
afeeceb0 EI	181	{
	182	unsigned int i;
	183	uint32_t r;
	184
3c50a71f EI	185	if (env->mmu.c_mmu < 2 \|\| !env->mmu.c_mmu_tlb_access) {
	186	qemu_log("MMU access on MMU-less system\n");
	187	return 0;
	188	}
	189
afeeceb0 EI	190	switch (rn) {
	191	/* Reads to HI/LO trig reads from the mmu rams. */
	192	case MMU_R_TLBLO:
	193	case MMU_R_TLBHI:
3c50a71f EI	194	if (!(env->mmu.c_mmu_tlb_access & 1)) {
	195	qemu_log("Invalid access to MMU reg %d\n", rn);
	196	return 0;
	197	}
	198
afeeceb0 EI	199	i = env->mmu.regs[MMU_R_TLBX] & 0xff;
	200	r = env->mmu.rams[rn & 1][i];
	201	if (rn == MMU_R_TLBHI)
	202	env->mmu.regs[MMU_R_PID] = env->mmu.tids[i];
	203	break;
3c50a71f EI	204	case MMU_R_PID:
	205	case MMU_R_ZPR:
	206	if (!(env->mmu.c_mmu_tlb_access & 1)) {
	207	qemu_log("Invalid access to MMU reg %d\n", rn);
	208	return 0;
	209	}
	210	r = env->mmu.regs[rn];
	211	break;
afeeceb0 EI	212	default:
	213	r = env->mmu.regs[rn];
	214	break;
	215	}
	216	D(qemu_log("%s rn=%d=%x\n", __func__, rn, r));
	217	return r;
	218	}
	219
68cee38a	220	void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
afeeceb0 EI	221	{
	222	unsigned int i;
	223	D(qemu_log("%s rn=%d=%x old=%x\n", __func__, rn, v, env->mmu.regs[rn]));
	224
3c50a71f EI	225	if (env->mmu.c_mmu < 2 \|\| !env->mmu.c_mmu_tlb_access) {
	226	qemu_log("MMU access on MMU-less system\n");
	227	return;
	228	}
	229
afeeceb0 EI	230	switch (rn) {
	231	/* Writes to HI/LO trig writes to the mmu rams. */
	232	case MMU_R_TLBLO:
	233	case MMU_R_TLBHI:
	234	i = env->mmu.regs[MMU_R_TLBX] & 0xff;
	235	if (rn == MMU_R_TLBHI) {
	236	if (i < 3 && !(v & TLB_VALID) && qemu_loglevel_mask(~0))
	237	qemu_log("invalidating index %x at pc=%x\n",
	238	i, env->sregs[SR_PC]);
	239	env->mmu.tids[i] = env->mmu.regs[MMU_R_PID] & 0xff;
	240	mmu_flush_idx(env, i);
	241	}
	242	env->mmu.rams[rn & 1][i] = v;
	243
	244	D(qemu_log("%s ram[%d][%d]=%x\n", __func__, rn & 1, i, v));
	245	break;
	246	case MMU_R_ZPR:
3c50a71f EI	247	if (env->mmu.c_mmu_tlb_access <= 1) {
	248	qemu_log("Invalid access to MMU reg %d\n", rn);
	249	return;
	250	}
	251
d0f3654f EI	252	/* Changes to the zone protection reg flush the QEMU TLB.
	253	Fortunately, these are very uncommon. */
	254	if (v != env->mmu.regs[rn]) {
	255	tlb_flush(env, 1);
	256	}
	257	env->mmu.regs[rn] = v;
	258	break;
afeeceb0	259	case MMU_R_PID:
3c50a71f EI	260	if (env->mmu.c_mmu_tlb_access <= 1) {
	261	qemu_log("Invalid access to MMU reg %d\n", rn);
	262	return;
	263	}
	264
afeeceb0 EI	265	if (v != env->mmu.regs[rn]) {
	266	mmu_change_pid(env, v);
	267	env->mmu.regs[rn] = v;
	268	}
	269	break;
	270	case MMU_R_TLBSX:
	271	{
	272	struct microblaze_mmu_lookup lu;
	273	int hit;
3c50a71f EI	274
	275	if (env->mmu.c_mmu_tlb_access <= 1) {
	276	qemu_log("Invalid access to MMU reg %d\n", rn);
	277	return;
	278	}
	279
afeeceb0 EI	280	hit = mmu_translate(&env->mmu, &lu,
	281	v & TLB_EPN_MASK, 0, cpu_mmu_index(env));
	282	if (hit) {
	283	env->mmu.regs[MMU_R_TLBX] = lu.idx;
	284	} else
	285	env->mmu.regs[MMU_R_TLBX] \|= 0x80000000;
	286	break;
	287	}
	288	default:
	289	env->mmu.regs[rn] = v;
	290	break;
	291	}
	292	}
	293
	294	void mmu_init(struct microblaze_mmu *mmu)
	295	{
3c50a71f EI	296	int i;
	297	for (i = 0; i < ARRAY_SIZE(mmu->regs); i++) {
	298	mmu->regs[i] = 0;
	299	}
afeeceb0	300	}