[qemu.git] / softmmu_template.h

/*
 *  Software MMU support
 *
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */
#define DATA_SIZE (1 << SHIFT)

#if DATA_SIZE == 8
#define SUFFIX q
#define USUFFIX q
#define DATA_TYPE uint64_t
#elif DATA_SIZE == 4
#define SUFFIX l
#define USUFFIX l
#define DATA_TYPE uint32_t
#elif DATA_SIZE == 2
#define SUFFIX w
#define USUFFIX uw
#define DATA_TYPE uint16_t
#elif DATA_SIZE == 1
#define SUFFIX b
#define USUFFIX ub
#define DATA_TYPE uint8_t
#else
#error unsupported data size
#endif

#ifdef SOFTMMU_CODE_ACCESS
#define READ_ACCESS_TYPE 2
#define ADDR_READ addr_code
#else
#define READ_ACCESS_TYPE 0
#define ADDR_READ addr_read
#endif

static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
                                                        int mmu_idx,
                                                        void *retaddr);
static inline DATA_TYPE glue(io_read, SUFFIX)(target_phys_addr_t physaddr,
                                              target_ulong addr,
                                              void *retaddr)
{
    DATA_TYPE res;
    int index;
    index = (physaddr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
    physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
    env->mem_io_pc = (unsigned long)retaddr;
    if (index > (IO_MEM_NOTDIRTY >> IO_MEM_SHIFT)
            && !can_do_io(env)) {
        cpu_io_recompile(env, retaddr);
    }

    env->mem_io_vaddr = addr;
#if SHIFT <= 2
    res = io_mem_read[index][SHIFT](io_mem_opaque[index], physaddr);
#else
#ifdef TARGET_WORDS_BIGENDIAN
    res = (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr) << 32;
    res |= io_mem_read[index][2](io_mem_opaque[index], physaddr + 4);
#else
    res = io_mem_read[index][2](io_mem_opaque[index], physaddr);
    res |= (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr + 4) << 32;
#endif
#endif /* SHIFT > 2 */
#ifdef CONFIG_KQEMU
    env->last_io_time = cpu_get_time_fast();
#endif
    return res;
}

/* handle all cases except unaligned access which span two pages */
DATA_TYPE REGPARM glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
                                                      int mmu_idx)
{
    DATA_TYPE res;
    int index;
    target_ulong tlb_addr;
    target_phys_addr_t addend;
    void *retaddr;

    /* test if there is match for unaligned or IO access */
    /* XXX: could done more in memory macro in a non portable way */
    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 redo:
    tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
    if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
        if (tlb_addr & ~TARGET_PAGE_MASK) {
            /* IO access */
            if ((addr & (DATA_SIZE - 1)) != 0)
                goto do_unaligned_access;
            retaddr = GETPC();
            addend = env->iotlb[mmu_idx][index];
            res = glue(io_read, SUFFIX)(addend, addr, retaddr);
        } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
            /* slow unaligned access (it spans two pages or IO) */
        do_unaligned_access:
            retaddr = GETPC();
#ifdef ALIGNED_ONLY
            do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
#endif
            res = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr,
                                                         mmu_idx, retaddr);
        } else {
            /* unaligned/aligned access in the same page */
#ifdef ALIGNED_ONLY
            if ((addr & (DATA_SIZE - 1)) != 0) {
                retaddr = GETPC();
                do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
            }
#endif
            addend = env->tlb_table[mmu_idx][index].addend;
            res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)(addr+addend));
        }
    } else {
        /* the page is not in the TLB : fill it */
        retaddr = GETPC();
#ifdef ALIGNED_ONLY
        if ((addr & (DATA_SIZE - 1)) != 0)
            do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
#endif
        tlb_fill(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
        goto redo;
    }
    return res;
}

/* handle all unaligned cases */
static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
                                                        int mmu_idx,
                                                        void *retaddr)
{
    DATA_TYPE res, res1, res2;
    int index, shift;
    target_phys_addr_t addend;
    target_ulong tlb_addr, addr1, addr2;

    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 redo:
    tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
    if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
        if (tlb_addr & ~TARGET_PAGE_MASK) {
            /* IO access */
            if ((addr & (DATA_SIZE - 1)) != 0)
                goto do_unaligned_access;
            retaddr = GETPC();
            addend = env->iotlb[mmu_idx][index];
            res = glue(io_read, SUFFIX)(addend, addr, retaddr);
        } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
        do_unaligned_access:
            /* slow unaligned access (it spans two pages) */
            addr1 = addr & ~(DATA_SIZE - 1);
            addr2 = addr1 + DATA_SIZE;
            res1 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr1,
                                                          mmu_idx, retaddr);
            res2 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr2,
                                                          mmu_idx, retaddr);
            shift = (addr & (DATA_SIZE - 1)) * 8;
#ifdef TARGET_WORDS_BIGENDIAN
            res = (res1 << shift) | (res2 >> ((DATA_SIZE * 8) - shift));
#else
            res = (res1 >> shift) | (res2 << ((DATA_SIZE * 8) - shift));
#endif
            res = (DATA_TYPE)res;
        } else {
            /* unaligned/aligned access in the same page */
            addend = env->tlb_table[mmu_idx][index].addend;
            res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)(addr+addend));
        }
    } else {
        /* the page is not in the TLB : fill it */
        tlb_fill(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
        goto redo;
    }
    return res;
}

#ifndef SOFTMMU_CODE_ACCESS

static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr,
                                                   DATA_TYPE val,
                                                   int mmu_idx,
                                                   void *retaddr);

static inline void glue(io_write, SUFFIX)(target_phys_addr_t physaddr,
                                          DATA_TYPE val,
                                          target_ulong addr,
                                          void *retaddr)
{
    int index;
    index = (physaddr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
    physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
    if (index > (IO_MEM_NOTDIRTY >> IO_MEM_SHIFT)
            && !can_do_io(env)) {
        cpu_io_recompile(env, retaddr);
    }

    env->mem_io_vaddr = addr;
    env->mem_io_pc = (unsigned long)retaddr;
#if SHIFT <= 2
    io_mem_write[index][SHIFT](io_mem_opaque[index], physaddr, val);
#else
#ifdef TARGET_WORDS_BIGENDIAN
    io_mem_write[index][2](io_mem_opaque[index], physaddr, val >> 32);
    io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val);
#else
    io_mem_write[index][2](io_mem_opaque[index], physaddr, val);
    io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val >> 32);
#endif
#endif /* SHIFT > 2 */
#ifdef CONFIG_KQEMU
    env->last_io_time = cpu_get_time_fast();
#endif
}

void REGPARM glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr,
                                                 DATA_TYPE val,
                                                 int mmu_idx)
{
    target_phys_addr_t addend;
    target_ulong tlb_addr;
    void *retaddr;
    int index;

    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 redo:
    tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
    if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
        if (tlb_addr & ~TARGET_PAGE_MASK) {
            /* IO access */
            if ((addr & (DATA_SIZE - 1)) != 0)
                goto do_unaligned_access;
            retaddr = GETPC();
            addend = env->iotlb[mmu_idx][index];
            glue(io_write, SUFFIX)(addend, val, addr, retaddr);
        } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
        do_unaligned_access:
            retaddr = GETPC();
#ifdef ALIGNED_ONLY
            do_unaligned_access(addr, 1, mmu_idx, retaddr);
#endif
            glue(glue(slow_st, SUFFIX), MMUSUFFIX)(addr, val,
                                                   mmu_idx, retaddr);
        } else {
            /* aligned/unaligned access in the same page */
#ifdef ALIGNED_ONLY
            if ((addr & (DATA_SIZE - 1)) != 0) {
                retaddr = GETPC();
                do_unaligned_access(addr, 1, mmu_idx, retaddr);
            }
#endif
            addend = env->tlb_table[mmu_idx][index].addend;
            glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)(addr+addend), val);
        }
    } else {
        /* the page is not in the TLB : fill it */
        retaddr = GETPC();
#ifdef ALIGNED_ONLY
        if ((addr & (DATA_SIZE - 1)) != 0)
            do_unaligned_access(addr, 1, mmu_idx, retaddr);
#endif
        tlb_fill(addr, 1, mmu_idx, retaddr);
        goto redo;
    }
}

/* handles all unaligned cases */
static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr,
                                                   DATA_TYPE val,
                                                   int mmu_idx,
                                                   void *retaddr)
{
    target_phys_addr_t addend;
    target_ulong tlb_addr;
    int index, i;

    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 redo:
    tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
    if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
        if (tlb_addr & ~TARGET_PAGE_MASK) {
            /* IO access */
            if ((addr & (DATA_SIZE - 1)) != 0)
                goto do_unaligned_access;
            addend = env->iotlb[mmu_idx][index];
            glue(io_write, SUFFIX)(addend, val, addr, retaddr);
        } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
        do_unaligned_access:
            /* XXX: not efficient, but simple */
            /* Note: relies on the fact that tlb_fill() does not remove the
             * previous page from the TLB cache.  */
            for(i = DATA_SIZE - 1; i >= 0; i--) {
#ifdef TARGET_WORDS_BIGENDIAN
                glue(slow_stb, MMUSUFFIX)(addr + i, val >> (((DATA_SIZE - 1) * 8) - (i * 8)),
                                          mmu_idx, retaddr);
#else
                glue(slow_stb, MMUSUFFIX)(addr + i, val >> (i * 8),
                                          mmu_idx, retaddr);
#endif
            }
        } else {
            /* aligned/unaligned access in the same page */
            addend = env->tlb_table[mmu_idx][index].addend;
            glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)(addr+addend), val);
        }
    } else {
        /* the page is not in the TLB : fill it */
        tlb_fill(addr, 1, mmu_idx, retaddr);
        goto redo;
    }
}

#endif /* !defined(SOFTMMU_CODE_ACCESS) */

#undef READ_ACCESS_TYPE
#undef SHIFT
#undef DATA_TYPE
#undef SUFFIX
#undef USUFFIX
#undef DATA_SIZE
#undef ADDR_READ
Commit	Line	Data
b92e5a22 FB	1	/*
b92e5a22 FB	2	* Software MMU support
5fafdf24	3	*
b92e5a22 FB	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
8167ee88	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
b92e5a22 FB	18	*/
	19	#define DATA_SIZE (1 << SHIFT)
	20
	21	#if DATA_SIZE == 8
	22	#define SUFFIX q
61382a50	23	#define USUFFIX q
b92e5a22 FB	24	#define DATA_TYPE uint64_t
	25	#elif DATA_SIZE == 4
	26	#define SUFFIX l
61382a50	27	#define USUFFIX l
b92e5a22 FB	28	#define DATA_TYPE uint32_t
	29	#elif DATA_SIZE == 2
	30	#define SUFFIX w
61382a50	31	#define USUFFIX uw
b92e5a22 FB	32	#define DATA_TYPE uint16_t
	33	#elif DATA_SIZE == 1
	34	#define SUFFIX b
61382a50	35	#define USUFFIX ub
b92e5a22 FB	36	#define DATA_TYPE uint8_t
	37	#else
	38	#error unsupported data size
	39	#endif
	40
b769d8fe FB	41	#ifdef SOFTMMU_CODE_ACCESS
b769d8fe FB	42	#define READ_ACCESS_TYPE 2
84b7b8e7	43	#define ADDR_READ addr_code
b769d8fe FB	44	#else
b769d8fe FB	45	#define READ_ACCESS_TYPE 0
84b7b8e7	46	#define ADDR_READ addr_read
b769d8fe FB	47	#endif
b769d8fe FB	48
5fafdf24	49	static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
6ebbf390	50	int mmu_idx,
61382a50	51	void *retaddr);
5fafdf24	52	static inline DATA_TYPE glue(io_read, SUFFIX)(target_phys_addr_t physaddr,
2e70f6ef PB	53	target_ulong addr,
2e70f6ef PB	54	void *retaddr)
b92e5a22 FB	55	{
	56	DATA_TYPE res;
	57	int index;
0f459d16 PB	58	index = (physaddr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
0f459d16 PB	59	physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
2e70f6ef PB	60	env->mem_io_pc = (unsigned long)retaddr;
	61	if (index > (IO_MEM_NOTDIRTY >> IO_MEM_SHIFT)
	62	&& !can_do_io(env)) {
	63	cpu_io_recompile(env, retaddr);
	64	}
b92e5a22	65
db8886d3	66	env->mem_io_vaddr = addr;
b92e5a22	67	#if SHIFT <= 2
a4193c8a	68	res = io_mem_read[index][SHIFT](io_mem_opaque[index], physaddr);
b92e5a22 FB	69	#else
b92e5a22 FB	70	#ifdef TARGET_WORDS_BIGENDIAN
a4193c8a FB	71	res = (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr) << 32;
a4193c8a FB	72	res \|= io_mem_read[index][2](io_mem_opaque[index], physaddr + 4);
b92e5a22	73	#else
a4193c8a FB	74	res = io_mem_read[index][2](io_mem_opaque[index], physaddr);
a4193c8a FB	75	res \|= (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr + 4) << 32;
b92e5a22 FB	76	#endif
b92e5a22 FB	77	#endif /* SHIFT > 2 */
640f42e4	78	#ifdef CONFIG_KQEMU
f1c85677 FB	79	env->last_io_time = cpu_get_time_fast();
f1c85677 FB	80	#endif
b92e5a22 FB	81	return res;
	82	}
	83
b92e5a22	84	/* handle all cases except unaligned access which span two pages */
d656469f FB	85	DATA_TYPE REGPARM glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
d656469f FB	86	int mmu_idx)
b92e5a22 FB	87	{
b92e5a22 FB	88	DATA_TYPE res;
61382a50	89	int index;
c27004ec	90	target_ulong tlb_addr;
0f459d16	91	target_phys_addr_t addend;
b92e5a22	92	void *retaddr;
3b46e624	93
b92e5a22 FB	94	/* test if there is match for unaligned or IO access */
b92e5a22 FB	95	/* XXX: could done more in memory macro in a non portable way */
b92e5a22 FB	96	index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
b92e5a22 FB	97	redo:
6ebbf390	98	tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
b92e5a22	99	if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK \| TLB_INVALID_MASK))) {
b92e5a22 FB	100	if (tlb_addr & ~TARGET_PAGE_MASK) {
	101	/* IO access */
	102	if ((addr & (DATA_SIZE - 1)) != 0)
	103	goto do_unaligned_access;
2e70f6ef	104	retaddr = GETPC();
0f459d16	105	addend = env->iotlb[mmu_idx][index];
2e70f6ef	106	res = glue(io_read, SUFFIX)(addend, addr, retaddr);
98699967	107	} else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
b92e5a22 FB	108	/* slow unaligned access (it spans two pages or IO) */
b92e5a22 FB	109	do_unaligned_access:
61382a50	110	retaddr = GETPC();
a64d4718	111	#ifdef ALIGNED_ONLY
6ebbf390	112	do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
a64d4718	113	#endif
5fafdf24	114	res = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr,
6ebbf390	115	mmu_idx, retaddr);
b92e5a22	116	} else {
a64d4718 FB	117	/* unaligned/aligned access in the same page */
	118	#ifdef ALIGNED_ONLY
	119	if ((addr & (DATA_SIZE - 1)) != 0) {
	120	retaddr = GETPC();
6ebbf390	121	do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
a64d4718 FB	122	}
a64d4718 FB	123	#endif
0f459d16 PB	124	addend = env->tlb_table[mmu_idx][index].addend;
0f459d16 PB	125	res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)(addr+addend));
b92e5a22 FB	126	}
	127	} else {
	128	/* the page is not in the TLB : fill it */
61382a50	129	retaddr = GETPC();
a64d4718 FB	130	#ifdef ALIGNED_ONLY
a64d4718 FB	131	if ((addr & (DATA_SIZE - 1)) != 0)
6ebbf390	132	do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
a64d4718	133	#endif
6ebbf390	134	tlb_fill(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
b92e5a22 FB	135	goto redo;
	136	}
	137	return res;
	138	}
	139
	140	/* handle all unaligned cases */
5fafdf24	141	static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
6ebbf390	142	int mmu_idx,
61382a50	143	void *retaddr)
b92e5a22 FB	144	{
b92e5a22 FB	145	DATA_TYPE res, res1, res2;
61382a50	146	int index, shift;
0f459d16	147	target_phys_addr_t addend;
c27004ec	148	target_ulong tlb_addr, addr1, addr2;
b92e5a22	149
b92e5a22 FB	150	index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
b92e5a22 FB	151	redo:
6ebbf390	152	tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
b92e5a22	153	if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK \| TLB_INVALID_MASK))) {
b92e5a22 FB	154	if (tlb_addr & ~TARGET_PAGE_MASK) {
	155	/* IO access */
	156	if ((addr & (DATA_SIZE - 1)) != 0)
	157	goto do_unaligned_access;
2e70f6ef	158	retaddr = GETPC();
0f459d16	159	addend = env->iotlb[mmu_idx][index];
2e70f6ef	160	res = glue(io_read, SUFFIX)(addend, addr, retaddr);
98699967	161	} else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
b92e5a22 FB	162	do_unaligned_access:
	163	/* slow unaligned access (it spans two pages) */
	164	addr1 = addr & ~(DATA_SIZE - 1);
	165	addr2 = addr1 + DATA_SIZE;
5fafdf24	166	res1 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr1,
6ebbf390	167	mmu_idx, retaddr);
5fafdf24	168	res2 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr2,
6ebbf390	169	mmu_idx, retaddr);
b92e5a22 FB	170	shift = (addr & (DATA_SIZE - 1)) * 8;
	171	#ifdef TARGET_WORDS_BIGENDIAN
	172	res = (res1 << shift) \| (res2 >> ((DATA_SIZE * 8) - shift));
	173	#else
	174	res = (res1 >> shift) \| (res2 << ((DATA_SIZE * 8) - shift));
	175	#endif
6986f88c	176	res = (DATA_TYPE)res;
b92e5a22 FB	177	} else {
b92e5a22 FB	178	/* unaligned/aligned access in the same page */
0f459d16 PB	179	addend = env->tlb_table[mmu_idx][index].addend;
0f459d16 PB	180	res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)(addr+addend));
b92e5a22 FB	181	}
	182	} else {
	183	/* the page is not in the TLB : fill it */
6ebbf390	184	tlb_fill(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
b92e5a22 FB	185	goto redo;
	186	}
	187	return res;
	188	}
	189
b769d8fe FB	190	#ifndef SOFTMMU_CODE_ACCESS
b769d8fe FB	191
5fafdf24 TS	192	static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr,
5fafdf24 TS	193	DATA_TYPE val,
6ebbf390	194	int mmu_idx,
b769d8fe FB	195	void *retaddr);
b769d8fe FB	196
5fafdf24	197	static inline void glue(io_write, SUFFIX)(target_phys_addr_t physaddr,
b769d8fe	198	DATA_TYPE val,
0f459d16	199	target_ulong addr,
b769d8fe FB	200	void *retaddr)
	201	{
	202	int index;
0f459d16 PB	203	index = (physaddr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
0f459d16 PB	204	physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
2e70f6ef PB	205	if (index > (IO_MEM_NOTDIRTY >> IO_MEM_SHIFT)
	206	&& !can_do_io(env)) {
	207	cpu_io_recompile(env, retaddr);
	208	}
b769d8fe	209
2e70f6ef PB	210	env->mem_io_vaddr = addr;
2e70f6ef PB	211	env->mem_io_pc = (unsigned long)retaddr;
b769d8fe FB	212	#if SHIFT <= 2
	213	io_mem_write[index][SHIFT](io_mem_opaque[index], physaddr, val);
	214	#else
	215	#ifdef TARGET_WORDS_BIGENDIAN
	216	io_mem_write[index][2](io_mem_opaque[index], physaddr, val >> 32);
	217	io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val);
	218	#else
	219	io_mem_write[index][2](io_mem_opaque[index], physaddr, val);
	220	io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val >> 32);
	221	#endif
	222	#endif /* SHIFT > 2 */
640f42e4	223	#ifdef CONFIG_KQEMU
f1c85677 FB	224	env->last_io_time = cpu_get_time_fast();
f1c85677 FB	225	#endif
b769d8fe	226	}
b92e5a22	227
d656469f FB	228	void REGPARM glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr,
	229	DATA_TYPE val,
	230	int mmu_idx)
b92e5a22	231	{
0f459d16	232	target_phys_addr_t addend;
c27004ec	233	target_ulong tlb_addr;
b92e5a22	234	void *retaddr;
61382a50	235	int index;
3b46e624	236
b92e5a22 FB	237	index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
b92e5a22 FB	238	redo:
6ebbf390	239	tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
b92e5a22	240	if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK \| TLB_INVALID_MASK))) {
b92e5a22 FB	241	if (tlb_addr & ~TARGET_PAGE_MASK) {
	242	/* IO access */
	243	if ((addr & (DATA_SIZE - 1)) != 0)
	244	goto do_unaligned_access;
d720b93d	245	retaddr = GETPC();
0f459d16 PB	246	addend = env->iotlb[mmu_idx][index];
0f459d16 PB	247	glue(io_write, SUFFIX)(addend, val, addr, retaddr);
98699967	248	} else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
b92e5a22	249	do_unaligned_access:
61382a50	250	retaddr = GETPC();
a64d4718	251	#ifdef ALIGNED_ONLY
6ebbf390	252	do_unaligned_access(addr, 1, mmu_idx, retaddr);
a64d4718	253	#endif
5fafdf24	254	glue(glue(slow_st, SUFFIX), MMUSUFFIX)(addr, val,
6ebbf390	255	mmu_idx, retaddr);
b92e5a22 FB	256	} else {
b92e5a22 FB	257	/* aligned/unaligned access in the same page */
a64d4718 FB	258	#ifdef ALIGNED_ONLY
	259	if ((addr & (DATA_SIZE - 1)) != 0) {
	260	retaddr = GETPC();
6ebbf390	261	do_unaligned_access(addr, 1, mmu_idx, retaddr);
a64d4718 FB	262	}
a64d4718 FB	263	#endif
0f459d16 PB	264	addend = env->tlb_table[mmu_idx][index].addend;
0f459d16 PB	265	glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)(addr+addend), val);
b92e5a22 FB	266	}
	267	} else {
	268	/* the page is not in the TLB : fill it */
61382a50	269	retaddr = GETPC();
a64d4718 FB	270	#ifdef ALIGNED_ONLY
a64d4718 FB	271	if ((addr & (DATA_SIZE - 1)) != 0)
6ebbf390	272	do_unaligned_access(addr, 1, mmu_idx, retaddr);
a64d4718	273	#endif
6ebbf390	274	tlb_fill(addr, 1, mmu_idx, retaddr);
b92e5a22 FB	275	goto redo;
	276	}
	277	}
	278
	279	/* handles all unaligned cases */
5fafdf24	280	static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr,
61382a50	281	DATA_TYPE val,
6ebbf390	282	int mmu_idx,
61382a50	283	void *retaddr)
b92e5a22	284	{
0f459d16	285	target_phys_addr_t addend;
c27004ec	286	target_ulong tlb_addr;
61382a50	287	int index, i;
b92e5a22	288
b92e5a22 FB	289	index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
b92e5a22 FB	290	redo:
6ebbf390	291	tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
b92e5a22	292	if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK \| TLB_INVALID_MASK))) {
b92e5a22 FB	293	if (tlb_addr & ~TARGET_PAGE_MASK) {
	294	/* IO access */
	295	if ((addr & (DATA_SIZE - 1)) != 0)
	296	goto do_unaligned_access;
0f459d16 PB	297	addend = env->iotlb[mmu_idx][index];
0f459d16 PB	298	glue(io_write, SUFFIX)(addend, val, addr, retaddr);
98699967	299	} else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
b92e5a22 FB	300	do_unaligned_access:
b92e5a22 FB	301	/* XXX: not efficient, but simple */
6c41b272 AZ	302	/* Note: relies on the fact that tlb_fill() does not remove the
6c41b272 AZ	303	* previous page from the TLB cache. */
7221fa98	304	for(i = DATA_SIZE - 1; i >= 0; i--) {
b92e5a22	305	#ifdef TARGET_WORDS_BIGENDIAN
5fafdf24	306	glue(slow_stb, MMUSUFFIX)(addr + i, val >> (((DATA_SIZE - 1) * 8) - (i * 8)),
6ebbf390	307	mmu_idx, retaddr);
b92e5a22	308	#else
5fafdf24	309	glue(slow_stb, MMUSUFFIX)(addr + i, val >> (i * 8),
6ebbf390	310	mmu_idx, retaddr);
b92e5a22 FB	311	#endif
	312	}
	313	} else {
	314	/* aligned/unaligned access in the same page */
0f459d16 PB	315	addend = env->tlb_table[mmu_idx][index].addend;
0f459d16 PB	316	glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)(addr+addend), val);
b92e5a22 FB	317	}
	318	} else {
	319	/* the page is not in the TLB : fill it */
6ebbf390	320	tlb_fill(addr, 1, mmu_idx, retaddr);
b92e5a22 FB	321	goto redo;
	322	}
	323	}
	324
b769d8fe FB	325	#endif /* !defined(SOFTMMU_CODE_ACCESS) */
	326
	327	#undef READ_ACCESS_TYPE
b92e5a22 FB	328	#undef SHIFT
	329	#undef DATA_TYPE
	330	#undef SUFFIX
61382a50	331	#undef USUFFIX
b92e5a22	332	#undef DATA_SIZE
84b7b8e7	333	#undef ADDR_READ