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94e1a912 GH |
1 | /* |
2 | * QEMU AMD PC-Net II (Am79C970A) emulation | |
3 | * | |
4 | * Copyright (c) 2004 Antony T Curtis | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
25 | /* This software was written to be compatible with the specification: | |
26 | * AMD Am79C970A PCnet-PCI II Ethernet Controller Data-Sheet | |
27 | * AMD Publication# 19436 Rev:E Amendment/0 Issue Date: June 2000 | |
28 | */ | |
29 | ||
30 | /* | |
31 | * On Sparc32, this is the Lance (Am7990) part of chip STP2000 (Master I/O), also | |
32 | * produced as NCR89C100. See | |
33 | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt | |
34 | * and | |
35 | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR92C990.txt | |
36 | */ | |
37 | ||
83c9f4ca | 38 | #include "hw/sysbus.h" |
1422e32d | 39 | #include "net/net.h" |
1de7afc9 PB |
40 | #include "qemu/timer.h" |
41 | #include "qemu/sockets.h" | |
0d09e41a | 42 | #include "hw/sparc/sun4m.h" |
47b43a1f | 43 | #include "pcnet.h" |
97bf4851 | 44 | #include "trace.h" |
ea3b3511 | 45 | #include "sysemu/sysemu.h" |
94e1a912 | 46 | |
b1a2aaf7 AF |
47 | #define TYPE_LANCE "lance" |
48 | #define SYSBUS_PCNET(obj) \ | |
49 | OBJECT_CHECK(SysBusPCNetState, (obj), TYPE_LANCE) | |
50 | ||
94e1a912 | 51 | typedef struct { |
b1a2aaf7 AF |
52 | SysBusDevice parent_obj; |
53 | ||
94e1a912 GH |
54 | PCNetState state; |
55 | } SysBusPCNetState; | |
56 | ||
57 | static void parent_lance_reset(void *opaque, int irq, int level) | |
58 | { | |
59 | SysBusPCNetState *d = opaque; | |
60 | if (level) | |
61 | pcnet_h_reset(&d->state); | |
62 | } | |
63 | ||
a8170e5e | 64 | static void lance_mem_write(void *opaque, hwaddr addr, |
bd8d6f7c | 65 | uint64_t val, unsigned size) |
94e1a912 GH |
66 | { |
67 | SysBusPCNetState *d = opaque; | |
97bf4851 BS |
68 | |
69 | trace_lance_mem_writew(addr, val & 0xffff); | |
94e1a912 GH |
70 | pcnet_ioport_writew(&d->state, addr, val & 0xffff); |
71 | } | |
72 | ||
a8170e5e | 73 | static uint64_t lance_mem_read(void *opaque, hwaddr addr, |
bd8d6f7c | 74 | unsigned size) |
94e1a912 GH |
75 | { |
76 | SysBusPCNetState *d = opaque; | |
77 | uint32_t val; | |
78 | ||
79 | val = pcnet_ioport_readw(&d->state, addr); | |
97bf4851 | 80 | trace_lance_mem_readw(addr, val & 0xffff); |
94e1a912 GH |
81 | return val & 0xffff; |
82 | } | |
83 | ||
bd8d6f7c AK |
84 | static const MemoryRegionOps lance_mem_ops = { |
85 | .read = lance_mem_read, | |
86 | .write = lance_mem_write, | |
87 | .endianness = DEVICE_NATIVE_ENDIAN, | |
88 | .valid = { | |
89 | .min_access_size = 2, | |
90 | .max_access_size = 2, | |
91 | }, | |
94e1a912 GH |
92 | }; |
93 | ||
1fa51482 | 94 | static NetClientInfo net_lance_info = { |
2be64a68 | 95 | .type = NET_CLIENT_OPTIONS_KIND_NIC, |
1fa51482 MM |
96 | .size = sizeof(NICState), |
97 | .can_receive = pcnet_can_receive, | |
98 | .receive = pcnet_receive, | |
e1c2008a | 99 | .link_status_changed = pcnet_set_link_status, |
1fa51482 MM |
100 | }; |
101 | ||
be73cfe2 JQ |
102 | static const VMStateDescription vmstate_lance = { |
103 | .name = "pcnet", | |
104 | .version_id = 3, | |
105 | .minimum_version_id = 2, | |
35d08458 | 106 | .fields = (VMStateField[]) { |
be73cfe2 JQ |
107 | VMSTATE_STRUCT(state, SysBusPCNetState, 0, vmstate_pcnet, PCNetState), |
108 | VMSTATE_END_OF_LIST() | |
109 | } | |
110 | }; | |
111 | ||
b1a2aaf7 | 112 | static int lance_init(SysBusDevice *sbd) |
94e1a912 | 113 | { |
b1a2aaf7 AF |
114 | DeviceState *dev = DEVICE(sbd); |
115 | SysBusPCNetState *d = SYSBUS_PCNET(dev); | |
94e1a912 GH |
116 | PCNetState *s = &d->state; |
117 | ||
eedfac6f PB |
118 | memory_region_init_io(&s->mmio, OBJECT(d), &lance_mem_ops, d, |
119 | "lance-mmio", 4); | |
94e1a912 | 120 | |
b1a2aaf7 | 121 | qdev_init_gpio_in(dev, parent_lance_reset, 1); |
94e1a912 | 122 | |
b1a2aaf7 | 123 | sysbus_init_mmio(sbd, &s->mmio); |
94e1a912 | 124 | |
b1a2aaf7 | 125 | sysbus_init_irq(sbd, &s->irq); |
94e1a912 GH |
126 | |
127 | s->phys_mem_read = ledma_memory_read; | |
128 | s->phys_mem_write = ledma_memory_write; | |
b1a2aaf7 | 129 | return pcnet_common_init(dev, s, &net_lance_info); |
94e1a912 GH |
130 | } |
131 | ||
132 | static void lance_reset(DeviceState *dev) | |
133 | { | |
b1a2aaf7 | 134 | SysBusPCNetState *d = SYSBUS_PCNET(dev); |
94e1a912 GH |
135 | |
136 | pcnet_h_reset(&d->state); | |
137 | } | |
138 | ||
ea3b3511 GA |
139 | static void lance_instance_init(Object *obj) |
140 | { | |
141 | SysBusPCNetState *d = SYSBUS_PCNET(obj); | |
142 | PCNetState *s = &d->state; | |
143 | ||
144 | device_add_bootindex_property(obj, &s->conf.bootindex, | |
145 | "bootindex", "/ethernet-phy@0", | |
146 | DEVICE(obj), NULL); | |
147 | } | |
148 | ||
999e12bb AL |
149 | static Property lance_properties[] = { |
150 | DEFINE_PROP_PTR("dma", SysBusPCNetState, state.dma_opaque), | |
151 | DEFINE_NIC_PROPERTIES(SysBusPCNetState, state.conf), | |
152 | DEFINE_PROP_END_OF_LIST(), | |
153 | }; | |
154 | ||
155 | static void lance_class_init(ObjectClass *klass, void *data) | |
156 | { | |
39bffca2 | 157 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb AL |
158 | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
159 | ||
160 | k->init = lance_init; | |
125ee0ed | 161 | set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); |
39bffca2 AL |
162 | dc->fw_name = "ethernet"; |
163 | dc->reset = lance_reset; | |
164 | dc->vmsd = &vmstate_lance; | |
165 | dc->props = lance_properties; | |
1b111dc1 MA |
166 | /* Reason: pointer property "dma" */ |
167 | dc->cannot_instantiate_with_device_add_yet = true; | |
999e12bb AL |
168 | } |
169 | ||
8c43a6f0 | 170 | static const TypeInfo lance_info = { |
b1a2aaf7 | 171 | .name = TYPE_LANCE, |
39bffca2 AL |
172 | .parent = TYPE_SYS_BUS_DEVICE, |
173 | .instance_size = sizeof(SysBusPCNetState), | |
174 | .class_init = lance_class_init, | |
ea3b3511 | 175 | .instance_init = lance_instance_init, |
94e1a912 GH |
176 | }; |
177 | ||
83f7d43a | 178 | static void lance_register_types(void) |
94e1a912 | 179 | { |
39bffca2 | 180 | type_register_static(&lance_info); |
94e1a912 | 181 | } |
83f7d43a AF |
182 | |
183 | type_init(lance_register_types) |