]>
Commit | Line | Data |
---|---|---|
9ee6e8bb PB |
1 | /* |
2 | * Arm PrimeCell PL061 General Purpose IO with additional | |
3 | * Luminary Micro Stellaris bits. | |
4 | * | |
5 | * Copyright (c) 2007 CodeSourcery. | |
6 | * Written by Paul Brook | |
7 | * | |
8e31bf38 | 8 | * This code is licensed under the GPL. |
9ee6e8bb PB |
9 | */ |
10 | ||
8ef94f0b | 11 | #include "qemu/osdep.h" |
83c9f4ca | 12 | #include "hw/sysbus.h" |
03dd024f | 13 | #include "qemu/log.h" |
9ee6e8bb PB |
14 | |
15 | //#define DEBUG_PL061 1 | |
16 | ||
17 | #ifdef DEBUG_PL061 | |
001faf32 BS |
18 | #define DPRINTF(fmt, ...) \ |
19 | do { printf("pl061: " fmt , ## __VA_ARGS__); } while (0) | |
20 | #define BADF(fmt, ...) \ | |
21 | do { fprintf(stderr, "pl061: error: " fmt , ## __VA_ARGS__); exit(1);} while (0) | |
9ee6e8bb | 22 | #else |
001faf32 BS |
23 | #define DPRINTF(fmt, ...) do {} while(0) |
24 | #define BADF(fmt, ...) \ | |
25 | do { fprintf(stderr, "pl061: error: " fmt , ## __VA_ARGS__);} while (0) | |
9ee6e8bb PB |
26 | #endif |
27 | ||
28 | static const uint8_t pl061_id[12] = | |
7063f49f PM |
29 | { 0x00, 0x00, 0x00, 0x00, 0x61, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 }; |
30 | static const uint8_t pl061_id_luminary[12] = | |
9ee6e8bb PB |
31 | { 0x00, 0x00, 0x00, 0x00, 0x61, 0x00, 0x18, 0x01, 0x0d, 0xf0, 0x05, 0xb1 }; |
32 | ||
692a76d1 AF |
33 | #define TYPE_PL061 "pl061" |
34 | #define PL061(obj) OBJECT_CHECK(PL061State, (obj), TYPE_PL061) | |
35 | ||
ee663e96 | 36 | typedef struct PL061State { |
692a76d1 AF |
37 | SysBusDevice parent_obj; |
38 | ||
3cf89f8a | 39 | MemoryRegion iomem; |
a35faa94 PM |
40 | uint32_t locked; |
41 | uint32_t data; | |
bfb27e60 CL |
42 | uint32_t old_out_data; |
43 | uint32_t old_in_data; | |
a35faa94 PM |
44 | uint32_t dir; |
45 | uint32_t isense; | |
46 | uint32_t ibe; | |
47 | uint32_t iev; | |
48 | uint32_t im; | |
49 | uint32_t istate; | |
50 | uint32_t afsel; | |
51 | uint32_t dr2r; | |
52 | uint32_t dr4r; | |
53 | uint32_t dr8r; | |
54 | uint32_t odr; | |
55 | uint32_t pur; | |
56 | uint32_t pdr; | |
57 | uint32_t slr; | |
58 | uint32_t den; | |
59 | uint32_t cr; | |
b3aaff11 | 60 | uint32_t amsel; |
9ee6e8bb PB |
61 | qemu_irq irq; |
62 | qemu_irq out[8]; | |
7063f49f | 63 | const unsigned char *id; |
09aa3bf3 | 64 | uint32_t rsvd_start; /* reserved area: [rsvd_start, 0xfcc] */ |
ee663e96 | 65 | } PL061State; |
9ee6e8bb | 66 | |
a35faa94 PM |
67 | static const VMStateDescription vmstate_pl061 = { |
68 | .name = "pl061", | |
c3a86b35 WH |
69 | .version_id = 4, |
70 | .minimum_version_id = 4, | |
a35faa94 | 71 | .fields = (VMStateField[]) { |
ee663e96 AF |
72 | VMSTATE_UINT32(locked, PL061State), |
73 | VMSTATE_UINT32(data, PL061State), | |
bfb27e60 CL |
74 | VMSTATE_UINT32(old_out_data, PL061State), |
75 | VMSTATE_UINT32(old_in_data, PL061State), | |
ee663e96 AF |
76 | VMSTATE_UINT32(dir, PL061State), |
77 | VMSTATE_UINT32(isense, PL061State), | |
78 | VMSTATE_UINT32(ibe, PL061State), | |
79 | VMSTATE_UINT32(iev, PL061State), | |
80 | VMSTATE_UINT32(im, PL061State), | |
81 | VMSTATE_UINT32(istate, PL061State), | |
82 | VMSTATE_UINT32(afsel, PL061State), | |
83 | VMSTATE_UINT32(dr2r, PL061State), | |
84 | VMSTATE_UINT32(dr4r, PL061State), | |
85 | VMSTATE_UINT32(dr8r, PL061State), | |
86 | VMSTATE_UINT32(odr, PL061State), | |
87 | VMSTATE_UINT32(pur, PL061State), | |
88 | VMSTATE_UINT32(pdr, PL061State), | |
89 | VMSTATE_UINT32(slr, PL061State), | |
90 | VMSTATE_UINT32(den, PL061State), | |
91 | VMSTATE_UINT32(cr, PL061State), | |
ee663e96 | 92 | VMSTATE_UINT32_V(amsel, PL061State, 2), |
a35faa94 PM |
93 | VMSTATE_END_OF_LIST() |
94 | } | |
95 | }; | |
96 | ||
ee663e96 | 97 | static void pl061_update(PL061State *s) |
9ee6e8bb PB |
98 | { |
99 | uint8_t changed; | |
100 | uint8_t mask; | |
775616c3 | 101 | uint8_t out; |
9ee6e8bb PB |
102 | int i; |
103 | ||
bfb27e60 CL |
104 | DPRINTF("dir = %d, data = %d\n", s->dir, s->data); |
105 | ||
775616c3 PB |
106 | /* Outputs float high. */ |
107 | /* FIXME: This is board dependent. */ | |
108 | out = (s->data & s->dir) | ~s->dir; | |
bfb27e60 CL |
109 | changed = s->old_out_data ^ out; |
110 | if (changed) { | |
111 | s->old_out_data = out; | |
112 | for (i = 0; i < 8; i++) { | |
113 | mask = 1 << i; | |
114 | if (changed & mask) { | |
115 | DPRINTF("Set output %d = %d\n", i, (out & mask) != 0); | |
116 | qemu_set_irq(s->out[i], (out & mask) != 0); | |
117 | } | |
9ee6e8bb PB |
118 | } |
119 | } | |
120 | ||
bfb27e60 CL |
121 | /* Inputs */ |
122 | changed = (s->old_in_data ^ s->data) & ~s->dir; | |
123 | if (changed) { | |
124 | s->old_in_data = s->data; | |
125 | for (i = 0; i < 8; i++) { | |
126 | mask = 1 << i; | |
127 | if (changed & mask) { | |
128 | DPRINTF("Changed input %d = %d\n", i, (s->data & mask) != 0); | |
129 | ||
130 | if (!(s->isense & mask)) { | |
131 | /* Edge interrupt */ | |
132 | if (s->ibe & mask) { | |
133 | /* Any edge triggers the interrupt */ | |
134 | s->istate |= mask; | |
135 | } else { | |
136 | /* Edge is selected by IEV */ | |
137 | s->istate |= ~(s->data ^ s->iev) & mask; | |
138 | } | |
139 | } | |
140 | } | |
141 | } | |
142 | } | |
143 | ||
144 | /* Level interrupt */ | |
145 | s->istate |= ~(s->data ^ s->iev) & s->isense; | |
146 | ||
147 | DPRINTF("istate = %02X\n", s->istate); | |
148 | ||
149 | qemu_set_irq(s->irq, (s->istate & s->im) != 0); | |
9ee6e8bb PB |
150 | } |
151 | ||
a8170e5e | 152 | static uint64_t pl061_read(void *opaque, hwaddr offset, |
3cf89f8a | 153 | unsigned size) |
9ee6e8bb | 154 | { |
ee663e96 | 155 | PL061State *s = (PL061State *)opaque; |
9ee6e8bb | 156 | |
9ee6e8bb PB |
157 | if (offset < 0x400) { |
158 | return s->data & (offset >> 2); | |
159 | } | |
09aa3bf3 WH |
160 | if (offset >= s->rsvd_start && offset <= 0xfcc) { |
161 | goto err_out; | |
162 | } | |
163 | if (offset >= 0xfd0 && offset < 0x1000) { | |
164 | return s->id[(offset - 0xfd0) >> 2]; | |
165 | } | |
9ee6e8bb PB |
166 | switch (offset) { |
167 | case 0x400: /* Direction */ | |
168 | return s->dir; | |
169 | case 0x404: /* Interrupt sense */ | |
170 | return s->isense; | |
171 | case 0x408: /* Interrupt both edges */ | |
172 | return s->ibe; | |
ff2712ba | 173 | case 0x40c: /* Interrupt event */ |
9ee6e8bb PB |
174 | return s->iev; |
175 | case 0x410: /* Interrupt mask */ | |
176 | return s->im; | |
177 | case 0x414: /* Raw interrupt status */ | |
178 | return s->istate; | |
179 | case 0x418: /* Masked interrupt status */ | |
0b2ff2ce | 180 | return s->istate & s->im; |
9ee6e8bb PB |
181 | case 0x420: /* Alternate function select */ |
182 | return s->afsel; | |
183 | case 0x500: /* 2mA drive */ | |
184 | return s->dr2r; | |
185 | case 0x504: /* 4mA drive */ | |
186 | return s->dr4r; | |
187 | case 0x508: /* 8mA drive */ | |
188 | return s->dr8r; | |
189 | case 0x50c: /* Open drain */ | |
190 | return s->odr; | |
191 | case 0x510: /* Pull-up */ | |
192 | return s->pur; | |
193 | case 0x514: /* Pull-down */ | |
194 | return s->pdr; | |
195 | case 0x518: /* Slew rate control */ | |
196 | return s->slr; | |
197 | case 0x51c: /* Digital enable */ | |
198 | return s->den; | |
199 | case 0x520: /* Lock */ | |
200 | return s->locked; | |
201 | case 0x524: /* Commit */ | |
202 | return s->cr; | |
b3aaff11 PM |
203 | case 0x528: /* Analog mode select */ |
204 | return s->amsel; | |
9ee6e8bb | 205 | default: |
09aa3bf3 | 206 | break; |
9ee6e8bb | 207 | } |
09aa3bf3 WH |
208 | err_out: |
209 | qemu_log_mask(LOG_GUEST_ERROR, | |
210 | "pl061_read: Bad offset %x\n", (int)offset); | |
211 | return 0; | |
9ee6e8bb PB |
212 | } |
213 | ||
a8170e5e | 214 | static void pl061_write(void *opaque, hwaddr offset, |
3cf89f8a | 215 | uint64_t value, unsigned size) |
9ee6e8bb | 216 | { |
ee663e96 | 217 | PL061State *s = (PL061State *)opaque; |
9ee6e8bb PB |
218 | uint8_t mask; |
219 | ||
9ee6e8bb PB |
220 | if (offset < 0x400) { |
221 | mask = (offset >> 2) & s->dir; | |
222 | s->data = (s->data & ~mask) | (value & mask); | |
223 | pl061_update(s); | |
224 | return; | |
225 | } | |
09aa3bf3 WH |
226 | if (offset >= s->rsvd_start) { |
227 | goto err_out; | |
228 | } | |
9ee6e8bb PB |
229 | switch (offset) { |
230 | case 0x400: /* Direction */ | |
a35faa94 | 231 | s->dir = value & 0xff; |
9ee6e8bb PB |
232 | break; |
233 | case 0x404: /* Interrupt sense */ | |
a35faa94 | 234 | s->isense = value & 0xff; |
9ee6e8bb PB |
235 | break; |
236 | case 0x408: /* Interrupt both edges */ | |
a35faa94 | 237 | s->ibe = value & 0xff; |
9ee6e8bb | 238 | break; |
ff2712ba | 239 | case 0x40c: /* Interrupt event */ |
a35faa94 | 240 | s->iev = value & 0xff; |
9ee6e8bb PB |
241 | break; |
242 | case 0x410: /* Interrupt mask */ | |
a35faa94 | 243 | s->im = value & 0xff; |
9ee6e8bb PB |
244 | break; |
245 | case 0x41c: /* Interrupt clear */ | |
246 | s->istate &= ~value; | |
247 | break; | |
248 | case 0x420: /* Alternate function select */ | |
249 | mask = s->cr; | |
250 | s->afsel = (s->afsel & ~mask) | (value & mask); | |
251 | break; | |
252 | case 0x500: /* 2mA drive */ | |
a35faa94 | 253 | s->dr2r = value & 0xff; |
9ee6e8bb PB |
254 | break; |
255 | case 0x504: /* 4mA drive */ | |
a35faa94 | 256 | s->dr4r = value & 0xff; |
9ee6e8bb PB |
257 | break; |
258 | case 0x508: /* 8mA drive */ | |
a35faa94 | 259 | s->dr8r = value & 0xff; |
9ee6e8bb PB |
260 | break; |
261 | case 0x50c: /* Open drain */ | |
a35faa94 | 262 | s->odr = value & 0xff; |
9ee6e8bb PB |
263 | break; |
264 | case 0x510: /* Pull-up */ | |
a35faa94 | 265 | s->pur = value & 0xff; |
9ee6e8bb PB |
266 | break; |
267 | case 0x514: /* Pull-down */ | |
a35faa94 | 268 | s->pdr = value & 0xff; |
9ee6e8bb PB |
269 | break; |
270 | case 0x518: /* Slew rate control */ | |
a35faa94 | 271 | s->slr = value & 0xff; |
9ee6e8bb PB |
272 | break; |
273 | case 0x51c: /* Digital enable */ | |
a35faa94 | 274 | s->den = value & 0xff; |
9ee6e8bb PB |
275 | break; |
276 | case 0x520: /* Lock */ | |
277 | s->locked = (value != 0xacce551); | |
278 | break; | |
279 | case 0x524: /* Commit */ | |
280 | if (!s->locked) | |
a35faa94 | 281 | s->cr = value & 0xff; |
9ee6e8bb | 282 | break; |
b3aaff11 PM |
283 | case 0x528: |
284 | s->amsel = value & 0xff; | |
285 | break; | |
9ee6e8bb | 286 | default: |
09aa3bf3 | 287 | goto err_out; |
9ee6e8bb PB |
288 | } |
289 | pl061_update(s); | |
09aa3bf3 WH |
290 | return; |
291 | err_out: | |
292 | qemu_log_mask(LOG_GUEST_ERROR, | |
293 | "pl061_write: Bad offset %x\n", (int)offset); | |
9ee6e8bb PB |
294 | } |
295 | ||
b527db44 | 296 | static void pl061_reset(DeviceState *dev) |
9ee6e8bb | 297 | { |
b527db44 WH |
298 | PL061State *s = PL061(dev); |
299 | ||
300 | /* reset values from PL061 TRM, Stellaris LM3S5P31 & LM3S8962 Data Sheet */ | |
301 | s->data = 0; | |
302 | s->old_out_data = 0; | |
303 | s->old_in_data = 0; | |
304 | s->dir = 0; | |
305 | s->isense = 0; | |
306 | s->ibe = 0; | |
307 | s->iev = 0; | |
308 | s->im = 0; | |
309 | s->istate = 0; | |
310 | s->afsel = 0; | |
311 | s->dr2r = 0xff; | |
312 | s->dr4r = 0; | |
313 | s->dr8r = 0; | |
314 | s->odr = 0; | |
315 | s->pur = 0; | |
316 | s->pdr = 0; | |
317 | s->slr = 0; | |
318 | s->den = 0; | |
319 | s->locked = 1; | |
320 | s->cr = 0xff; | |
321 | s->amsel = 0; | |
9ee6e8bb PB |
322 | } |
323 | ||
9596ebb7 | 324 | static void pl061_set_irq(void * opaque, int irq, int level) |
9ee6e8bb | 325 | { |
ee663e96 | 326 | PL061State *s = (PL061State *)opaque; |
9ee6e8bb PB |
327 | uint8_t mask; |
328 | ||
329 | mask = 1 << irq; | |
330 | if ((s->dir & mask) == 0) { | |
331 | s->data &= ~mask; | |
332 | if (level) | |
333 | s->data |= mask; | |
334 | pl061_update(s); | |
335 | } | |
336 | } | |
337 | ||
3cf89f8a AK |
338 | static const MemoryRegionOps pl061_ops = { |
339 | .read = pl061_read, | |
340 | .write = pl061_write, | |
341 | .endianness = DEVICE_NATIVE_ENDIAN, | |
9ee6e8bb PB |
342 | }; |
343 | ||
692a76d1 | 344 | static void pl061_luminary_init(Object *obj) |
7063f49f | 345 | { |
692a76d1 AF |
346 | PL061State *s = PL061(obj); |
347 | ||
348 | s->id = pl061_id_luminary; | |
09aa3bf3 | 349 | s->rsvd_start = 0x52c; |
7063f49f PM |
350 | } |
351 | ||
692a76d1 | 352 | static void pl061_init(Object *obj) |
7063f49f | 353 | { |
692a76d1 | 354 | PL061State *s = PL061(obj); |
09e6fb3e XZ |
355 | DeviceState *dev = DEVICE(obj); |
356 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | |
692a76d1 AF |
357 | |
358 | s->id = pl061_id; | |
09aa3bf3 | 359 | s->rsvd_start = 0x424; |
09e6fb3e XZ |
360 | |
361 | memory_region_init_io(&s->iomem, obj, &pl061_ops, s, "pl061", 0x1000); | |
362 | sysbus_init_mmio(sbd, &s->iomem); | |
363 | sysbus_init_irq(sbd, &s->irq); | |
364 | qdev_init_gpio_in(dev, pl061_set_irq, 8); | |
365 | qdev_init_gpio_out(dev, s->out, 8); | |
7063f49f PM |
366 | } |
367 | ||
999e12bb AL |
368 | static void pl061_class_init(ObjectClass *klass, void *data) |
369 | { | |
39bffca2 | 370 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 371 | |
39bffca2 | 372 | dc->vmsd = &vmstate_pl061; |
b527db44 | 373 | dc->reset = &pl061_reset; |
999e12bb AL |
374 | } |
375 | ||
8c43a6f0 | 376 | static const TypeInfo pl061_info = { |
692a76d1 | 377 | .name = TYPE_PL061, |
39bffca2 | 378 | .parent = TYPE_SYS_BUS_DEVICE, |
ee663e96 | 379 | .instance_size = sizeof(PL061State), |
692a76d1 | 380 | .instance_init = pl061_init, |
39bffca2 | 381 | .class_init = pl061_class_init, |
a35faa94 PM |
382 | }; |
383 | ||
8c43a6f0 | 384 | static const TypeInfo pl061_luminary_info = { |
39bffca2 | 385 | .name = "pl061_luminary", |
692a76d1 AF |
386 | .parent = TYPE_PL061, |
387 | .instance_init = pl061_luminary_init, | |
a35faa94 PM |
388 | }; |
389 | ||
83f7d43a | 390 | static void pl061_register_types(void) |
40905a6a | 391 | { |
39bffca2 AL |
392 | type_register_static(&pl061_info); |
393 | type_register_static(&pl061_luminary_info); | |
40905a6a PB |
394 | } |
395 | ||
83f7d43a | 396 | type_init(pl061_register_types) |