[qemu.git] / target-s390x / ioinst.h

/*
 * S/390 channel I/O instructions
 *
 * Copyright 2012 IBM Corp.
 * Author(s): Cornelia Huck <[email protected]>
 *
 * This work is licensed under the terms of the GNU GPL, version 2 or (at
 * your option) any later version. See the COPYING file in the top-level
 * directory.
*/

#ifndef IOINST_S390X_H
#define IOINST_S390X_H
/*
 * Channel I/O related definitions, as defined in the Principles
 * Of Operation (and taken from the Linux implementation).
 */

/* subchannel status word (command mode only) */
typedef struct SCSW {
    uint16_t flags;
    uint16_t ctrl;
    uint32_t cpa;
    uint8_t dstat;
    uint8_t cstat;
    uint16_t count;
} QEMU_PACKED SCSW;

#define SCSW_FLAGS_MASK_KEY 0xf000
#define SCSW_FLAGS_MASK_SCTL 0x0800
#define SCSW_FLAGS_MASK_ESWF 0x0400
#define SCSW_FLAGS_MASK_CC 0x0300
#define SCSW_FLAGS_MASK_FMT 0x0080
#define SCSW_FLAGS_MASK_PFCH 0x0040
#define SCSW_FLAGS_MASK_ISIC 0x0020
#define SCSW_FLAGS_MASK_ALCC 0x0010
#define SCSW_FLAGS_MASK_SSI 0x0008
#define SCSW_FLAGS_MASK_ZCC 0x0004
#define SCSW_FLAGS_MASK_ECTL 0x0002
#define SCSW_FLAGS_MASK_PNO 0x0001

#define SCSW_CTRL_MASK_FCTL 0x7000
#define SCSW_CTRL_MASK_ACTL 0x0fe0
#define SCSW_CTRL_MASK_STCTL 0x001f

#define SCSW_FCTL_CLEAR_FUNC 0x1000
#define SCSW_FCTL_HALT_FUNC 0x2000
#define SCSW_FCTL_START_FUNC 0x4000

#define SCSW_ACTL_SUSP 0x0020
#define SCSW_ACTL_DEVICE_ACTIVE 0x0040
#define SCSW_ACTL_SUBCH_ACTIVE 0x0080
#define SCSW_ACTL_CLEAR_PEND 0x0100
#define SCSW_ACTL_HALT_PEND  0x0200
#define SCSW_ACTL_START_PEND 0x0400
#define SCSW_ACTL_RESUME_PEND 0x0800

#define SCSW_STCTL_STATUS_PEND 0x0001
#define SCSW_STCTL_SECONDARY 0x0002
#define SCSW_STCTL_PRIMARY 0x0004
#define SCSW_STCTL_INTERMEDIATE 0x0008
#define SCSW_STCTL_ALERT 0x0010

#define SCSW_DSTAT_ATTENTION     0x80
#define SCSW_DSTAT_STAT_MOD      0x40
#define SCSW_DSTAT_CU_END        0x20
#define SCSW_DSTAT_BUSY          0x10
#define SCSW_DSTAT_CHANNEL_END   0x08
#define SCSW_DSTAT_DEVICE_END    0x04
#define SCSW_DSTAT_UNIT_CHECK    0x02
#define SCSW_DSTAT_UNIT_EXCEP    0x01

#define SCSW_CSTAT_PCI           0x80
#define SCSW_CSTAT_INCORR_LEN    0x40
#define SCSW_CSTAT_PROG_CHECK    0x20
#define SCSW_CSTAT_PROT_CHECK    0x10
#define SCSW_CSTAT_DATA_CHECK    0x08
#define SCSW_CSTAT_CHN_CTRL_CHK  0x04
#define SCSW_CSTAT_INTF_CTRL_CHK 0x02
#define SCSW_CSTAT_CHAIN_CHECK   0x01

/* path management control word */
typedef struct PMCW {
    uint32_t intparm;
    uint16_t flags;
    uint16_t devno;
    uint8_t  lpm;
    uint8_t  pnom;
    uint8_t  lpum;
    uint8_t  pim;
    uint16_t mbi;
    uint8_t  pom;
    uint8_t  pam;
    uint8_t  chpid[8];
    uint32_t chars;
} QEMU_PACKED PMCW;

#define PMCW_FLAGS_MASK_QF 0x8000
#define PMCW_FLAGS_MASK_W 0x4000
#define PMCW_FLAGS_MASK_ISC 0x3800
#define PMCW_FLAGS_MASK_ENA 0x0080
#define PMCW_FLAGS_MASK_LM 0x0060
#define PMCW_FLAGS_MASK_MME 0x0018
#define PMCW_FLAGS_MASK_MP 0x0004
#define PMCW_FLAGS_MASK_TF 0x0002
#define PMCW_FLAGS_MASK_DNV 0x0001
#define PMCW_FLAGS_MASK_INVALID 0x0700

#define PMCW_CHARS_MASK_ST 0x00e00000
#define PMCW_CHARS_MASK_MBFC 0x00000004
#define PMCW_CHARS_MASK_XMWME 0x00000002
#define PMCW_CHARS_MASK_CSENSE 0x00000001
#define PMCW_CHARS_MASK_INVALID 0xff1ffff8

/* subchannel information block */
typedef struct SCHIB {
    PMCW pmcw;
    SCSW scsw;
    uint64_t mba;
    uint8_t mda[4];
} QEMU_PACKED SCHIB;

/* interruption response block */
typedef struct IRB {
    SCSW scsw;
    uint32_t esw[5];
    uint32_t ecw[8];
    uint32_t emw[8];
} QEMU_PACKED IRB;

/* operation request block */
typedef struct ORB {
    uint32_t intparm;
    uint16_t ctrl0;
    uint8_t lpm;
    uint8_t ctrl1;
    uint32_t cpa;
} QEMU_PACKED ORB;

#define ORB_CTRL0_MASK_KEY 0xf000
#define ORB_CTRL0_MASK_SPND 0x0800
#define ORB_CTRL0_MASK_STR 0x0400
#define ORB_CTRL0_MASK_MOD 0x0200
#define ORB_CTRL0_MASK_SYNC 0x0100
#define ORB_CTRL0_MASK_FMT 0x0080
#define ORB_CTRL0_MASK_PFCH 0x0040
#define ORB_CTRL0_MASK_ISIC 0x0020
#define ORB_CTRL0_MASK_ALCC 0x0010
#define ORB_CTRL0_MASK_SSIC 0x0008
#define ORB_CTRL0_MASK_C64 0x0002
#define ORB_CTRL0_MASK_I2K 0x0001
#define ORB_CTRL0_MASK_INVALID 0x0004

#define ORB_CTRL1_MASK_ILS 0x80
#define ORB_CTRL1_MASK_MIDAW 0x40
#define ORB_CTRL1_MASK_ORBX 0x01
#define ORB_CTRL1_MASK_INVALID 0x3e

/* channel command word (type 1) */
typedef struct CCW1 {
    uint8_t cmd_code;
    uint8_t flags;
    uint16_t count;
    uint32_t cda;
} QEMU_PACKED CCW1;

#define CCW_FLAG_DC              0x80
#define CCW_FLAG_CC              0x40
#define CCW_FLAG_SLI             0x20
#define CCW_FLAG_SKIP            0x10
#define CCW_FLAG_PCI             0x08
#define CCW_FLAG_IDA             0x04
#define CCW_FLAG_SUSPEND         0x02

#define CCW_CMD_NOOP             0x03
#define CCW_CMD_BASIC_SENSE      0x04
#define CCW_CMD_TIC              0x08
#define CCW_CMD_SENSE_ID         0xe4

typedef struct CRW {
    uint16_t flags;
    uint16_t rsid;
} QEMU_PACKED CRW;

#define CRW_FLAGS_MASK_S 0x4000
#define CRW_FLAGS_MASK_R 0x2000
#define CRW_FLAGS_MASK_C 0x1000
#define CRW_FLAGS_MASK_RSC 0x0f00
#define CRW_FLAGS_MASK_A 0x0080
#define CRW_FLAGS_MASK_ERC 0x003f

#define CRW_ERC_INIT 0x02
#define CRW_ERC_IPI  0x04

#define CRW_RSC_SUBCH 0x3
#define CRW_RSC_CHP   0x4

/* I/O interruption code */
typedef struct IOIntCode {
    uint32_t subsys_id;
    uint32_t intparm;
    uint32_t interrupt_id;
} QEMU_PACKED IOIntCode;

/* schid disintegration */
#define IOINST_SCHID_ONE(_schid)   ((_schid & 0x00010000) >> 16)
#define IOINST_SCHID_M(_schid)     ((_schid & 0x00080000) >> 19)
#define IOINST_SCHID_CSSID(_schid) ((_schid & 0xff000000) >> 24)
#define IOINST_SCHID_SSID(_schid)  ((_schid & 0x00060000) >> 17)
#define IOINST_SCHID_NR(_schid)    (_schid & 0x0000ffff)

#define IO_INT_WORD_ISC(_int_word) ((_int_word & 0x38000000) >> 24)
#define ISC_TO_ISC_BITS(_isc)      ((0x80 >> _isc) << 24)

int ioinst_disassemble_sch_ident(uint32_t value, int *m, int *cssid, int *ssid,
                                 int *schid);
int ioinst_handle_xsch(CPUS390XState *env, uint64_t reg1);
int ioinst_handle_csch(CPUS390XState *env, uint64_t reg1);
int ioinst_handle_hsch(CPUS390XState *env, uint64_t reg1);
int ioinst_handle_msch(CPUS390XState *env, uint64_t reg1, uint32_t ipb);
int ioinst_handle_ssch(CPUS390XState *env, uint64_t reg1, uint32_t ipb);
int ioinst_handle_stcrw(CPUS390XState *env, uint32_t ipb);
int ioinst_handle_stsch(CPUS390XState *env, uint64_t reg1, uint32_t ipb);
int ioinst_handle_tsch(CPUS390XState *env, uint64_t reg1, uint32_t ipb);
int ioinst_handle_chsc(CPUS390XState *env, uint32_t ipb);
int ioinst_handle_tpi(CPUS390XState *env, uint32_t ipb);
int ioinst_handle_schm(CPUS390XState *env, uint64_t reg1, uint64_t reg2,
                       uint32_t ipb);
int ioinst_handle_rsch(CPUS390XState *env, uint64_t reg1);
int ioinst_handle_rchp(CPUS390XState *env, uint64_t reg1);
int ioinst_handle_sal(CPUS390XState *env, uint64_t reg1);

#endif
Commit	Line	Data
db1c8f53 CH	1	/*
	2	* S/390 channel I/O instructions
	3	*
	4	* Copyright 2012 IBM Corp.
	5	* Author(s): Cornelia Huck <[email protected]>
	6	*
	7	* This work is licensed under the terms of the GNU GPL, version 2 or (at
	8	* your option) any later version. See the COPYING file in the top-level
	9	* directory.
	10	*/
	11
	12	#ifndef IOINST_S390X_H
	13	#define IOINST_S390X_H
	14	/*
	15	* Channel I/O related definitions, as defined in the Principles
	16	* Of Operation (and taken from the Linux implementation).
	17	*/
	18
	19	/* subchannel status word (command mode only) */
	20	typedef struct SCSW {
	21	uint16_t flags;
	22	uint16_t ctrl;
	23	uint32_t cpa;
	24	uint8_t dstat;
	25	uint8_t cstat;
	26	uint16_t count;
	27	} QEMU_PACKED SCSW;
	28
	29	#define SCSW_FLAGS_MASK_KEY 0xf000
	30	#define SCSW_FLAGS_MASK_SCTL 0x0800
	31	#define SCSW_FLAGS_MASK_ESWF 0x0400
	32	#define SCSW_FLAGS_MASK_CC 0x0300
	33	#define SCSW_FLAGS_MASK_FMT 0x0080
	34	#define SCSW_FLAGS_MASK_PFCH 0x0040
	35	#define SCSW_FLAGS_MASK_ISIC 0x0020
	36	#define SCSW_FLAGS_MASK_ALCC 0x0010
	37	#define SCSW_FLAGS_MASK_SSI 0x0008
	38	#define SCSW_FLAGS_MASK_ZCC 0x0004
	39	#define SCSW_FLAGS_MASK_ECTL 0x0002
	40	#define SCSW_FLAGS_MASK_PNO 0x0001
	41
	42	#define SCSW_CTRL_MASK_FCTL 0x7000
	43	#define SCSW_CTRL_MASK_ACTL 0x0fe0
	44	#define SCSW_CTRL_MASK_STCTL 0x001f
	45
	46	#define SCSW_FCTL_CLEAR_FUNC 0x1000
	47	#define SCSW_FCTL_HALT_FUNC 0x2000
	48	#define SCSW_FCTL_START_FUNC 0x4000
	49
	50	#define SCSW_ACTL_SUSP 0x0020
	51	#define SCSW_ACTL_DEVICE_ACTIVE 0x0040
	52	#define SCSW_ACTL_SUBCH_ACTIVE 0x0080
	53	#define SCSW_ACTL_CLEAR_PEND 0x0100
	54	#define SCSW_ACTL_HALT_PEND 0x0200
	55	#define SCSW_ACTL_START_PEND 0x0400
	56	#define SCSW_ACTL_RESUME_PEND 0x0800
	57
	58	#define SCSW_STCTL_STATUS_PEND 0x0001
	59	#define SCSW_STCTL_SECONDARY 0x0002
	60	#define SCSW_STCTL_PRIMARY 0x0004
	61	#define SCSW_STCTL_INTERMEDIATE 0x0008
	62	#define SCSW_STCTL_ALERT 0x0010
	63
	64	#define SCSW_DSTAT_ATTENTION 0x80
65	#define SCSW_DSTAT_STAT_MOD 0x40
66	#define SCSW_DSTAT_CU_END 0x20
67	#define SCSW_DSTAT_BUSY 0x10
68	#define SCSW_DSTAT_CHANNEL_END 0x08
69	#define SCSW_DSTAT_DEVICE_END 0x04
70	#define SCSW_DSTAT_UNIT_CHECK 0x02
71	#define SCSW_DSTAT_UNIT_EXCEP 0x01
72
73	#define SCSW_CSTAT_PCI 0x80
74	#define SCSW_CSTAT_INCORR_LEN 0x40
75	#define SCSW_CSTAT_PROG_CHECK 0x20
76	#define SCSW_CSTAT_PROT_CHECK 0x10
77	#define SCSW_CSTAT_DATA_CHECK 0x08
78	#define SCSW_CSTAT_CHN_CTRL_CHK 0x04
79	#define SCSW_CSTAT_INTF_CTRL_CHK 0x02
80	#define SCSW_CSTAT_CHAIN_CHECK 0x01
81
82	/* path management control word */
83	typedef struct PMCW {
84	uint32_t intparm;
85	uint16_t flags;
86	uint16_t devno;
87	uint8_t lpm;
88	uint8_t pnom;
89	uint8_t lpum;
90	uint8_t pim;
91	uint16_t mbi;
92	uint8_t pom;
93	uint8_t pam;
94	uint8_t chpid[8];
95	uint32_t chars;
96	} QEMU_PACKED PMCW;
97
98	#define PMCW_FLAGS_MASK_QF 0x8000
99	#define PMCW_FLAGS_MASK_W 0x4000
100	#define PMCW_FLAGS_MASK_ISC 0x3800
101	#define PMCW_FLAGS_MASK_ENA 0x0080
102	#define PMCW_FLAGS_MASK_LM 0x0060
103	#define PMCW_FLAGS_MASK_MME 0x0018
104	#define PMCW_FLAGS_MASK_MP 0x0004
105	#define PMCW_FLAGS_MASK_TF 0x0002
106	#define PMCW_FLAGS_MASK_DNV 0x0001
107	#define PMCW_FLAGS_MASK_INVALID 0x0700
108
109	#define PMCW_CHARS_MASK_ST 0x00e00000
110	#define PMCW_CHARS_MASK_MBFC 0x00000004
111	#define PMCW_CHARS_MASK_XMWME 0x00000002
112	#define PMCW_CHARS_MASK_CSENSE 0x00000001
113	#define PMCW_CHARS_MASK_INVALID 0xff1ffff8
114
115	/* subchannel information block */
116	typedef struct SCHIB {
117	PMCW pmcw;
118	SCSW scsw;
119	uint64_t mba;
120	uint8_t mda[4];
121	} QEMU_PACKED SCHIB;
122
123	/* interruption response block */
124	typedef struct IRB {
125	SCSW scsw;
126	uint32_t esw[5];
127	uint32_t ecw[8];
128	uint32_t emw[8];
129	} QEMU_PACKED IRB;
130
131	/* operation request block */
132	typedef struct ORB {
133	uint32_t intparm;
134	uint16_t ctrl0;
135	uint8_t lpm;
136	uint8_t ctrl1;
137	uint32_t cpa;
138	} QEMU_PACKED ORB;
139
140	#define ORB_CTRL0_MASK_KEY 0xf000
141	#define ORB_CTRL0_MASK_SPND 0x0800
142	#define ORB_CTRL0_MASK_STR 0x0400
143	#define ORB_CTRL0_MASK_MOD 0x0200
144	#define ORB_CTRL0_MASK_SYNC 0x0100
145	#define ORB_CTRL0_MASK_FMT 0x0080
146	#define ORB_CTRL0_MASK_PFCH 0x0040
147	#define ORB_CTRL0_MASK_ISIC 0x0020
148	#define ORB_CTRL0_MASK_ALCC 0x0010
149	#define ORB_CTRL0_MASK_SSIC 0x0008
150	#define ORB_CTRL0_MASK_C64 0x0002
151	#define ORB_CTRL0_MASK_I2K 0x0001
152	#define ORB_CTRL0_MASK_INVALID 0x0004
153
154	#define ORB_CTRL1_MASK_ILS 0x80
155	#define ORB_CTRL1_MASK_MIDAW 0x40
156	#define ORB_CTRL1_MASK_ORBX 0x01
157	#define ORB_CTRL1_MASK_INVALID 0x3e
158
159	/* channel command word (type 1) */
160	typedef struct CCW1 {
161	uint8_t cmd_code;
162	uint8_t flags;
163	uint16_t count;
164	uint32_t cda;
165	} QEMU_PACKED CCW1;
166
167	#define CCW_FLAG_DC 0x80
168	#define CCW_FLAG_CC 0x40
169	#define CCW_FLAG_SLI 0x20
170	#define CCW_FLAG_SKIP 0x10
171	#define CCW_FLAG_PCI 0x08
172	#define CCW_FLAG_IDA 0x04
173	#define CCW_FLAG_SUSPEND 0x02
174
175	#define CCW_CMD_NOOP 0x03
176	#define CCW_CMD_BASIC_SENSE 0x04
177	#define CCW_CMD_TIC 0x08
178	#define CCW_CMD_SENSE_ID 0xe4
179
180	typedef struct CRW {
181	uint16_t flags;
182	uint16_t rsid;
183	} QEMU_PACKED CRW;
184
185	#define CRW_FLAGS_MASK_S 0x4000
186	#define CRW_FLAGS_MASK_R 0x2000
187	#define CRW_FLAGS_MASK_C 0x1000
188	#define CRW_FLAGS_MASK_RSC 0x0f00
189	#define CRW_FLAGS_MASK_A 0x0080
190	#define CRW_FLAGS_MASK_ERC 0x003f
191
192	#define CRW_ERC_INIT 0x02
193	#define CRW_ERC_IPI 0x04
194
195	#define CRW_RSC_SUBCH 0x3
196	#define CRW_RSC_CHP 0x4
197
50c8d9bf CH	198	/* I/O interruption code */
	199	typedef struct IOIntCode {
	200	uint32_t subsys_id;
	201	uint32_t intparm;
	202	uint32_t interrupt_id;
	203	} QEMU_PACKED IOIntCode;
	204
db1c8f53 CH	205	/* schid disintegration */
	206	#define IOINST_SCHID_ONE(_schid) ((_schid & 0x00010000) >> 16)
	207	#define IOINST_SCHID_M(_schid) ((_schid & 0x00080000) >> 19)
	208	#define IOINST_SCHID_CSSID(_schid) ((_schid & 0xff000000) >> 24)
	209	#define IOINST_SCHID_SSID(_schid) ((_schid & 0x00060000) >> 17)
	210	#define IOINST_SCHID_NR(_schid) (_schid & 0x0000ffff)
	211
91b0a8f3 CH	212	#define IO_INT_WORD_ISC(_int_word) ((_int_word & 0x38000000) >> 24)
	213	#define ISC_TO_ISC_BITS(_isc) ((0x80 >> _isc) << 24)
	214
db1c8f53 CH	215	int ioinst_disassemble_sch_ident(uint32_t value, int m, int cssid, int *ssid,
db1c8f53 CH	216	int *schid);
7b18aad5 CH	217	int ioinst_handle_xsch(CPUS390XState *env, uint64_t reg1);
	218	int ioinst_handle_csch(CPUS390XState *env, uint64_t reg1);
	219	int ioinst_handle_hsch(CPUS390XState *env, uint64_t reg1);
	220	int ioinst_handle_msch(CPUS390XState *env, uint64_t reg1, uint32_t ipb);
	221	int ioinst_handle_ssch(CPUS390XState *env, uint64_t reg1, uint32_t ipb);
	222	int ioinst_handle_stcrw(CPUS390XState *env, uint32_t ipb);
	223	int ioinst_handle_stsch(CPUS390XState *env, uint64_t reg1, uint32_t ipb);
	224	int ioinst_handle_tsch(CPUS390XState *env, uint64_t reg1, uint32_t ipb);
	225	int ioinst_handle_chsc(CPUS390XState *env, uint32_t ipb);
	226	int ioinst_handle_tpi(CPUS390XState *env, uint32_t ipb);
	227	int ioinst_handle_schm(CPUS390XState *env, uint64_t reg1, uint64_t reg2,
	228	uint32_t ipb);
	229	int ioinst_handle_rsch(CPUS390XState *env, uint64_t reg1);
	230	int ioinst_handle_rchp(CPUS390XState *env, uint64_t reg1);
	231	int ioinst_handle_sal(CPUS390XState *env, uint64_t reg1);
	232
db1c8f53	233	#endif