[qemu.git] / hw / tcx.c

/*
 * QEMU TCX Frame buffer
 * 
 * Copyright (c) 2003-2005 Fabrice Bellard
 * 
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "vl.h"

#define MAXX 1024
#define MAXY 768
#define TCX_DAC_NREGS 16

typedef struct TCXState {
    uint32_t addr;
    DisplayState *ds;
    uint8_t *vram;
    ram_addr_t vram_offset;
    uint16_t width, height;
    uint8_t r[256], g[256], b[256];
    uint32_t palette[256];
    uint8_t dac_index, dac_state;
} TCXState;

static void tcx_screen_dump(void *opaque, const char *filename);

/* XXX: unify with vga draw line functions */
static inline unsigned int rgb_to_pixel8(unsigned int r, unsigned int g, unsigned b)
{
    return ((r >> 5) << 5) | ((g >> 5) << 2) | (b >> 6);
}

static inline unsigned int rgb_to_pixel15(unsigned int r, unsigned int g, unsigned b)
{
    return ((r >> 3) << 10) | ((g >> 3) << 5) | (b >> 3);
}

static inline unsigned int rgb_to_pixel16(unsigned int r, unsigned int g, unsigned b)
{
    return ((r >> 3) << 11) | ((g >> 2) << 5) | (b >> 3);
}

static inline unsigned int rgb_to_pixel32(unsigned int r, unsigned int g, unsigned b)
{
    return (r << 16) | (g << 8) | b;
}

static void update_palette_entries(TCXState *s, int start, int end)
{
    int i;
    for(i = start; i < end; i++) {
        switch(s->ds->depth) {
        default:
        case 8:
            s->palette[i] = rgb_to_pixel8(s->r[i], s->g[i], s->b[i]);
            break;
        case 15:
            s->palette[i] = rgb_to_pixel15(s->r[i], s->g[i], s->b[i]);
            break;
        case 16:
            s->palette[i] = rgb_to_pixel16(s->r[i], s->g[i], s->b[i]);
            break;
        case 32:
            s->palette[i] = rgb_to_pixel32(s->r[i], s->g[i], s->b[i]);
            break;
        }
    }
}

static void tcx_draw_line32(TCXState *s1, uint8_t *d, 
			    const uint8_t *s, int width)
{
    int x;
    uint8_t val;
    uint32_t *p = (uint32_t *)d;

    for(x = 0; x < width; x++) {
	val = *s++;
        *p++ = s1->palette[val];
    }
}

static void tcx_draw_line16(TCXState *s1, uint8_t *d, 
			    const uint8_t *s, int width)
{
    int x;
    uint8_t val;
    uint16_t *p = (uint16_t *)d;

    for(x = 0; x < width; x++) {
	val = *s++;
        *p++ = s1->palette[val];
    }
}

static void tcx_draw_line8(TCXState *s1, uint8_t *d, 
			   const uint8_t *s, int width)
{
    int x;
    uint8_t val;

    for(x = 0; x < width; x++) {
	val = *s++;
        *d++ = s1->palette[val];
    }
}

/* Fixed line length 1024 allows us to do nice tricks not possible on
   VGA... */
static void tcx_update_display(void *opaque)
{
    TCXState *ts = opaque;
    ram_addr_t page, page_min, page_max;
    int y, y_start, dd, ds;
    uint8_t *d, *s;
    void (*f)(TCXState *s1, uint8_t *d, const uint8_t *s, int width);

    if (ts->ds->depth == 0)
	return;
    page = ts->vram_offset;
    y_start = -1;
    page_min = 0xffffffff;
    page_max = 0;
    d = ts->ds->data;
    s = ts->vram;
    dd = ts->ds->linesize;
    ds = 1024;

    switch (ts->ds->depth) {
    case 32:
	f = tcx_draw_line32;
	break;
    case 15:
    case 16:
	f = tcx_draw_line16;
	break;
    default:
    case 8:
	f = tcx_draw_line8;
	break;
    case 0:
	return;
    }
    
    for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE) {
	if (cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG)) {
	    if (y_start < 0)
                y_start = y;
            if (page < page_min)
                page_min = page;
            if (page > page_max)
                page_max = page;
	    f(ts, d, s, ts->width);
	    d += dd;
	    s += ds;
	    f(ts, d, s, ts->width);
	    d += dd;
	    s += ds;
	    f(ts, d, s, ts->width);
	    d += dd;
	    s += ds;
	    f(ts, d, s, ts->width);
	    d += dd;
	    s += ds;
	} else {
            if (y_start >= 0) {
                /* flush to display */
                dpy_update(ts->ds, 0, y_start, 
                           ts->width, y - y_start);
                y_start = -1;
            }
	    d += dd * 4;
	    s += ds * 4;
	}
    }
    if (y_start >= 0) {
	/* flush to display */
	dpy_update(ts->ds, 0, y_start, 
		   ts->width, y - y_start);
    }
    /* reset modified pages */
    if (page_min <= page_max) {
        cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE,
                                        VGA_DIRTY_FLAG);
    }
}

static void tcx_invalidate_display(void *opaque)
{
    TCXState *s = opaque;
    int i;

    for (i = 0; i < MAXX*MAXY; i += TARGET_PAGE_SIZE) {
	cpu_physical_memory_set_dirty(s->vram_offset + i);
    }
}

static void tcx_save(QEMUFile *f, void *opaque)
{
    TCXState *s = opaque;
    
    qemu_put_be32s(f, (uint32_t *)&s->addr);
    qemu_put_be32s(f, (uint32_t *)&s->vram);
    qemu_put_be16s(f, (uint16_t *)&s->height);
    qemu_put_be16s(f, (uint16_t *)&s->width);
    qemu_put_buffer(f, s->r, 256);
    qemu_put_buffer(f, s->g, 256);
    qemu_put_buffer(f, s->b, 256);
    qemu_put_8s(f, &s->dac_index);
    qemu_put_8s(f, &s->dac_state);
}

static int tcx_load(QEMUFile *f, void *opaque, int version_id)
{
    TCXState *s = opaque;
    
    if (version_id != 1)
        return -EINVAL;

    qemu_get_be32s(f, (uint32_t *)&s->addr);
    qemu_get_be32s(f, (uint32_t *)&s->vram);
    qemu_get_be16s(f, (uint16_t *)&s->height);
    qemu_get_be16s(f, (uint16_t *)&s->width);
    qemu_get_buffer(f, s->r, 256);
    qemu_get_buffer(f, s->g, 256);
    qemu_get_buffer(f, s->b, 256);
    qemu_get_8s(f, &s->dac_index);
    qemu_get_8s(f, &s->dac_state);
    update_palette_entries(s, 0, 256);
    return 0;
}

static void tcx_reset(void *opaque)
{
    TCXState *s = opaque;

    /* Initialize palette */
    memset(s->r, 0, 256);
    memset(s->g, 0, 256);
    memset(s->b, 0, 256);
    s->r[255] = s->g[255] = s->b[255] = 255;
    update_palette_entries(s, 0, 256);
    memset(s->vram, 0, MAXX*MAXY);
    cpu_physical_memory_reset_dirty(s->vram_offset, s->vram_offset + MAXX*MAXY,
                                    VGA_DIRTY_FLAG);
    s->dac_index = 0;
    s->dac_state = 0;
}

static uint32_t tcx_dac_readl(void *opaque, target_phys_addr_t addr)
{
    return 0;
}

static void tcx_dac_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
    TCXState *s = opaque;
    uint32_t saddr;

    saddr = (addr & (TCX_DAC_NREGS - 1)) >> 2;
    switch (saddr) {
    case 0:
	s->dac_index = val >> 24;
	s->dac_state = 0;
	break;
    case 1:
	switch (s->dac_state) {
	case 0:
	    s->r[s->dac_index] = val >> 24;
            update_palette_entries(s, s->dac_index, s->dac_index + 1);
	    s->dac_state++;
	    break;
	case 1:
	    s->g[s->dac_index] = val >> 24;
            update_palette_entries(s, s->dac_index, s->dac_index + 1);
	    s->dac_state++;
	    break;
	case 2:
	    s->b[s->dac_index] = val >> 24;
            update_palette_entries(s, s->dac_index, s->dac_index + 1);
	default:
	    s->dac_state = 0;
	    break;
	}
	break;
    default:
	break;
    }
    return;
}

static CPUReadMemoryFunc *tcx_dac_read[3] = {
    tcx_dac_readl,
    tcx_dac_readl,
    tcx_dac_readl,
};

static CPUWriteMemoryFunc *tcx_dac_write[3] = {
    tcx_dac_writel,
    tcx_dac_writel,
    tcx_dac_writel,
};

void tcx_init(DisplayState *ds, uint32_t addr, uint8_t *vram_base,
	      unsigned long vram_offset, int vram_size, int width, int height)
{
    TCXState *s;
    int io_memory;

    s = qemu_mallocz(sizeof(TCXState));
    if (!s)
        return;
    s->ds = ds;
    s->addr = addr;
    s->vram = vram_base;
    s->vram_offset = vram_offset;
    s->width = width;
    s->height = height;

    cpu_register_physical_memory(addr + 0x800000, vram_size, vram_offset);
    io_memory = cpu_register_io_memory(0, tcx_dac_read, tcx_dac_write, s);
    cpu_register_physical_memory(addr + 0x200000, TCX_DAC_NREGS, io_memory);

    graphic_console_init(s->ds, tcx_update_display, tcx_invalidate_display,
                         tcx_screen_dump, s);
    register_savevm("tcx", addr, 1, tcx_save, tcx_load, s);
    qemu_register_reset(tcx_reset, s);
    tcx_reset(s);
    dpy_resize(s->ds, width, height);
}

static void tcx_screen_dump(void *opaque, const char *filename)
{
    TCXState *s = opaque;
    FILE *f;
    uint8_t *d, *d1, v;
    int y, x;

    f = fopen(filename, "wb");
    if (!f)
        return;
    fprintf(f, "P6\n%d %d\n%d\n", s->width, s->height, 255);
    d1 = s->vram;
    for(y = 0; y < s->height; y++) {
        d = d1;
        for(x = 0; x < s->width; x++) {
            v = *d;
            fputc(s->r[v], f);
            fputc(s->g[v], f);
            fputc(s->b[v], f);
            d++;
        }
        d1 += MAXX;
    }
    fclose(f);
    return;
}
Commit	Line	Data
420557e8	1	/*
6f7e9aec	2	* QEMU TCX Frame buffer
420557e8	3	*
6f7e9aec	4	* Copyright (c) 2003-2005 Fabrice Bellard
420557e8 FB	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24	#include "vl.h"
	25
420557e8 FB	26	#define MAXX 1024
420557e8 FB	27	#define MAXY 768
6f7e9aec	28	#define TCX_DAC_NREGS 16
420557e8	29
420557e8	30	typedef struct TCXState {
8d5f07fa	31	uint32_t addr;
420557e8	32	DisplayState *ds;
8d5f07fa	33	uint8_t *vram;
550be127	34	ram_addr_t vram_offset;
6f7e9aec	35	uint16_t width, height;
e80cfcfc	36	uint8_t r[256], g[256], b[256];
21206a10	37	uint32_t palette[256];
6f7e9aec	38	uint8_t dac_index, dac_state;
420557e8 FB	39	} TCXState;
420557e8 FB	40
95219897 PB	41	static void tcx_screen_dump(void opaque, const char filename);
95219897 PB	42
21206a10 FB	43	/* XXX: unify with vga draw line functions */
	44	static inline unsigned int rgb_to_pixel8(unsigned int r, unsigned int g, unsigned b)
	45	{
	46	return ((r >> 5) << 5) \| ((g >> 5) << 2) \| (b >> 6);
	47	}
	48
	49	static inline unsigned int rgb_to_pixel15(unsigned int r, unsigned int g, unsigned b)
	50	{
	51	return ((r >> 3) << 10) \| ((g >> 3) << 5) \| (b >> 3);
	52	}
	53
	54	static inline unsigned int rgb_to_pixel16(unsigned int r, unsigned int g, unsigned b)
	55	{
	56	return ((r >> 3) << 11) \| ((g >> 2) << 5) \| (b >> 3);
	57	}
	58
	59	static inline unsigned int rgb_to_pixel32(unsigned int r, unsigned int g, unsigned b)
	60	{
	61	return (r << 16) \| (g << 8) \| b;
	62	}
	63
	64	static void update_palette_entries(TCXState *s, int start, int end)
	65	{
	66	int i;
	67	for(i = start; i < end; i++) {
	68	switch(s->ds->depth) {
	69	default:
	70	case 8:
	71	s->palette[i] = rgb_to_pixel8(s->r[i], s->g[i], s->b[i]);
	72	break;
	73	case 15:
	74	s->palette[i] = rgb_to_pixel15(s->r[i], s->g[i], s->b[i]);
	75	break;
	76	case 16:
	77	s->palette[i] = rgb_to_pixel16(s->r[i], s->g[i], s->b[i]);
	78	break;
	79	case 32:
	80	s->palette[i] = rgb_to_pixel32(s->r[i], s->g[i], s->b[i]);
	81	break;
	82	}
	83	}
	84	}
	85
e80cfcfc FB	86	static void tcx_draw_line32(TCXState s1, uint8_t d,
e80cfcfc FB	87	const uint8_t *s, int width)
420557e8	88	{
e80cfcfc FB	89	int x;
e80cfcfc FB	90	uint8_t val;
8bdc2159	91	uint32_t p = (uint32_t )d;
e80cfcfc FB	92
	93	for(x = 0; x < width; x++) {
	94	val = *s++;
8bdc2159	95	*p++ = s1->palette[val];
e80cfcfc	96	}
420557e8 FB	97	}
420557e8 FB	98
21206a10	99	static void tcx_draw_line16(TCXState s1, uint8_t d,
e80cfcfc FB	100	const uint8_t *s, int width)
	101	{
	102	int x;
	103	uint8_t val;
8bdc2159	104	uint16_t p = (uint16_t )d;
8d5f07fa	105
e80cfcfc FB	106	for(x = 0; x < width; x++) {
e80cfcfc FB	107	val = *s++;
8bdc2159	108	*p++ = s1->palette[val];
e80cfcfc FB	109	}
	110	}
	111
	112	static void tcx_draw_line8(TCXState s1, uint8_t d,
	113	const uint8_t *s, int width)
420557e8	114	{
e80cfcfc FB	115	int x;
	116	uint8_t val;
	117
	118	for(x = 0; x < width; x++) {
	119	val = *s++;
21206a10	120	*d++ = s1->palette[val];
420557e8	121	}
420557e8 FB	122	}
420557e8 FB	123
e80cfcfc FB	124	/* Fixed line length 1024 allows us to do nice tricks not possible on
e80cfcfc FB	125	VGA... */
95219897	126	static void tcx_update_display(void *opaque)
420557e8	127	{
e80cfcfc	128	TCXState *ts = opaque;
550be127 FB	129	ram_addr_t page, page_min, page_max;
550be127 FB	130	int y, y_start, dd, ds;
e80cfcfc FB	131	uint8_t d, s;
	132	void (f)(TCXState s1, uint8_t d, const uint8_t s, int width);
	133
	134	if (ts->ds->depth == 0)
	135	return;
6f7e9aec	136	page = ts->vram_offset;
e80cfcfc	137	y_start = -1;
550be127 FB	138	page_min = 0xffffffff;
550be127 FB	139	page_max = 0;
e80cfcfc	140	d = ts->ds->data;
6f7e9aec	141	s = ts->vram;
e80cfcfc FB	142	dd = ts->ds->linesize;
	143	ds = 1024;
	144
	145	switch (ts->ds->depth) {
	146	case 32:
	147	f = tcx_draw_line32;
	148	break;
21206a10 FB	149	case 15:
	150	case 16:
	151	f = tcx_draw_line16;
e80cfcfc FB	152	break;
	153	default:
	154	case 8:
	155	f = tcx_draw_line8;
	156	break;
	157	case 0:
	158	return;
	159	}
662f3c86	160
6f7e9aec	161	for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE) {
0a962c02	162	if (cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG)) {
e80cfcfc FB	163	if (y_start < 0)
	164	y_start = y;
	165	if (page < page_min)
	166	page_min = page;
	167	if (page > page_max)
	168	page_max = page;
6f7e9aec	169	f(ts, d, s, ts->width);
e80cfcfc FB	170	d += dd;
e80cfcfc FB	171	s += ds;
6f7e9aec	172	f(ts, d, s, ts->width);
e80cfcfc FB	173	d += dd;
e80cfcfc FB	174	s += ds;
6f7e9aec	175	f(ts, d, s, ts->width);
e80cfcfc FB	176	d += dd;
e80cfcfc FB	177	s += ds;
6f7e9aec	178	f(ts, d, s, ts->width);
e80cfcfc FB	179	d += dd;
	180	s += ds;
	181	} else {
	182	if (y_start >= 0) {
	183	/* flush to display */
	184	dpy_update(ts->ds, 0, y_start,
6f7e9aec	185	ts->width, y - y_start);
e80cfcfc FB	186	y_start = -1;
	187	}
	188	d += dd * 4;
	189	s += ds * 4;
	190	}
	191	}
	192	if (y_start >= 0) {
	193	/* flush to display */
	194	dpy_update(ts->ds, 0, y_start,
6f7e9aec	195	ts->width, y - y_start);
e80cfcfc FB	196	}
e80cfcfc FB	197	/* reset modified pages */
550be127	198	if (page_min <= page_max) {
0a962c02 FB	199	cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE,
0a962c02 FB	200	VGA_DIRTY_FLAG);
e80cfcfc	201	}
420557e8 FB	202	}
420557e8 FB	203
95219897	204	static void tcx_invalidate_display(void *opaque)
420557e8	205	{
e80cfcfc FB	206	TCXState *s = opaque;
	207	int i;
	208
	209	for (i = 0; i < MAXX*MAXY; i += TARGET_PAGE_SIZE) {
e80cfcfc	210	cpu_physical_memory_set_dirty(s->vram_offset + i);
e80cfcfc	211	}
420557e8 FB	212	}
420557e8 FB	213
e80cfcfc	214	static void tcx_save(QEMUFile f, void opaque)
420557e8 FB	215	{
420557e8 FB	216	TCXState *s = opaque;
e80cfcfc FB	217
	218	qemu_put_be32s(f, (uint32_t *)&s->addr);
	219	qemu_put_be32s(f, (uint32_t *)&s->vram);
6f7e9aec FB	220	qemu_put_be16s(f, (uint16_t *)&s->height);
6f7e9aec FB	221	qemu_put_be16s(f, (uint16_t *)&s->width);
e80cfcfc FB	222	qemu_put_buffer(f, s->r, 256);
	223	qemu_put_buffer(f, s->g, 256);
	224	qemu_put_buffer(f, s->b, 256);
6f7e9aec FB	225	qemu_put_8s(f, &s->dac_index);
6f7e9aec FB	226	qemu_put_8s(f, &s->dac_state);
420557e8 FB	227	}
420557e8 FB	228
e80cfcfc	229	static int tcx_load(QEMUFile f, void opaque, int version_id)
420557e8	230	{
e80cfcfc FB	231	TCXState *s = opaque;
	232
	233	if (version_id != 1)
	234	return -EINVAL;
	235
	236	qemu_get_be32s(f, (uint32_t *)&s->addr);
	237	qemu_get_be32s(f, (uint32_t *)&s->vram);
6f7e9aec FB	238	qemu_get_be16s(f, (uint16_t *)&s->height);
6f7e9aec FB	239	qemu_get_be16s(f, (uint16_t *)&s->width);
e80cfcfc FB	240	qemu_get_buffer(f, s->r, 256);
	241	qemu_get_buffer(f, s->g, 256);
	242	qemu_get_buffer(f, s->b, 256);
6f7e9aec FB	243	qemu_get_8s(f, &s->dac_index);
6f7e9aec FB	244	qemu_get_8s(f, &s->dac_state);
21206a10	245	update_palette_entries(s, 0, 256);
e80cfcfc	246	return 0;
420557e8 FB	247	}
420557e8 FB	248
e80cfcfc	249	static void tcx_reset(void *opaque)
420557e8	250	{
e80cfcfc FB	251	TCXState *s = opaque;
	252
	253	/* Initialize palette */
	254	memset(s->r, 0, 256);
	255	memset(s->g, 0, 256);
	256	memset(s->b, 0, 256);
	257	s->r[255] = s->g[255] = s->b[255] = 255;
21206a10	258	update_palette_entries(s, 0, 256);
e80cfcfc	259	memset(s->vram, 0, MAXX*MAXY);
0a962c02 FB	260	cpu_physical_memory_reset_dirty(s->vram_offset, s->vram_offset + MAXX*MAXY,
0a962c02 FB	261	VGA_DIRTY_FLAG);
6f7e9aec FB	262	s->dac_index = 0;
	263	s->dac_state = 0;
	264	}
	265
	266	static uint32_t tcx_dac_readl(void *opaque, target_phys_addr_t addr)
	267	{
	268	return 0;
	269	}
	270
	271	static void tcx_dac_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
	272	{
	273	TCXState *s = opaque;
	274	uint32_t saddr;
	275
	276	saddr = (addr & (TCX_DAC_NREGS - 1)) >> 2;
	277	switch (saddr) {
	278	case 0:
	279	s->dac_index = val >> 24;
	280	s->dac_state = 0;
	281	break;
	282	case 1:
	283	switch (s->dac_state) {
	284	case 0:
	285	s->r[s->dac_index] = val >> 24;
21206a10	286	update_palette_entries(s, s->dac_index, s->dac_index + 1);
6f7e9aec FB	287	s->dac_state++;
	288	break;
	289	case 1:
	290	s->g[s->dac_index] = val >> 24;
21206a10	291	update_palette_entries(s, s->dac_index, s->dac_index + 1);
6f7e9aec FB	292	s->dac_state++;
	293	break;
	294	case 2:
	295	s->b[s->dac_index] = val >> 24;
21206a10	296	update_palette_entries(s, s->dac_index, s->dac_index + 1);
6f7e9aec FB	297	default:
	298	s->dac_state = 0;
	299	break;
	300	}
	301	break;
	302	default:
	303	break;
	304	}
	305	return;
420557e8 FB	306	}
420557e8 FB	307
6f7e9aec FB	308	static CPUReadMemoryFunc *tcx_dac_read[3] = {
	309	tcx_dac_readl,
	310	tcx_dac_readl,
	311	tcx_dac_readl,
	312	};
	313
	314	static CPUWriteMemoryFunc *tcx_dac_write[3] = {
	315	tcx_dac_writel,
	316	tcx_dac_writel,
	317	tcx_dac_writel,
	318	};
	319
95219897 PB	320	void tcx_init(DisplayState ds, uint32_t addr, uint8_t vram_base,
95219897 PB	321	unsigned long vram_offset, int vram_size, int width, int height)
420557e8 FB	322	{
420557e8 FB	323	TCXState *s;
6f7e9aec	324	int io_memory;
420557e8 FB	325
	326	s = qemu_mallocz(sizeof(TCXState));
	327	if (!s)
95219897	328	return;
420557e8	329	s->ds = ds;
8d5f07fa	330	s->addr = addr;
e80cfcfc FB	331	s->vram = vram_base;
e80cfcfc FB	332	s->vram_offset = vram_offset;
6f7e9aec FB	333	s->width = width;
6f7e9aec FB	334	s->height = height;
e80cfcfc	335
6f7e9aec FB	336	cpu_register_physical_memory(addr + 0x800000, vram_size, vram_offset);
	337	io_memory = cpu_register_io_memory(0, tcx_dac_read, tcx_dac_write, s);
	338	cpu_register_physical_memory(addr + 0x200000, TCX_DAC_NREGS, io_memory);
e80cfcfc	339
95219897 PB	340	graphic_console_init(s->ds, tcx_update_display, tcx_invalidate_display,
95219897 PB	341	tcx_screen_dump, s);
e80cfcfc FB	342	register_savevm("tcx", addr, 1, tcx_save, tcx_load, s);
	343	qemu_register_reset(tcx_reset, s);
	344	tcx_reset(s);
6f7e9aec	345	dpy_resize(s->ds, width, height);
420557e8 FB	346	}
420557e8 FB	347
95219897	348	static void tcx_screen_dump(void opaque, const char filename)
8d5f07fa	349	{
e80cfcfc	350	TCXState *s = opaque;
8d5f07fa	351	FILE *f;
e80cfcfc	352	uint8_t d, d1, v;
8d5f07fa FB	353	int y, x;
	354
	355	f = fopen(filename, "wb");
	356	if (!f)
e80cfcfc	357	return;
6f7e9aec FB	358	fprintf(f, "P6\n%d %d\n%d\n", s->width, s->height, 255);
	359	d1 = s->vram;
	360	for(y = 0; y < s->height; y++) {
8d5f07fa	361	d = d1;
6f7e9aec	362	for(x = 0; x < s->width; x++) {
8d5f07fa	363	v = *d;
e80cfcfc FB	364	fputc(s->r[v], f);
	365	fputc(s->g[v], f);
	366	fputc(s->b[v], f);
8d5f07fa FB	367	d++;
8d5f07fa FB	368	}
e80cfcfc	369	d1 += MAXX;
8d5f07fa FB	370	}
	371	fclose(f);
	372	return;
	373	}
	374
	375
	376