[qemu.git] / hw / slavio_timer.c

/*
 * QEMU Sparc SLAVIO timer controller emulation
 *
 * Copyright (c) 2003-2005 Fabrice Bellard
 * 
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "vl.h"

//#define DEBUG_TIMER

#ifdef DEBUG_TIMER
#define DPRINTF(fmt, args...) \
do { printf("TIMER: " fmt , ##args); } while (0)
#define pic_set_irq_new(intctl, irq, level)                             \
    do { printf("TIMER: set_irq(%d): %d\n", (irq), (level));            \
        pic_set_irq_new((intctl), (irq),(level));} while (0)
#else
#define DPRINTF(fmt, args...)
#endif

/*
 * Registers of hardware timer in sun4m.
 *
 * This is the timer/counter part of chip STP2001 (Slave I/O), also
 * produced as NCR89C105. See
 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
 * 
 * The 31-bit counter is incremented every 500ns by bit 9. Bits 8..0
 * are zero. Bit 31 is 1 when count has been reached.
 *
 * Per-CPU timers interrupt local CPU, system timer uses normal
 * interrupt routing.
 *
 */

typedef struct SLAVIO_TIMERState {
    uint32_t limit, count, counthigh;
    int64_t count_load_time;
    int64_t expire_time;
    int64_t stop_time, tick_offset;
    QEMUTimer *irq_timer;
    int irq;
    int reached, stopped;
    int mode; // 0 = processor, 1 = user, 2 = system
    unsigned int cpu;
    void *intctl;
} SLAVIO_TIMERState;

#define TIMER_MAXADDR 0x1f
#define CNT_FREQ 2000000

// Update count, set irq, update expire_time
static void slavio_timer_get_out(SLAVIO_TIMERState *s)
{
    int out;
    int64_t diff, ticks, count;
    uint32_t limit;

    // There are three clock tick units: CPU ticks, register units
    // (nanoseconds), and counter ticks (500 ns).
    if (s->mode == 1 && s->stopped)
	ticks = s->stop_time;
    else
	ticks = qemu_get_clock(vm_clock) - s->tick_offset;

    out = (ticks > s->expire_time);
    if (out)
	s->reached = 0x80000000;
    if (!s->limit)
	limit = 0x7fffffff;
    else
	limit = s->limit;

    // Convert register units to counter ticks
    limit = limit >> 9;

    // Convert cpu ticks to counter ticks
    diff = muldiv64(ticks - s->count_load_time, CNT_FREQ, ticks_per_sec);

    // Calculate what the counter should be, convert to register
    // units
    count = diff % limit;
    s->count = count << 9;
    s->counthigh = count >> 22;

    // Expire time: CPU ticks left to next interrupt
    // Convert remaining counter ticks to CPU ticks
    s->expire_time = ticks + muldiv64(limit - count, ticks_per_sec, CNT_FREQ);

    DPRINTF("irq %d limit %d reached %d d %" PRId64 " count %d s->c %x diff %" PRId64 " stopped %d mode %d\n", s->irq, limit, s->reached?1:0, (ticks-s->count_load_time), count, s->count, s->expire_time - ticks, s->stopped, s->mode);

    if (s->mode != 1)
	pic_set_irq_cpu(s->intctl, s->irq, out, s->cpu);
}

// timer callback
static void slavio_timer_irq(void *opaque)
{
    SLAVIO_TIMERState *s = opaque;

    if (!s->irq_timer)
        return;
    slavio_timer_get_out(s);
    if (s->mode != 1)
	qemu_mod_timer(s->irq_timer, s->expire_time);
}

static uint32_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr)
{
    SLAVIO_TIMERState *s = opaque;
    uint32_t saddr;

    saddr = (addr & TIMER_MAXADDR) >> 2;
    switch (saddr) {
    case 0:
	// read limit (system counter mode) or read most signifying
	// part of counter (user mode)
	if (s->mode != 1) {
	    // clear irq
	    pic_set_irq_cpu(s->intctl, s->irq, 0, s->cpu);
	    s->reached = 0;
	    return s->limit;
	}
	else {
	    slavio_timer_get_out(s);
	    return s->counthigh & 0x7fffffff;
	}
    case 1:
	// read counter and reached bit (system mode) or read lsbits
	// of counter (user mode)
	slavio_timer_get_out(s);
	if (s->mode != 1)
	    return (s->count & 0x7fffffff) | s->reached;
	else
	    return s->count;
    case 3:
	// read start/stop status
	return s->stopped;
    case 4:
	// read user/system mode
	return s->mode & 1;
    default:
	return 0;
    }
}

static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
    SLAVIO_TIMERState *s = opaque;
    uint32_t saddr;

    saddr = (addr & TIMER_MAXADDR) >> 2;
    switch (saddr) {
    case 0:
	// set limit, reset counter
	s->count_load_time = qemu_get_clock(vm_clock);
	// fall through
    case 2:
	// set limit without resetting counter
	if (!val)
	    s->limit = 0x7fffffff;
	else
	    s->limit = val & 0x7fffffff;
	slavio_timer_irq(s);
	break;
    case 3:
	// start/stop user counter
	if (s->mode == 1) {
	    if (val & 1) {
		s->stop_time = qemu_get_clock(vm_clock);
		s->stopped = 1;
	    }
	    else {
		if (s->stopped)
		    s->tick_offset += qemu_get_clock(vm_clock) - s->stop_time;
		s->stopped = 0;
	    }
	}
	break;
    case 4:
	// bit 0: user (1) or system (0) counter mode
	if (s->mode == 0 || s->mode == 1)
	    s->mode = val & 1;
	break;
    default:
	break;
    }
}

static CPUReadMemoryFunc *slavio_timer_mem_read[3] = {
    slavio_timer_mem_readl,
    slavio_timer_mem_readl,
    slavio_timer_mem_readl,
};

static CPUWriteMemoryFunc *slavio_timer_mem_write[3] = {
    slavio_timer_mem_writel,
    slavio_timer_mem_writel,
    slavio_timer_mem_writel,
};

static void slavio_timer_save(QEMUFile *f, void *opaque)
{
    SLAVIO_TIMERState *s = opaque;

    qemu_put_be32s(f, &s->limit);
    qemu_put_be32s(f, &s->count);
    qemu_put_be32s(f, &s->counthigh);
    qemu_put_be64s(f, &s->count_load_time);
    qemu_put_be64s(f, &s->expire_time);
    qemu_put_be64s(f, &s->stop_time);
    qemu_put_be64s(f, &s->tick_offset);
    qemu_put_be32s(f, &s->irq);
    qemu_put_be32s(f, &s->reached);
    qemu_put_be32s(f, &s->stopped);
    qemu_put_be32s(f, &s->mode);
}

static int slavio_timer_load(QEMUFile *f, void *opaque, int version_id)
{
    SLAVIO_TIMERState *s = opaque;
    
    if (version_id != 1)
        return -EINVAL;

    qemu_get_be32s(f, &s->limit);
    qemu_get_be32s(f, &s->count);
    qemu_get_be32s(f, &s->counthigh);
    qemu_get_be64s(f, &s->count_load_time);
    qemu_get_be64s(f, &s->expire_time);
    qemu_get_be64s(f, &s->stop_time);
    qemu_get_be64s(f, &s->tick_offset);
    qemu_get_be32s(f, &s->irq);
    qemu_get_be32s(f, &s->reached);
    qemu_get_be32s(f, &s->stopped);
    qemu_get_be32s(f, &s->mode);
    return 0;
}

static void slavio_timer_reset(void *opaque)
{
    SLAVIO_TIMERState *s = opaque;

    s->limit = 0;
    s->count = 0;
    s->count_load_time = qemu_get_clock(vm_clock);;
    s->stop_time = s->count_load_time;
    s->tick_offset = 0;
    s->reached = 0;
    s->mode &= 2;
    s->stopped = 1;
    slavio_timer_get_out(s);
}

void slavio_timer_init(uint32_t addr, int irq, int mode, unsigned int cpu,
                       void *intctl)
{
    int slavio_timer_io_memory;
    SLAVIO_TIMERState *s;

    s = qemu_mallocz(sizeof(SLAVIO_TIMERState));
    if (!s)
        return;
    s->irq = irq;
    s->mode = mode;
    s->cpu = cpu;
    s->irq_timer = qemu_new_timer(vm_clock, slavio_timer_irq, s);
    s->intctl = intctl;

    slavio_timer_io_memory = cpu_register_io_memory(0, slavio_timer_mem_read,
						    slavio_timer_mem_write, s);
    cpu_register_physical_memory(addr, TIMER_MAXADDR, slavio_timer_io_memory);
    register_savevm("slavio_timer", addr, 1, slavio_timer_save, slavio_timer_load, s);
    qemu_register_reset(slavio_timer_reset, s);
    slavio_timer_reset(s);
}
Commit	Line	Data
e80cfcfc FB	1	/*
	2	* QEMU Sparc SLAVIO timer controller emulation
	3	*
66321a11	4	* Copyright (c) 2003-2005 Fabrice Bellard
e80cfcfc FB	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24	#include "vl.h"
	25
	26	//#define DEBUG_TIMER
	27
66321a11 FB	28	#ifdef DEBUG_TIMER
	29	#define DPRINTF(fmt, args...) \
	30	do { printf("TIMER: " fmt , ##args); } while (0)
52cc07d0 BS	31	#define pic_set_irq_new(intctl, irq, level) \
	32	do { printf("TIMER: set_irq(%d): %d\n", (irq), (level)); \
	33	pic_set_irq_new((intctl), (irq),(level));} while (0)
66321a11 FB	34	#else
	35	#define DPRINTF(fmt, args...)
	36	#endif
	37
e80cfcfc FB	38	/*
	39	* Registers of hardware timer in sun4m.
	40	*
	41	* This is the timer/counter part of chip STP2001 (Slave I/O), also
	42	* produced as NCR89C105. See
	43	* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
	44	*
	45	* The 31-bit counter is incremented every 500ns by bit 9. Bits 8..0
	46	* are zero. Bit 31 is 1 when count has been reached.
	47	*
ba3c64fb FB	48	* Per-CPU timers interrupt local CPU, system timer uses normal
	49	* interrupt routing.
	50	*
e80cfcfc FB	51	*/
	52
	53	typedef struct SLAVIO_TIMERState {
	54	uint32_t limit, count, counthigh;
	55	int64_t count_load_time;
	56	int64_t expire_time;
	57	int64_t stop_time, tick_offset;
	58	QEMUTimer *irq_timer;
	59	int irq;
	60	int reached, stopped;
	61	int mode; // 0 = processor, 1 = user, 2 = system
ba3c64fb	62	unsigned int cpu;
52cc07d0	63	void *intctl;
e80cfcfc FB	64	} SLAVIO_TIMERState;
	65
	66	#define TIMER_MAXADDR 0x1f
	67	#define CNT_FREQ 2000000
e80cfcfc FB	68
	69	// Update count, set irq, update expire_time
	70	static void slavio_timer_get_out(SLAVIO_TIMERState *s)
	71	{
	72	int out;
	73	int64_t diff, ticks, count;
	74	uint32_t limit;
	75
	76	// There are three clock tick units: CPU ticks, register units
	77	// (nanoseconds), and counter ticks (500 ns).
	78	if (s->mode == 1 && s->stopped)
	79	ticks = s->stop_time;
	80	else
	81	ticks = qemu_get_clock(vm_clock) - s->tick_offset;
	82
ba3c64fb	83	out = (ticks > s->expire_time);
e80cfcfc FB	84	if (out)
	85	s->reached = 0x80000000;
	86	if (!s->limit)
	87	limit = 0x7fffffff;
	88	else
	89	limit = s->limit;
	90
	91	// Convert register units to counter ticks
	92	limit = limit >> 9;
	93
	94	// Convert cpu ticks to counter ticks
	95	diff = muldiv64(ticks - s->count_load_time, CNT_FREQ, ticks_per_sec);
	96
	97	// Calculate what the counter should be, convert to register
	98	// units
	99	count = diff % limit;
	100	s->count = count << 9;
	101	s->counthigh = count >> 22;
	102
	103	// Expire time: CPU ticks left to next interrupt
	104	// Convert remaining counter ticks to CPU ticks
	105	s->expire_time = ticks + muldiv64(limit - count, ticks_per_sec, CNT_FREQ);
	106
26a76461	107	DPRINTF("irq %d limit %d reached %d d %" PRId64 " count %d s->c %x diff %" PRId64 " stopped %d mode %d\n", s->irq, limit, s->reached?1:0, (ticks-s->count_load_time), count, s->count, s->expire_time - ticks, s->stopped, s->mode);
66321a11	108
e80cfcfc	109	if (s->mode != 1)
52cc07d0	110	pic_set_irq_cpu(s->intctl, s->irq, out, s->cpu);
e80cfcfc FB	111	}
	112
	113	// timer callback
	114	static void slavio_timer_irq(void *opaque)
	115	{
	116	SLAVIO_TIMERState *s = opaque;
	117
	118	if (!s->irq_timer)
	119	return;
	120	slavio_timer_get_out(s);
	121	if (s->mode != 1)
	122	qemu_mod_timer(s->irq_timer, s->expire_time);
	123	}
	124
	125	static uint32_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr)
	126	{
	127	SLAVIO_TIMERState *s = opaque;
	128	uint32_t saddr;
	129
	130	saddr = (addr & TIMER_MAXADDR) >> 2;
	131	switch (saddr) {
	132	case 0:
	133	// read limit (system counter mode) or read most signifying
	134	// part of counter (user mode)
	135	if (s->mode != 1) {
	136	// clear irq
52cc07d0	137	pic_set_irq_cpu(s->intctl, s->irq, 0, s->cpu);
e80cfcfc FB	138	s->reached = 0;
	139	return s->limit;
	140	}
	141	else {
	142	slavio_timer_get_out(s);
	143	return s->counthigh & 0x7fffffff;
	144	}
	145	case 1:
	146	// read counter and reached bit (system mode) or read lsbits
	147	// of counter (user mode)
	148	slavio_timer_get_out(s);
	149	if (s->mode != 1)
	150	return (s->count & 0x7fffffff) \| s->reached;
	151	else
	152	return s->count;
	153	case 3:
	154	// read start/stop status
	155	return s->stopped;
	156	case 4:
	157	// read user/system mode
	158	return s->mode & 1;
	159	default:
	160	return 0;
	161	}
	162	}
	163
	164	static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
	165	{
	166	SLAVIO_TIMERState *s = opaque;
	167	uint32_t saddr;
	168
	169	saddr = (addr & TIMER_MAXADDR) >> 2;
	170	switch (saddr) {
	171	case 0:
	172	// set limit, reset counter
	173	s->count_load_time = qemu_get_clock(vm_clock);
	174	// fall through
	175	case 2:
	176	// set limit without resetting counter
	177	if (!val)
	178	s->limit = 0x7fffffff;
	179	else
	180	s->limit = val & 0x7fffffff;
	181	slavio_timer_irq(s);
	182	break;
	183	case 3:
	184	// start/stop user counter
	185	if (s->mode == 1) {
	186	if (val & 1) {
	187	s->stop_time = qemu_get_clock(vm_clock);
	188	s->stopped = 1;
	189	}
	190	else {
	191	if (s->stopped)
	192	s->tick_offset += qemu_get_clock(vm_clock) - s->stop_time;
	193	s->stopped = 0;
	194	}
	195	}
	196	break;
	197	case 4:
	198	// bit 0: user (1) or system (0) counter mode
	199	if (s->mode == 0 \|\| s->mode == 1)
	200	s->mode = val & 1;
	201	break;
202	default:
203	break;
204	}
205	}
206
207	static CPUReadMemoryFunc *slavio_timer_mem_read[3] = {
208	slavio_timer_mem_readl,
209	slavio_timer_mem_readl,
210	slavio_timer_mem_readl,
211	};
212
213	static CPUWriteMemoryFunc *slavio_timer_mem_write[3] = {
214	slavio_timer_mem_writel,
215	slavio_timer_mem_writel,
216	slavio_timer_mem_writel,
217	};
218
219	static void slavio_timer_save(QEMUFile f, void opaque)
220	{
221	SLAVIO_TIMERState *s = opaque;
222
223	qemu_put_be32s(f, &s->limit);
224	qemu_put_be32s(f, &s->count);
225	qemu_put_be32s(f, &s->counthigh);
226	qemu_put_be64s(f, &s->count_load_time);
227	qemu_put_be64s(f, &s->expire_time);
228	qemu_put_be64s(f, &s->stop_time);
229	qemu_put_be64s(f, &s->tick_offset);
230	qemu_put_be32s(f, &s->irq);
231	qemu_put_be32s(f, &s->reached);
232	qemu_put_be32s(f, &s->stopped);
233	qemu_put_be32s(f, &s->mode);
234	}
235
236	static int slavio_timer_load(QEMUFile f, void opaque, int version_id)
237	{
238	SLAVIO_TIMERState *s = opaque;
239
240	if (version_id != 1)
241	return -EINVAL;
242
243	qemu_get_be32s(f, &s->limit);
244	qemu_get_be32s(f, &s->count);
245	qemu_get_be32s(f, &s->counthigh);
246	qemu_get_be64s(f, &s->count_load_time);
247	qemu_get_be64s(f, &s->expire_time);
248	qemu_get_be64s(f, &s->stop_time);
249	qemu_get_be64s(f, &s->tick_offset);
250	qemu_get_be32s(f, &s->irq);
251	qemu_get_be32s(f, &s->reached);
252	qemu_get_be32s(f, &s->stopped);
253	qemu_get_be32s(f, &s->mode);
254	return 0;
255	}
256
257	static void slavio_timer_reset(void *opaque)
258	{
259	SLAVIO_TIMERState *s = opaque;
260
261	s->limit = 0;
262	s->count = 0;
263	s->count_load_time = qemu_get_clock(vm_clock);;
264	s->stop_time = s->count_load_time;
265	s->tick_offset = 0;
266	s->reached = 0;
267	s->mode &= 2;
268	s->stopped = 1;
269	slavio_timer_get_out(s);
270	}
271
52cc07d0 BS	272	void slavio_timer_init(uint32_t addr, int irq, int mode, unsigned int cpu,
52cc07d0 BS	273	void *intctl)
e80cfcfc FB	274	{
	275	int slavio_timer_io_memory;
	276	SLAVIO_TIMERState *s;
	277
	278	s = qemu_mallocz(sizeof(SLAVIO_TIMERState));
	279	if (!s)
	280	return;
	281	s->irq = irq;
	282	s->mode = mode;
ba3c64fb	283	s->cpu = cpu;
e80cfcfc	284	s->irq_timer = qemu_new_timer(vm_clock, slavio_timer_irq, s);
52cc07d0	285	s->intctl = intctl;
e80cfcfc FB	286
	287	slavio_timer_io_memory = cpu_register_io_memory(0, slavio_timer_mem_read,
	288	slavio_timer_mem_write, s);
	289	cpu_register_physical_memory(addr, TIMER_MAXADDR, slavio_timer_io_memory);
	290	register_savevm("slavio_timer", addr, 1, slavio_timer_save, slavio_timer_load, s);
	291	qemu_register_reset(slavio_timer_reset, s);
	292	slavio_timer_reset(s);
	293	}