[qemu.git] / target / arm / sve.decode

# AArch64 SVE instruction descriptions
#
#  Copyright (c) 2017 Linaro, Ltd
#
# This library is free software; you can redistribute it and/or
# modify it under the terms of the GNU Lesser General Public
# License as published by the Free Software Foundation; either
# version 2 of the License, or (at your option) any later version.
#
# This library is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
# Lesser General Public License for more details.
#
# You should have received a copy of the GNU Lesser General Public
# License along with this library; if not, see <http://www.gnu.org/licenses/>.

#
# This file is processed by scripts/decodetree.py
#

###########################################################################
# Named fields.  These are primarily for disjoint fields.

%imm4_16_p1     16:4 !function=plus1
%imm6_22_5      22:1 5:5
%imm7_22_16     22:2 16:5
%imm8_16_10     16:5 10:3
%imm9_16_10     16:s6 10:3

# A combination of tsz:imm3 -- extract esize.
%tszimm_esz     22:2 5:5 !function=tszimm_esz
# A combination of tsz:imm3 -- extract (2 * esize) - (tsz:imm3)
%tszimm_shr     22:2 5:5 !function=tszimm_shr
# A combination of tsz:imm3 -- extract (tsz:imm3) - esize
%tszimm_shl     22:2 5:5 !function=tszimm_shl

# Similarly for the tszh/tszl pair at 22/16 for zzi
%tszimm16_esz   22:2 16:5 !function=tszimm_esz
%tszimm16_shr   22:2 16:5 !function=tszimm_shr
%tszimm16_shl   22:2 16:5 !function=tszimm_shl

# Signed 8-bit immediate, optionally shifted left by 8.
%sh8_i8s        5:9 !function=expand_imm_sh8s

# Either a copy of rd (at bit 0), or a different source
# as propagated via the MOVPRFX instruction.
%reg_movprfx    0:5

###########################################################################
# Named attribute sets.  These are used to make nice(er) names
# when creating helpers common to those for the individual
# instruction patterns.

&rr_esz         rd rn esz
&rri            rd rn imm
&rr_dbm         rd rn dbm
&rrri           rd rn rm imm
&rri_esz        rd rn imm esz
&rrr_esz        rd rn rm esz
&rpr_esz        rd pg rn esz
&rprr_s         rd pg rn rm s
&rprr_esz       rd pg rn rm esz
&rprrr_esz      rd pg rn rm ra esz
&rpri_esz       rd pg rn imm esz
&ptrue          rd esz pat s
&incdec_cnt     rd pat esz imm d u
&incdec2_cnt    rd rn pat esz imm d u

###########################################################################
# Named instruction formats.  These are generally used to
# reduce the amount of duplication between instruction patterns.

# Two operand with unused vector element size
@pd_pn_e0       ........ ........ ....... rn:4 . rd:4           &rr_esz esz=0

# Two operand
@pd_pn          ........ esz:2 .. .... ....... rn:4 . rd:4      &rr_esz
@rd_rn          ........ esz:2 ...... ...... rn:5 rd:5          &rr_esz

# Three operand with unused vector element size
@rd_rn_rm_e0    ........ ... rm:5 ... ... rn:5 rd:5             &rrr_esz esz=0

# Three predicate operand, with governing predicate, flag setting
@pd_pg_pn_pm_s  ........ . s:1 .. rm:4 .. pg:4 . rn:4 . rd:4    &rprr_s

# Three operand, vector element size
@rd_rn_rm       ........ esz:2 . rm:5 ... ... rn:5 rd:5         &rrr_esz
@rdn_rm         ........ esz:2 ...... ...... rm:5 rd:5 \
                &rrr_esz rn=%reg_movprfx

# Three operand with "memory" size, aka immediate left shift
@rd_rn_msz_rm   ........ ... rm:5 .... imm:2 rn:5 rd:5          &rrri

# Two register operand, with governing predicate, vector element size
@rdn_pg_rm      ........ esz:2 ... ... ... pg:3 rm:5 rd:5 \
                &rprr_esz rn=%reg_movprfx
@rdm_pg_rn      ........ esz:2 ... ... ... pg:3 rn:5 rd:5 \
                &rprr_esz rm=%reg_movprfx

# Three register operand, with governing predicate, vector element size
@rda_pg_rn_rm   ........ esz:2 . rm:5  ... pg:3 rn:5 rd:5 \
                &rprrr_esz ra=%reg_movprfx
@rdn_pg_ra_rm   ........ esz:2 . rm:5  ... pg:3 ra:5 rd:5 \
                &rprrr_esz rn=%reg_movprfx

# One register operand, with governing predicate, vector element size
@rd_pg_rn       ........ esz:2 ... ... ... pg:3 rn:5 rd:5       &rpr_esz

# Two register operands with a 6-bit signed immediate.
@rd_rn_i6       ........ ... rn:5 ..... imm:s6 rd:5             &rri

# Two register operand, one immediate operand, with predicate,
# element size encoded as TSZHL.  User must fill in imm.
@rdn_pg_tszimm  ........ .. ... ... ... pg:3 ..... rd:5 \
                &rpri_esz rn=%reg_movprfx esz=%tszimm_esz

# Similarly without predicate.
@rd_rn_tszimm   ........ .. ... ... ...... rn:5 rd:5 \
                &rri_esz esz=%tszimm16_esz

# Two register operand, one immediate operand, with 4-bit predicate.
# User must fill in imm.
@rdn_pg4        ........ esz:2 .. pg:4 ... ........ rd:5 \
                &rpri_esz rn=%reg_movprfx

# Two register operand, one encoded bitmask.
@rdn_dbm        ........ .. .... dbm:13 rd:5 \
                &rr_dbm rn=%reg_movprfx

# Basic Load/Store with 9-bit immediate offset
@pd_rn_i9       ........ ........ ...... rn:5 . rd:4    \
                &rri imm=%imm9_16_10
@rd_rn_i9       ........ ........ ...... rn:5 rd:5      \
                &rri imm=%imm9_16_10

# One register, pattern, and uint4+1.
# User must fill in U and D.
@incdec_cnt     ........ esz:2 .. .... ...... pat:5 rd:5 \
                &incdec_cnt imm=%imm4_16_p1
@incdec2_cnt    ........ esz:2 .. .... ...... pat:5 rd:5 \
                &incdec2_cnt imm=%imm4_16_p1 rn=%reg_movprfx

###########################################################################
# Instruction patterns.  Grouped according to the SVE encodingindex.xhtml.

### SVE Integer Arithmetic - Binary Predicated Group

# SVE bitwise logical vector operations (predicated)
ORR_zpzz        00000100 .. 011 000 000 ... ..... .....   @rdn_pg_rm
EOR_zpzz        00000100 .. 011 001 000 ... ..... .....   @rdn_pg_rm
AND_zpzz        00000100 .. 011 010 000 ... ..... .....   @rdn_pg_rm
BIC_zpzz        00000100 .. 011 011 000 ... ..... .....   @rdn_pg_rm

# SVE integer add/subtract vectors (predicated)
ADD_zpzz        00000100 .. 000 000 000 ... ..... .....   @rdn_pg_rm
SUB_zpzz        00000100 .. 000 001 000 ... ..... .....   @rdn_pg_rm
SUB_zpzz        00000100 .. 000 011 000 ... ..... .....   @rdm_pg_rn # SUBR

# SVE integer min/max/difference (predicated)
SMAX_zpzz       00000100 .. 001 000 000 ... ..... .....   @rdn_pg_rm
UMAX_zpzz       00000100 .. 001 001 000 ... ..... .....   @rdn_pg_rm
SMIN_zpzz       00000100 .. 001 010 000 ... ..... .....   @rdn_pg_rm
UMIN_zpzz       00000100 .. 001 011 000 ... ..... .....   @rdn_pg_rm
SABD_zpzz       00000100 .. 001 100 000 ... ..... .....   @rdn_pg_rm
UABD_zpzz       00000100 .. 001 101 000 ... ..... .....   @rdn_pg_rm

# SVE integer multiply/divide (predicated)
MUL_zpzz        00000100 .. 010 000 000 ... ..... .....   @rdn_pg_rm
SMULH_zpzz      00000100 .. 010 010 000 ... ..... .....   @rdn_pg_rm
UMULH_zpzz      00000100 .. 010 011 000 ... ..... .....   @rdn_pg_rm
# Note that divide requires size >= 2; below 2 is unallocated.
SDIV_zpzz       00000100 .. 010 100 000 ... ..... .....   @rdn_pg_rm
UDIV_zpzz       00000100 .. 010 101 000 ... ..... .....   @rdn_pg_rm
SDIV_zpzz       00000100 .. 010 110 000 ... ..... .....   @rdm_pg_rn # SDIVR
UDIV_zpzz       00000100 .. 010 111 000 ... ..... .....   @rdm_pg_rn # UDIVR

### SVE Integer Reduction Group

# SVE bitwise logical reduction (predicated)
ORV             00000100 .. 011 000 001 ... ..... .....         @rd_pg_rn
EORV            00000100 .. 011 001 001 ... ..... .....         @rd_pg_rn
ANDV            00000100 .. 011 010 001 ... ..... .....         @rd_pg_rn

# SVE integer add reduction (predicated)
# Note that saddv requires size != 3.
UADDV           00000100 .. 000 001 001 ... ..... .....         @rd_pg_rn
SADDV           00000100 .. 000 000 001 ... ..... .....         @rd_pg_rn

# SVE integer min/max reduction (predicated)
SMAXV           00000100 .. 001 000 001 ... ..... .....         @rd_pg_rn
UMAXV           00000100 .. 001 001 001 ... ..... .....         @rd_pg_rn
SMINV           00000100 .. 001 010 001 ... ..... .....         @rd_pg_rn
UMINV           00000100 .. 001 011 001 ... ..... .....         @rd_pg_rn

### SVE Shift by Immediate - Predicated Group

# SVE bitwise shift by immediate (predicated)
ASR_zpzi        00000100 .. 000 000 100 ... .. ... ..... \
                @rdn_pg_tszimm imm=%tszimm_shr
LSR_zpzi        00000100 .. 000 001 100 ... .. ... ..... \
                @rdn_pg_tszimm imm=%tszimm_shr
LSL_zpzi        00000100 .. 000 011 100 ... .. ... ..... \
                @rdn_pg_tszimm imm=%tszimm_shl
ASRD            00000100 .. 000 100 100 ... .. ... ..... \
                @rdn_pg_tszimm imm=%tszimm_shr

# SVE bitwise shift by vector (predicated)
ASR_zpzz        00000100 .. 010 000 100 ... ..... .....   @rdn_pg_rm
LSR_zpzz        00000100 .. 010 001 100 ... ..... .....   @rdn_pg_rm
LSL_zpzz        00000100 .. 010 011 100 ... ..... .....   @rdn_pg_rm
ASR_zpzz        00000100 .. 010 100 100 ... ..... .....   @rdm_pg_rn # ASRR
LSR_zpzz        00000100 .. 010 101 100 ... ..... .....   @rdm_pg_rn # LSRR
LSL_zpzz        00000100 .. 010 111 100 ... ..... .....   @rdm_pg_rn # LSLR

# SVE bitwise shift by wide elements (predicated)
# Note these require size != 3.
ASR_zpzw        00000100 .. 011 000 100 ... ..... .....         @rdn_pg_rm
LSR_zpzw        00000100 .. 011 001 100 ... ..... .....         @rdn_pg_rm
LSL_zpzw        00000100 .. 011 011 100 ... ..... .....         @rdn_pg_rm

### SVE Integer Arithmetic - Unary Predicated Group

# SVE unary bit operations (predicated)
# Note esz != 0 for FABS and FNEG.
CLS             00000100 .. 011 000 101 ... ..... .....         @rd_pg_rn
CLZ             00000100 .. 011 001 101 ... ..... .....         @rd_pg_rn
CNT_zpz         00000100 .. 011 010 101 ... ..... .....         @rd_pg_rn
CNOT            00000100 .. 011 011 101 ... ..... .....         @rd_pg_rn
NOT_zpz         00000100 .. 011 110 101 ... ..... .....         @rd_pg_rn
FABS            00000100 .. 011 100 101 ... ..... .....         @rd_pg_rn
FNEG            00000100 .. 011 101 101 ... ..... .....         @rd_pg_rn

# SVE integer unary operations (predicated)
# Note esz > original size for extensions.
ABS             00000100 .. 010 110 101 ... ..... .....         @rd_pg_rn
NEG             00000100 .. 010 111 101 ... ..... .....         @rd_pg_rn
SXTB            00000100 .. 010 000 101 ... ..... .....         @rd_pg_rn
UXTB            00000100 .. 010 001 101 ... ..... .....         @rd_pg_rn
SXTH            00000100 .. 010 010 101 ... ..... .....         @rd_pg_rn
UXTH            00000100 .. 010 011 101 ... ..... .....         @rd_pg_rn
SXTW            00000100 .. 010 100 101 ... ..... .....         @rd_pg_rn
UXTW            00000100 .. 010 101 101 ... ..... .....         @rd_pg_rn

### SVE Integer Multiply-Add Group

# SVE integer multiply-add writing addend (predicated)
MLA             00000100 .. 0 ..... 010 ... ..... .....   @rda_pg_rn_rm
MLS             00000100 .. 0 ..... 011 ... ..... .....   @rda_pg_rn_rm

# SVE integer multiply-add writing multiplicand (predicated)
MLA             00000100 .. 0 ..... 110 ... ..... .....   @rdn_pg_ra_rm # MAD
MLS             00000100 .. 0 ..... 111 ... ..... .....   @rdn_pg_ra_rm # MSB

### SVE Integer Arithmetic - Unpredicated Group

# SVE integer add/subtract vectors (unpredicated)
ADD_zzz         00000100 .. 1 ..... 000 000 ..... .....         @rd_rn_rm
SUB_zzz         00000100 .. 1 ..... 000 001 ..... .....         @rd_rn_rm
SQADD_zzz       00000100 .. 1 ..... 000 100 ..... .....         @rd_rn_rm
UQADD_zzz       00000100 .. 1 ..... 000 101 ..... .....         @rd_rn_rm
SQSUB_zzz       00000100 .. 1 ..... 000 110 ..... .....         @rd_rn_rm
UQSUB_zzz       00000100 .. 1 ..... 000 111 ..... .....         @rd_rn_rm

### SVE Logical - Unpredicated Group

# SVE bitwise logical operations (unpredicated)
AND_zzz         00000100 00 1 ..... 001 100 ..... .....         @rd_rn_rm_e0
ORR_zzz         00000100 01 1 ..... 001 100 ..... .....         @rd_rn_rm_e0
EOR_zzz         00000100 10 1 ..... 001 100 ..... .....         @rd_rn_rm_e0
BIC_zzz         00000100 11 1 ..... 001 100 ..... .....         @rd_rn_rm_e0

### SVE Index Generation Group

# SVE index generation (immediate start, immediate increment)
INDEX_ii        00000100 esz:2 1 imm2:s5 010000 imm1:s5 rd:5

# SVE index generation (immediate start, register increment)
INDEX_ir        00000100 esz:2 1 rm:5 010010 imm:s5 rd:5

# SVE index generation (register start, immediate increment)
INDEX_ri        00000100 esz:2 1 imm:s5 010001 rn:5 rd:5

# SVE index generation (register start, register increment)
INDEX_rr        00000100 .. 1 ..... 010011 ..... .....          @rd_rn_rm

### SVE Stack Allocation Group

# SVE stack frame adjustment
ADDVL           00000100 001 ..... 01010 ...... .....           @rd_rn_i6
ADDPL           00000100 011 ..... 01010 ...... .....           @rd_rn_i6

# SVE stack frame size
RDVL            00000100 101 11111 01010 imm:s6 rd:5

### SVE Bitwise Shift - Unpredicated Group

# SVE bitwise shift by immediate (unpredicated)
ASR_zzi         00000100 .. 1 ..... 1001 00 ..... ..... \
                @rd_rn_tszimm imm=%tszimm16_shr
LSR_zzi         00000100 .. 1 ..... 1001 01 ..... ..... \
                @rd_rn_tszimm imm=%tszimm16_shr
LSL_zzi         00000100 .. 1 ..... 1001 11 ..... ..... \
                @rd_rn_tszimm imm=%tszimm16_shl

# SVE bitwise shift by wide elements (unpredicated)
# Note esz != 3
ASR_zzw         00000100 .. 1 ..... 1000 00 ..... .....         @rd_rn_rm
LSR_zzw         00000100 .. 1 ..... 1000 01 ..... .....         @rd_rn_rm
LSL_zzw         00000100 .. 1 ..... 1000 11 ..... .....         @rd_rn_rm

### SVE Compute Vector Address Group

# SVE vector address generation
ADR_s32         00000100 00 1 ..... 1010 .. ..... .....         @rd_rn_msz_rm
ADR_u32         00000100 01 1 ..... 1010 .. ..... .....         @rd_rn_msz_rm
ADR_p32         00000100 10 1 ..... 1010 .. ..... .....         @rd_rn_msz_rm
ADR_p64         00000100 11 1 ..... 1010 .. ..... .....         @rd_rn_msz_rm

### SVE Integer Misc - Unpredicated Group

# SVE floating-point exponential accelerator
# Note esz != 0
FEXPA           00000100 .. 1 00000 101110 ..... .....          @rd_rn

# SVE floating-point trig select coefficient
# Note esz != 0
FTSSEL          00000100 .. 1 ..... 101100 ..... .....          @rd_rn_rm

### SVE Element Count Group

# SVE element count
CNT_r           00000100 .. 10 .... 1110 0 0 ..... .....    @incdec_cnt d=0 u=1

# SVE inc/dec register by element count
INCDEC_r        00000100 .. 11 .... 1110 0 d:1 ..... .....      @incdec_cnt u=1

# SVE saturating inc/dec register by element count
SINCDEC_r_32    00000100 .. 10 .... 1111 d:1 u:1 ..... .....    @incdec_cnt
SINCDEC_r_64    00000100 .. 11 .... 1111 d:1 u:1 ..... .....    @incdec_cnt

# SVE inc/dec vector by element count
# Note this requires esz != 0.
INCDEC_v        00000100 .. 1 1 .... 1100 0 d:1 ..... .....    @incdec2_cnt u=1

# SVE saturating inc/dec vector by element count
# Note these require esz != 0.
SINCDEC_v       00000100 .. 1 0 .... 1100 d:1 u:1 ..... .....   @incdec2_cnt

### SVE Bitwise Immediate Group

# SVE bitwise logical with immediate (unpredicated)
ORR_zzi         00000101 00 0000 ............. .....            @rdn_dbm
EOR_zzi         00000101 01 0000 ............. .....            @rdn_dbm
AND_zzi         00000101 10 0000 ............. .....            @rdn_dbm

# SVE broadcast bitmask immediate
DUPM            00000101 11 0000 dbm:13 rd:5

### SVE Integer Wide Immediate - Predicated Group

# SVE copy floating-point immediate (predicated)
FCPY            00000101 .. 01 .... 110 imm:8 .....             @rdn_pg4

# SVE copy integer immediate (predicated)
CPY_m_i         00000101 .. 01 .... 01 . ........ .....   @rdn_pg4 imm=%sh8_i8s
CPY_z_i         00000101 .. 01 .... 00 . ........ .....   @rdn_pg4 imm=%sh8_i8s

### SVE Permute - Extract Group

# SVE extract vector (immediate offset)
EXT             00000101 001 ..... 000 ... rm:5 rd:5 \
                &rrri rn=%reg_movprfx imm=%imm8_16_10

### SVE Permute - Unpredicated Group

# SVE broadcast general register
DUP_s           00000101 .. 1 00000 001110 ..... .....          @rd_rn

# SVE broadcast indexed element
DUP_x           00000101 .. 1 ..... 001000 rn:5 rd:5 \
                &rri imm=%imm7_22_16

# SVE insert SIMD&FP scalar register
INSR_f          00000101 .. 1 10100 001110 ..... .....          @rdn_rm

# SVE insert general register
INSR_r          00000101 .. 1 00100 001110 ..... .....          @rdn_rm

# SVE reverse vector elements
REV_v           00000101 .. 1 11000 001110 ..... .....          @rd_rn

# SVE vector table lookup
TBL             00000101 .. 1 ..... 001100 ..... .....          @rd_rn_rm

# SVE unpack vector elements
UNPK            00000101 esz:2 1100 u:1 h:1 001110 rn:5 rd:5

### SVE Predicate Logical Operations Group

# SVE predicate logical operations
AND_pppp        00100101 0. 00 .... 01 .... 0 .... 0 ....       @pd_pg_pn_pm_s
BIC_pppp        00100101 0. 00 .... 01 .... 0 .... 1 ....       @pd_pg_pn_pm_s
EOR_pppp        00100101 0. 00 .... 01 .... 1 .... 0 ....       @pd_pg_pn_pm_s
SEL_pppp        00100101 0. 00 .... 01 .... 1 .... 1 ....       @pd_pg_pn_pm_s
ORR_pppp        00100101 1. 00 .... 01 .... 0 .... 0 ....       @pd_pg_pn_pm_s
ORN_pppp        00100101 1. 00 .... 01 .... 0 .... 1 ....       @pd_pg_pn_pm_s
NOR_pppp        00100101 1. 00 .... 01 .... 1 .... 0 ....       @pd_pg_pn_pm_s
NAND_pppp       00100101 1. 00 .... 01 .... 1 .... 1 ....       @pd_pg_pn_pm_s

### SVE Predicate Misc Group

# SVE predicate test
PTEST           00100101 01 010000 11 pg:4 0 rn:4 0 0000

# SVE predicate initialize
PTRUE           00100101 esz:2 01100 s:1 111000 pat:5 0 rd:4

# SVE initialize FFR
SETFFR          00100101 0010 1100 1001 0000 0000 0000

# SVE zero predicate register
PFALSE          00100101 0001 1000 1110 0100 0000 rd:4

# SVE predicate read from FFR (predicated)
RDFFR_p         00100101 0 s:1 0110001111000 pg:4 0 rd:4

# SVE predicate read from FFR (unpredicated)
RDFFR           00100101 0001 1001 1111 0000 0000 rd:4

# SVE FFR write from predicate (WRFFR)
WRFFR           00100101 0010 1000 1001 000 rn:4 00000

# SVE predicate first active
PFIRST          00100101 01 011 000 11000 00 .... 0 ....        @pd_pn_e0

# SVE predicate next active
PNEXT           00100101 .. 011 001 11000 10 .... 0 ....        @pd_pn

### SVE Memory - 32-bit Gather and Unsized Contiguous Group

# SVE load predicate register
LDR_pri         10000101 10 ...... 000 ... ..... 0 ....         @pd_rn_i9

# SVE load vector register
LDR_zri         10000101 10 ...... 010 ... ..... .....          @rd_rn_i9
Commit	Line	Data
38388f7e RH	1	# AArch64 SVE instruction descriptions
	2	#
	3	# Copyright (c) 2017 Linaro, Ltd
	4	#
	5	# This library is free software; you can redistribute it and/or
	6	# modify it under the terms of the GNU Lesser General Public
	7	# License as published by the Free Software Foundation; either
	8	# version 2 of the License, or (at your option) any later version.
	9	#
	10	# This library is distributed in the hope that it will be useful,
	11	# but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	13	# Lesser General Public License for more details.
	14	#
	15	# You should have received a copy of the GNU Lesser General Public
	16	# License along with this library; if not, see <http://www.gnu.org/licenses/>.
	17
	18	#
	19	# This file is processed by scripts/decodetree.py
	20	#
	21
d1822297 RH	22	###########################################################################
	23	# Named fields. These are primarily for disjoint fields.
	24
f25a2361	25	%imm4_16_p1 16:4 !function=plus1
ccd841c3	26	%imm6_22_5 22:1 5:5
30562ab7	27	%imm7_22_16 22:2 16:5
b94f8f60	28	%imm8_16_10 16:5 10:3
d1822297 RH	29	%imm9_16_10 16:s6 10:3
d1822297 RH	30
ccd841c3 RH	31	# A combination of tsz:imm3 -- extract esize.
	32	%tszimm_esz 22:2 5:5 !function=tszimm_esz
	33	# A combination of tsz:imm3 -- extract (2 * esize) - (tsz:imm3)
	34	%tszimm_shr 22:2 5:5 !function=tszimm_shr
	35	# A combination of tsz:imm3 -- extract (tsz:imm3) - esize
	36	%tszimm_shl 22:2 5:5 !function=tszimm_shl
	37
d9d78dcc RH	38	# Similarly for the tszh/tszl pair at 22/16 for zzi
	39	%tszimm16_esz 22:2 16:5 !function=tszimm_esz
	40	%tszimm16_shr 22:2 16:5 !function=tszimm_shr
	41	%tszimm16_shl 22:2 16:5 !function=tszimm_shl
	42
f25a2361 RH	43	# Signed 8-bit immediate, optionally shifted left by 8.
	44	%sh8_i8s 5:9 !function=expand_imm_sh8s
	45
f97cfd59 RH	46	# Either a copy of rd (at bit 0), or a different source
	47	# as propagated via the MOVPRFX instruction.
	48	%reg_movprfx 0:5
	49
38388f7e RH	50	###########################################################################
	51	# Named attribute sets. These are used to make nice(er) names
	52	# when creating helpers common to those for the individual
	53	# instruction patterns.
	54
028e2a7b	55	&rr_esz rd rn esz
d1822297	56	&rri rd rn imm
e1fa1164	57	&rr_dbm rd rn dbm
4b242d9c	58	&rrri rd rn rm imm
d9d78dcc	59	&rri_esz rd rn imm esz
38388f7e	60	&rrr_esz rd rn rm esz
047cec97	61	&rpr_esz rd pg rn esz
516e246a	62	&rprr_s rd pg rn rm s
f97cfd59	63	&rprr_esz rd pg rn rm esz
96a36e4a	64	&rprrr_esz rd pg rn rm ra esz
ccd841c3	65	&rpri_esz rd pg rn imm esz
24e82e68 RH	66	&ptrue rd esz pat s
	67	&incdec_cnt rd pat esz imm d u
	68	&incdec2_cnt rd rn pat esz imm d u
38388f7e RH	69
	70	###########################################################################
	71	# Named instruction formats. These are generally used to
	72	# reduce the amount of duplication between instruction patterns.
	73
028e2a7b RH	74	# Two operand with unused vector element size
	75	@pd_pn_e0 ........ ........ ....... rn:4 . rd:4 &rr_esz esz=0
	76
	77	# Two operand
	78	@pd_pn ........ esz:2 .. .... ....... rn:4 . rd:4 &rr_esz
0762cd42	79	@rd_rn ........ esz:2 ...... ...... rn:5 rd:5 &rr_esz
028e2a7b	80
38388f7e RH	81	# Three operand with unused vector element size
	82	@rd_rn_rm_e0 ........ ... rm:5 ... ... rn:5 rd:5 &rrr_esz esz=0
	83
516e246a RH	84	# Three predicate operand, with governing predicate, flag setting
	85	@pd_pg_pn_pm_s ........ . s:1 .. rm:4 .. pg:4 . rn:4 . rd:4 &rprr_s
	86
fea98f9c RH	87	# Three operand, vector element size
fea98f9c RH	88	@rd_rn_rm ........ esz:2 . rm:5 ... ... rn:5 rd:5 &rrr_esz
30562ab7 RH	89	@rdn_rm ........ esz:2 ...... ...... rm:5 rd:5 \
30562ab7 RH	90	&rrr_esz rn=%reg_movprfx
fea98f9c	91
4b242d9c RH	92	# Three operand with "memory" size, aka immediate left shift
	93	@rd_rn_msz_rm ........ ... rm:5 .... imm:2 rn:5 rd:5 &rrri
	94
f97cfd59 RH	95	# Two register operand, with governing predicate, vector element size
	96	@rdn_pg_rm ........ esz:2 ... ... ... pg:3 rm:5 rd:5 \
	97	&rprr_esz rn=%reg_movprfx
	98	@rdm_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 \
	99	&rprr_esz rm=%reg_movprfx
	100
96a36e4a RH	101	# Three register operand, with governing predicate, vector element size
	102	@rda_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 rd:5 \
	103	&rprrr_esz ra=%reg_movprfx
	104	@rdn_pg_ra_rm ........ esz:2 . rm:5 ... pg:3 ra:5 rd:5 \
	105	&rprrr_esz rn=%reg_movprfx
	106
047cec97 RH	107	# One register operand, with governing predicate, vector element size
	108	@rd_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 &rpr_esz
	109
96f922cc RH	110	# Two register operands with a 6-bit signed immediate.
	111	@rd_rn_i6 ........ ... rn:5 ..... imm:s6 rd:5 &rri
	112
ccd841c3 RH	113	# Two register operand, one immediate operand, with predicate,
	114	# element size encoded as TSZHL. User must fill in imm.
	115	@rdn_pg_tszimm ........ .. ... ... ... pg:3 ..... rd:5 \
	116	&rpri_esz rn=%reg_movprfx esz=%tszimm_esz
	117
d9d78dcc RH	118	# Similarly without predicate.
	119	@rd_rn_tszimm ........ .. ... ... ...... rn:5 rd:5 \
	120	&rri_esz esz=%tszimm16_esz
	121
f25a2361 RH	122	# Two register operand, one immediate operand, with 4-bit predicate.
	123	# User must fill in imm.
	124	@rdn_pg4 ........ esz:2 .. pg:4 ... ........ rd:5 \
	125	&rpri_esz rn=%reg_movprfx
	126
e1fa1164 RH	127	# Two register operand, one encoded bitmask.
	128	@rdn_dbm ........ .. .... dbm:13 rd:5 \
	129	&rr_dbm rn=%reg_movprfx
	130
d1822297 RH	131	# Basic Load/Store with 9-bit immediate offset
	132	@pd_rn_i9 ........ ........ ...... rn:5 . rd:4 \
	133	&rri imm=%imm9_16_10
	134	@rd_rn_i9 ........ ........ ...... rn:5 rd:5 \
	135	&rri imm=%imm9_16_10
	136
24e82e68 RH	137	# One register, pattern, and uint4+1.
	138	# User must fill in U and D.
	139	@incdec_cnt ........ esz:2 .. .... ...... pat:5 rd:5 \
	140	&incdec_cnt imm=%imm4_16_p1
	141	@incdec2_cnt ........ esz:2 .. .... ...... pat:5 rd:5 \
	142	&incdec2_cnt imm=%imm4_16_p1 rn=%reg_movprfx
	143
38388f7e RH	144	###########################################################################
	145	# Instruction patterns. Grouped according to the SVE encodingindex.xhtml.
	146
f97cfd59 RH	147	### SVE Integer Arithmetic - Binary Predicated Group
	148
	149	# SVE bitwise logical vector operations (predicated)
	150	ORR_zpzz 00000100 .. 011 000 000 ... ..... ..... @rdn_pg_rm
	151	EOR_zpzz 00000100 .. 011 001 000 ... ..... ..... @rdn_pg_rm
	152	AND_zpzz 00000100 .. 011 010 000 ... ..... ..... @rdn_pg_rm
	153	BIC_zpzz 00000100 .. 011 011 000 ... ..... ..... @rdn_pg_rm
	154
	155	# SVE integer add/subtract vectors (predicated)
	156	ADD_zpzz 00000100 .. 000 000 000 ... ..... ..... @rdn_pg_rm
	157	SUB_zpzz 00000100 .. 000 001 000 ... ..... ..... @rdn_pg_rm
	158	SUB_zpzz 00000100 .. 000 011 000 ... ..... ..... @rdm_pg_rn # SUBR
	159
	160	# SVE integer min/max/difference (predicated)
	161	SMAX_zpzz 00000100 .. 001 000 000 ... ..... ..... @rdn_pg_rm
	162	UMAX_zpzz 00000100 .. 001 001 000 ... ..... ..... @rdn_pg_rm
	163	SMIN_zpzz 00000100 .. 001 010 000 ... ..... ..... @rdn_pg_rm
	164	UMIN_zpzz 00000100 .. 001 011 000 ... ..... ..... @rdn_pg_rm
	165	SABD_zpzz 00000100 .. 001 100 000 ... ..... ..... @rdn_pg_rm
	166	UABD_zpzz 00000100 .. 001 101 000 ... ..... ..... @rdn_pg_rm
	167
	168	# SVE integer multiply/divide (predicated)
	169	MUL_zpzz 00000100 .. 010 000 000 ... ..... ..... @rdn_pg_rm
	170	SMULH_zpzz 00000100 .. 010 010 000 ... ..... ..... @rdn_pg_rm
	171	UMULH_zpzz 00000100 .. 010 011 000 ... ..... ..... @rdn_pg_rm
	172	# Note that divide requires size >= 2; below 2 is unallocated.
	173	SDIV_zpzz 00000100 .. 010 100 000 ... ..... ..... @rdn_pg_rm
	174	UDIV_zpzz 00000100 .. 010 101 000 ... ..... ..... @rdn_pg_rm
	175	SDIV_zpzz 00000100 .. 010 110 000 ... ..... ..... @rdm_pg_rn # SDIVR
	176	UDIV_zpzz 00000100 .. 010 111 000 ... ..... ..... @rdm_pg_rn # UDIVR
	177
047cec97 RH	178	### SVE Integer Reduction Group
	179
	180	# SVE bitwise logical reduction (predicated)
	181	ORV 00000100 .. 011 000 001 ... ..... ..... @rd_pg_rn
	182	EORV 00000100 .. 011 001 001 ... ..... ..... @rd_pg_rn
	183	ANDV 00000100 .. 011 010 001 ... ..... ..... @rd_pg_rn
	184
	185	# SVE integer add reduction (predicated)
	186	# Note that saddv requires size != 3.
	187	UADDV 00000100 .. 000 001 001 ... ..... ..... @rd_pg_rn
	188	SADDV 00000100 .. 000 000 001 ... ..... ..... @rd_pg_rn
	189
	190	# SVE integer min/max reduction (predicated)
	191	SMAXV 00000100 .. 001 000 001 ... ..... ..... @rd_pg_rn
	192	UMAXV 00000100 .. 001 001 001 ... ..... ..... @rd_pg_rn
	193	SMINV 00000100 .. 001 010 001 ... ..... ..... @rd_pg_rn
	194	UMINV 00000100 .. 001 011 001 ... ..... ..... @rd_pg_rn
	195
ccd841c3 RH	196	### SVE Shift by Immediate - Predicated Group
	197
	198	# SVE bitwise shift by immediate (predicated)
	199	ASR_zpzi 00000100 .. 000 000 100 ... .. ... ..... \
	200	@rdn_pg_tszimm imm=%tszimm_shr
	201	LSR_zpzi 00000100 .. 000 001 100 ... .. ... ..... \
	202	@rdn_pg_tszimm imm=%tszimm_shr
	203	LSL_zpzi 00000100 .. 000 011 100 ... .. ... ..... \
	204	@rdn_pg_tszimm imm=%tszimm_shl
	205	ASRD 00000100 .. 000 100 100 ... .. ... ..... \
	206	@rdn_pg_tszimm imm=%tszimm_shr
	207
27721dbb RH	208	# SVE bitwise shift by vector (predicated)
	209	ASR_zpzz 00000100 .. 010 000 100 ... ..... ..... @rdn_pg_rm
	210	LSR_zpzz 00000100 .. 010 001 100 ... ..... ..... @rdn_pg_rm
	211	LSL_zpzz 00000100 .. 010 011 100 ... ..... ..... @rdn_pg_rm
	212	ASR_zpzz 00000100 .. 010 100 100 ... ..... ..... @rdm_pg_rn # ASRR
	213	LSR_zpzz 00000100 .. 010 101 100 ... ..... ..... @rdm_pg_rn # LSRR
	214	LSL_zpzz 00000100 .. 010 111 100 ... ..... ..... @rdm_pg_rn # LSLR
	215
fe7f8dfb RH	216	# SVE bitwise shift by wide elements (predicated)
	217	# Note these require size != 3.
	218	ASR_zpzw 00000100 .. 011 000 100 ... ..... ..... @rdn_pg_rm
	219	LSR_zpzw 00000100 .. 011 001 100 ... ..... ..... @rdn_pg_rm
	220	LSL_zpzw 00000100 .. 011 011 100 ... ..... ..... @rdn_pg_rm
	221
afac6d04 RH	222	### SVE Integer Arithmetic - Unary Predicated Group
	223
	224	# SVE unary bit operations (predicated)
	225	# Note esz != 0 for FABS and FNEG.
	226	CLS 00000100 .. 011 000 101 ... ..... ..... @rd_pg_rn
	227	CLZ 00000100 .. 011 001 101 ... ..... ..... @rd_pg_rn
	228	CNT_zpz 00000100 .. 011 010 101 ... ..... ..... @rd_pg_rn
	229	CNOT 00000100 .. 011 011 101 ... ..... ..... @rd_pg_rn
	230	NOT_zpz 00000100 .. 011 110 101 ... ..... ..... @rd_pg_rn
	231	FABS 00000100 .. 011 100 101 ... ..... ..... @rd_pg_rn
	232	FNEG 00000100 .. 011 101 101 ... ..... ..... @rd_pg_rn
	233
	234	# SVE integer unary operations (predicated)
	235	# Note esz > original size for extensions.
	236	ABS 00000100 .. 010 110 101 ... ..... ..... @rd_pg_rn
	237	NEG 00000100 .. 010 111 101 ... ..... ..... @rd_pg_rn
	238	SXTB 00000100 .. 010 000 101 ... ..... ..... @rd_pg_rn
	239	UXTB 00000100 .. 010 001 101 ... ..... ..... @rd_pg_rn
	240	SXTH 00000100 .. 010 010 101 ... ..... ..... @rd_pg_rn
	241	UXTH 00000100 .. 010 011 101 ... ..... ..... @rd_pg_rn
	242	SXTW 00000100 .. 010 100 101 ... ..... ..... @rd_pg_rn
	243	UXTW 00000100 .. 010 101 101 ... ..... ..... @rd_pg_rn
	244
96a36e4a RH	245	### SVE Integer Multiply-Add Group
	246
	247	# SVE integer multiply-add writing addend (predicated)
	248	MLA 00000100 .. 0 ..... 010 ... ..... ..... @rda_pg_rn_rm
	249	MLS 00000100 .. 0 ..... 011 ... ..... ..... @rda_pg_rn_rm
	250
	251	# SVE integer multiply-add writing multiplicand (predicated)
	252	MLA 00000100 .. 0 ..... 110 ... ..... ..... @rdn_pg_ra_rm # MAD
	253	MLS 00000100 .. 0 ..... 111 ... ..... ..... @rdn_pg_ra_rm # MSB
	254
fea98f9c RH	255	### SVE Integer Arithmetic - Unpredicated Group
	256
	257	# SVE integer add/subtract vectors (unpredicated)
	258	ADD_zzz 00000100 .. 1 ..... 000 000 ..... ..... @rd_rn_rm
	259	SUB_zzz 00000100 .. 1 ..... 000 001 ..... ..... @rd_rn_rm
	260	SQADD_zzz 00000100 .. 1 ..... 000 100 ..... ..... @rd_rn_rm
	261	UQADD_zzz 00000100 .. 1 ..... 000 101 ..... ..... @rd_rn_rm
	262	SQSUB_zzz 00000100 .. 1 ..... 000 110 ..... ..... @rd_rn_rm
	263	UQSUB_zzz 00000100 .. 1 ..... 000 111 ..... ..... @rd_rn_rm
	264
38388f7e RH	265	### SVE Logical - Unpredicated Group
	266
	267	# SVE bitwise logical operations (unpredicated)
	268	AND_zzz 00000100 00 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
	269	ORR_zzz 00000100 01 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
	270	EOR_zzz 00000100 10 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
	271	BIC_zzz 00000100 11 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
d1822297	272
9a56c9c3 RH	273	### SVE Index Generation Group
	274
	275	# SVE index generation (immediate start, immediate increment)
	276	INDEX_ii 00000100 esz:2 1 imm2:s5 010000 imm1:s5 rd:5
	277
	278	# SVE index generation (immediate start, register increment)
	279	INDEX_ir 00000100 esz:2 1 rm:5 010010 imm:s5 rd:5
	280
	281	# SVE index generation (register start, immediate increment)
	282	INDEX_ri 00000100 esz:2 1 imm:s5 010001 rn:5 rd:5
	283
	284	# SVE index generation (register start, register increment)
	285	INDEX_rr 00000100 .. 1 ..... 010011 ..... ..... @rd_rn_rm
	286
96f922cc RH	287	### SVE Stack Allocation Group
	288
	289	# SVE stack frame adjustment
	290	ADDVL 00000100 001 ..... 01010 ...... ..... @rd_rn_i6
	291	ADDPL 00000100 011 ..... 01010 ...... ..... @rd_rn_i6
	292
	293	# SVE stack frame size
	294	RDVL 00000100 101 11111 01010 imm:s6 rd:5
	295
d9d78dcc RH	296	### SVE Bitwise Shift - Unpredicated Group
	297
	298	# SVE bitwise shift by immediate (unpredicated)
	299	ASR_zzi 00000100 .. 1 ..... 1001 00 ..... ..... \
	300	@rd_rn_tszimm imm=%tszimm16_shr
	301	LSR_zzi 00000100 .. 1 ..... 1001 01 ..... ..... \
	302	@rd_rn_tszimm imm=%tszimm16_shr
	303	LSL_zzi 00000100 .. 1 ..... 1001 11 ..... ..... \
	304	@rd_rn_tszimm imm=%tszimm16_shl
	305
	306	# SVE bitwise shift by wide elements (unpredicated)
	307	# Note esz != 3
	308	ASR_zzw 00000100 .. 1 ..... 1000 00 ..... ..... @rd_rn_rm
	309	LSR_zzw 00000100 .. 1 ..... 1000 01 ..... ..... @rd_rn_rm
	310	LSL_zzw 00000100 .. 1 ..... 1000 11 ..... ..... @rd_rn_rm
	311
4b242d9c RH	312	### SVE Compute Vector Address Group
	313
	314	# SVE vector address generation
	315	ADR_s32 00000100 00 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm
	316	ADR_u32 00000100 01 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm
	317	ADR_p32 00000100 10 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm
	318	ADR_p64 00000100 11 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm
	319
0762cd42 RH	320	### SVE Integer Misc - Unpredicated Group
	321
	322	# SVE floating-point exponential accelerator
	323	# Note esz != 0
	324	FEXPA 00000100 .. 1 00000 101110 ..... ..... @rd_rn
	325
a1f233f2 RH	326	# SVE floating-point trig select coefficient
	327	# Note esz != 0
	328	FTSSEL 00000100 .. 1 ..... 101100 ..... ..... @rd_rn_rm
	329
24e82e68 RH	330	### SVE Element Count Group
	331
	332	# SVE element count
	333	CNT_r 00000100 .. 10 .... 1110 0 0 ..... ..... @incdec_cnt d=0 u=1
	334
	335	# SVE inc/dec register by element count
	336	INCDEC_r 00000100 .. 11 .... 1110 0 d:1 ..... ..... @incdec_cnt u=1
	337
	338	# SVE saturating inc/dec register by element count
	339	SINCDEC_r_32 00000100 .. 10 .... 1111 d:1 u:1 ..... ..... @incdec_cnt
	340	SINCDEC_r_64 00000100 .. 11 .... 1111 d:1 u:1 ..... ..... @incdec_cnt
	341
	342	# SVE inc/dec vector by element count
	343	# Note this requires esz != 0.
	344	INCDEC_v 00000100 .. 1 1 .... 1100 0 d:1 ..... ..... @incdec2_cnt u=1
	345
	346	# SVE saturating inc/dec vector by element count
	347	# Note these require esz != 0.
	348	SINCDEC_v 00000100 .. 1 0 .... 1100 d:1 u:1 ..... ..... @incdec2_cnt
516e246a	349
e1fa1164 RH	350	### SVE Bitwise Immediate Group
	351
	352	# SVE bitwise logical with immediate (unpredicated)
	353	ORR_zzi 00000101 00 0000 ............. ..... @rdn_dbm
	354	EOR_zzi 00000101 01 0000 ............. ..... @rdn_dbm
	355	AND_zzi 00000101 10 0000 ............. ..... @rdn_dbm
	356
	357	# SVE broadcast bitmask immediate
	358	DUPM 00000101 11 0000 dbm:13 rd:5
	359
f25a2361 RH	360	### SVE Integer Wide Immediate - Predicated Group
	361
	362	# SVE copy floating-point immediate (predicated)
	363	FCPY 00000101 .. 01 .... 110 imm:8 ..... @rdn_pg4
	364
	365	# SVE copy integer immediate (predicated)
	366	CPY_m_i 00000101 .. 01 .... 01 . ........ ..... @rdn_pg4 imm=%sh8_i8s
	367	CPY_z_i 00000101 .. 01 .... 00 . ........ ..... @rdn_pg4 imm=%sh8_i8s
	368
b94f8f60 RH	369	### SVE Permute - Extract Group
	370
	371	# SVE extract vector (immediate offset)
	372	EXT 00000101 001 ..... 000 ... rm:5 rd:5 \
	373	&rrri rn=%reg_movprfx imm=%imm8_16_10
	374
30562ab7 RH	375	### SVE Permute - Unpredicated Group
	376
	377	# SVE broadcast general register
	378	DUP_s 00000101 .. 1 00000 001110 ..... ..... @rd_rn
	379
	380	# SVE broadcast indexed element
	381	DUP_x 00000101 .. 1 ..... 001000 rn:5 rd:5 \
	382	&rri imm=%imm7_22_16
	383
	384	# SVE insert SIMD&FP scalar register
	385	INSR_f 00000101 .. 1 10100 001110 ..... ..... @rdn_rm
	386
	387	# SVE insert general register
	388	INSR_r 00000101 .. 1 00100 001110 ..... ..... @rdn_rm
	389
	390	# SVE reverse vector elements
	391	REV_v 00000101 .. 1 11000 001110 ..... ..... @rd_rn
	392
	393	# SVE vector table lookup
	394	TBL 00000101 .. 1 ..... 001100 ..... ..... @rd_rn_rm
	395
	396	# SVE unpack vector elements
	397	UNPK 00000101 esz:2 1100 u:1 h:1 001110 rn:5 rd:5
	398
e1fa1164 RH	399	### SVE Predicate Logical Operations Group
e1fa1164 RH	400
516e246a RH	401	# SVE predicate logical operations
	402	AND_pppp 00100101 0. 00 .... 01 .... 0 .... 0 .... @pd_pg_pn_pm_s
	403	BIC_pppp 00100101 0. 00 .... 01 .... 0 .... 1 .... @pd_pg_pn_pm_s
	404	EOR_pppp 00100101 0. 00 .... 01 .... 1 .... 0 .... @pd_pg_pn_pm_s
	405	SEL_pppp 00100101 0. 00 .... 01 .... 1 .... 1 .... @pd_pg_pn_pm_s
	406	ORR_pppp 00100101 1. 00 .... 01 .... 0 .... 0 .... @pd_pg_pn_pm_s
	407	ORN_pppp 00100101 1. 00 .... 01 .... 0 .... 1 .... @pd_pg_pn_pm_s
	408	NOR_pppp 00100101 1. 00 .... 01 .... 1 .... 0 .... @pd_pg_pn_pm_s
	409	NAND_pppp 00100101 1. 00 .... 01 .... 1 .... 1 .... @pd_pg_pn_pm_s
	410
9e18d7a6 RH	411	### SVE Predicate Misc Group
	412
	413	# SVE predicate test
	414	PTEST 00100101 01 010000 11 pg:4 0 rn:4 0 0000
	415
028e2a7b RH	416	# SVE predicate initialize
	417	PTRUE 00100101 esz:2 01100 s:1 111000 pat:5 0 rd:4
	418
	419	# SVE initialize FFR
	420	SETFFR 00100101 0010 1100 1001 0000 0000 0000
	421
	422	# SVE zero predicate register
	423	PFALSE 00100101 0001 1000 1110 0100 0000 rd:4
	424
	425	# SVE predicate read from FFR (predicated)
	426	RDFFR_p 00100101 0 s:1 0110001111000 pg:4 0 rd:4
	427
	428	# SVE predicate read from FFR (unpredicated)
	429	RDFFR 00100101 0001 1001 1111 0000 0000 rd:4
	430
	431	# SVE FFR write from predicate (WRFFR)
	432	WRFFR 00100101 0010 1000 1001 000 rn:4 00000
	433
	434	# SVE predicate first active
	435	PFIRST 00100101 01 011 000 11000 00 .... 0 .... @pd_pn_e0
	436
	437	# SVE predicate next active
	438	PNEXT 00100101 .. 011 001 11000 10 .... 0 .... @pd_pn
	439
d1822297 RH	440	### SVE Memory - 32-bit Gather and Unsized Contiguous Group
	441
	442	# SVE load predicate register
	443	LDR_pri 10000101 10 ...... 000 ... ..... 0 .... @pd_rn_i9
	444
	445	# SVE load vector register
	446	LDR_zri 10000101 10 ...... 010 ... ..... ..... @rd_rn_i9