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dd83b06a AF |
1 | /* |
2 | * QEMU CPU model | |
3 | * | |
4 | * Copyright (c) 2012 SUSE LINUX Products GmbH | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, see | |
18 | * <http://www.gnu.org/licenses/gpl-2.0.html> | |
19 | */ | |
20 | #ifndef QEMU_CPU_H | |
21 | #define QEMU_CPU_H | |
22 | ||
fcd7d003 | 23 | #include <signal.h> |
961f8395 | 24 | #include "hw/qdev-core.h" |
c658b94f | 25 | #include "exec/hwaddr.h" |
bdc44640 | 26 | #include "qemu/queue.h" |
1de7afc9 | 27 | #include "qemu/thread.h" |
4917cf44 | 28 | #include "qemu/tls.h" |
a23bbfda | 29 | #include "qemu/typedefs.h" |
dd83b06a | 30 | |
b5ba1cc6 QN |
31 | typedef int (*WriteCoreDumpFunction)(const void *buf, size_t size, |
32 | void *opaque); | |
c72bf468 | 33 | |
577f42c0 AF |
34 | /** |
35 | * vaddr: | |
36 | * Type wide enough to contain any #target_ulong virtual address. | |
37 | */ | |
38 | typedef uint64_t vaddr; | |
39 | #define VADDR_PRId PRId64 | |
40 | #define VADDR_PRIu PRIu64 | |
41 | #define VADDR_PRIo PRIo64 | |
42 | #define VADDR_PRIx PRIx64 | |
43 | #define VADDR_PRIX PRIX64 | |
44 | #define VADDR_MAX UINT64_MAX | |
45 | ||
dd83b06a AF |
46 | /** |
47 | * SECTION:cpu | |
48 | * @section_id: QEMU-cpu | |
49 | * @title: CPU Class | |
50 | * @short_description: Base class for all CPUs | |
51 | */ | |
52 | ||
53 | #define TYPE_CPU "cpu" | |
54 | ||
55 | #define CPU(obj) OBJECT_CHECK(CPUState, (obj), TYPE_CPU) | |
56 | #define CPU_CLASS(class) OBJECT_CLASS_CHECK(CPUClass, (class), TYPE_CPU) | |
57 | #define CPU_GET_CLASS(obj) OBJECT_GET_CLASS(CPUClass, (obj), TYPE_CPU) | |
58 | ||
59 | typedef struct CPUState CPUState; | |
60 | ||
c658b94f AF |
61 | typedef void (*CPUUnassignedAccess)(CPUState *cpu, hwaddr addr, |
62 | bool is_write, bool is_exec, int opaque, | |
63 | unsigned size); | |
64 | ||
bdf7ae5b AF |
65 | struct TranslationBlock; |
66 | ||
dd83b06a AF |
67 | /** |
68 | * CPUClass: | |
2b8c2754 AF |
69 | * @class_by_name: Callback to map -cpu command line model name to an |
70 | * instantiatable CPU type. | |
f5df5baf | 71 | * @reset: Callback to reset the #CPUState to its initial state. |
91b1df8c | 72 | * @reset_dump_flags: #CPUDumpFlags to use for reset logging. |
97a8ea5a | 73 | * @do_interrupt: Callback for interrupt handling. |
c658b94f | 74 | * @do_unassigned_access: Callback for unassigned access handling. |
f3659eee | 75 | * @memory_rw_debug: Callback for GDB memory access. |
878096ee AF |
76 | * @dump_state: Callback for dumping state. |
77 | * @dump_statistics: Callback for dumping statistics. | |
997395d3 | 78 | * @get_arch_id: Callback for getting architecture-dependent CPU ID. |
444d5590 | 79 | * @get_paging_enabled: Callback for inquiring whether paging is enabled. |
a23bbfda | 80 | * @get_memory_mapping: Callback for obtaining the memory mappings. |
f45748f1 | 81 | * @set_pc: Callback for setting the Program Counter register. |
bdf7ae5b AF |
82 | * @synchronize_from_tb: Callback for synchronizing state from a TCG |
83 | * #TranslationBlock. | |
00b941e5 | 84 | * @get_phys_page_debug: Callback for obtaining a physical address. |
5b50e790 AF |
85 | * @gdb_read_register: Callback for letting GDB read a register. |
86 | * @gdb_write_register: Callback for letting GDB write a register. | |
b170fce3 | 87 | * @vmsd: State description for migration. |
a0e372f0 | 88 | * @gdb_num_core_regs: Number of core registers accessible to GDB. |
5b24c641 | 89 | * @gdb_core_xml_file: File name for core registers GDB XML description. |
dd83b06a AF |
90 | * |
91 | * Represents a CPU family or model. | |
92 | */ | |
93 | typedef struct CPUClass { | |
94 | /*< private >*/ | |
961f8395 | 95 | DeviceClass parent_class; |
dd83b06a AF |
96 | /*< public >*/ |
97 | ||
2b8c2754 AF |
98 | ObjectClass *(*class_by_name)(const char *cpu_model); |
99 | ||
dd83b06a | 100 | void (*reset)(CPUState *cpu); |
91b1df8c | 101 | int reset_dump_flags; |
97a8ea5a | 102 | void (*do_interrupt)(CPUState *cpu); |
c658b94f | 103 | CPUUnassignedAccess do_unassigned_access; |
f3659eee AF |
104 | int (*memory_rw_debug)(CPUState *cpu, vaddr addr, |
105 | uint8_t *buf, int len, bool is_write); | |
878096ee AF |
106 | void (*dump_state)(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, |
107 | int flags); | |
108 | void (*dump_statistics)(CPUState *cpu, FILE *f, | |
109 | fprintf_function cpu_fprintf, int flags); | |
997395d3 | 110 | int64_t (*get_arch_id)(CPUState *cpu); |
444d5590 | 111 | bool (*get_paging_enabled)(const CPUState *cpu); |
a23bbfda AF |
112 | void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list, |
113 | Error **errp); | |
f45748f1 | 114 | void (*set_pc)(CPUState *cpu, vaddr value); |
bdf7ae5b | 115 | void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb); |
00b941e5 | 116 | hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr); |
5b50e790 AF |
117 | int (*gdb_read_register)(CPUState *cpu, uint8_t *buf, int reg); |
118 | int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); | |
b170fce3 | 119 | |
c72bf468 JF |
120 | int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu, |
121 | int cpuid, void *opaque); | |
122 | int (*write_elf64_qemunote)(WriteCoreDumpFunction f, CPUState *cpu, | |
123 | void *opaque); | |
124 | int (*write_elf32_note)(WriteCoreDumpFunction f, CPUState *cpu, | |
125 | int cpuid, void *opaque); | |
126 | int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu, | |
127 | void *opaque); | |
a0e372f0 AF |
128 | |
129 | const struct VMStateDescription *vmsd; | |
130 | int gdb_num_core_regs; | |
5b24c641 | 131 | const char *gdb_core_xml_file; |
dd83b06a AF |
132 | } CPUClass; |
133 | ||
a60f24b5 | 134 | struct KVMState; |
f7575c96 | 135 | struct kvm_run; |
a60f24b5 | 136 | |
dd83b06a AF |
137 | /** |
138 | * CPUState: | |
55e5c285 | 139 | * @cpu_index: CPU index (informative). |
ce3960eb AF |
140 | * @nr_cores: Number of cores within this CPU package. |
141 | * @nr_threads: Number of threads within this CPU. | |
1b1ed8dc | 142 | * @numa_node: NUMA node this CPU is belonging to. |
0d34282f | 143 | * @host_tid: Host thread ID. |
0315c31c | 144 | * @running: #true if CPU is currently running (usermode). |
61a46217 | 145 | * @created: Indicates whether the CPU thread has been successfully created. |
259186a7 AF |
146 | * @interrupt_request: Indicates a pending interrupt request. |
147 | * @halted: Nonzero if the CPU is in suspended state. | |
4fdeee7c | 148 | * @stop: Indicates a pending stop request. |
f324e766 | 149 | * @stopped: Indicates the CPU has been artificially stopped. |
378df4b2 PM |
150 | * @tcg_exit_req: Set to force TCG to stop executing linked TBs for this |
151 | * CPU and return to its top level loop. | |
ed2803da | 152 | * @singlestep_enabled: Flags for single-stepping. |
c05efcb1 | 153 | * @env_ptr: Pointer to subclass-specific CPUArchState field. |
d77953b9 | 154 | * @current_tb: Currently executing TB. |
eac8b355 | 155 | * @gdb_regs: Additional GDB registers. |
a0e372f0 | 156 | * @gdb_num_regs: Number of total registers accessible to GDB. |
35143f01 | 157 | * @gdb_num_g_regs: Number of registers in GDB 'g' packets. |
182735ef | 158 | * @next_cpu: Next CPU sharing TB cache. |
8737c51c | 159 | * @kvm_fd: vCPU file descriptor for KVM. |
dd83b06a AF |
160 | * |
161 | * State of one CPU core or thread. | |
162 | */ | |
163 | struct CPUState { | |
164 | /*< private >*/ | |
961f8395 | 165 | DeviceState parent_obj; |
dd83b06a AF |
166 | /*< public >*/ |
167 | ||
ce3960eb AF |
168 | int nr_cores; |
169 | int nr_threads; | |
1b1ed8dc | 170 | int numa_node; |
ce3960eb | 171 | |
814e612e | 172 | struct QemuThread *thread; |
bcba2a72 AF |
173 | #ifdef _WIN32 |
174 | HANDLE hThread; | |
175 | #endif | |
9f09e18a | 176 | int thread_id; |
0d34282f | 177 | uint32_t host_tid; |
0315c31c | 178 | bool running; |
f5c121b8 | 179 | struct QemuCond *halt_cond; |
c64ca814 | 180 | struct qemu_work_item *queued_work_first, *queued_work_last; |
216fc9a4 | 181 | bool thread_kicked; |
61a46217 | 182 | bool created; |
4fdeee7c | 183 | bool stop; |
f324e766 | 184 | bool stopped; |
fcd7d003 | 185 | volatile sig_atomic_t exit_request; |
378df4b2 | 186 | volatile sig_atomic_t tcg_exit_req; |
259186a7 | 187 | uint32_t interrupt_request; |
ed2803da | 188 | int singlestep_enabled; |
bcba2a72 | 189 | |
09daed84 EI |
190 | AddressSpace *as; |
191 | MemoryListener *tcg_as_listener; | |
192 | ||
c05efcb1 | 193 | void *env_ptr; /* CPUArchState */ |
d77953b9 | 194 | struct TranslationBlock *current_tb; |
eac8b355 | 195 | struct GDBRegisterState *gdb_regs; |
a0e372f0 | 196 | int gdb_num_regs; |
35143f01 | 197 | int gdb_num_g_regs; |
bdc44640 | 198 | QTAILQ_ENTRY(CPUState) node; |
d77953b9 | 199 | |
8737c51c | 200 | int kvm_fd; |
20d695a9 | 201 | bool kvm_vcpu_dirty; |
a60f24b5 | 202 | struct KVMState *kvm_state; |
f7575c96 | 203 | struct kvm_run *kvm_run; |
8737c51c | 204 | |
f5df5baf | 205 | /* TODO Move common fields from CPUArchState here. */ |
55e5c285 | 206 | int cpu_index; /* used by alpha TCG */ |
259186a7 | 207 | uint32_t halted; /* used by alpha, cris, ppc TCG */ |
dd83b06a AF |
208 | }; |
209 | ||
bdc44640 AF |
210 | QTAILQ_HEAD(CPUTailQ, CPUState); |
211 | extern struct CPUTailQ cpus; | |
212 | #define CPU_NEXT(cpu) QTAILQ_NEXT(cpu, node) | |
213 | #define CPU_FOREACH(cpu) QTAILQ_FOREACH(cpu, &cpus, node) | |
214 | #define CPU_FOREACH_SAFE(cpu, next_cpu) \ | |
215 | QTAILQ_FOREACH_SAFE(cpu, &cpus, node, next_cpu) | |
216 | #define first_cpu QTAILQ_FIRST(&cpus) | |
182735ef | 217 | |
4917cf44 AF |
218 | DECLARE_TLS(CPUState *, current_cpu); |
219 | #define current_cpu tls_var(current_cpu) | |
220 | ||
444d5590 AF |
221 | /** |
222 | * cpu_paging_enabled: | |
223 | * @cpu: The CPU whose state is to be inspected. | |
224 | * | |
225 | * Returns: %true if paging is enabled, %false otherwise. | |
226 | */ | |
227 | bool cpu_paging_enabled(const CPUState *cpu); | |
228 | ||
a23bbfda AF |
229 | /** |
230 | * cpu_get_memory_mapping: | |
231 | * @cpu: The CPU whose memory mappings are to be obtained. | |
232 | * @list: Where to write the memory mappings to. | |
233 | * @errp: Pointer for reporting an #Error. | |
234 | */ | |
235 | void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list, | |
236 | Error **errp); | |
237 | ||
c72bf468 JF |
238 | /** |
239 | * cpu_write_elf64_note: | |
240 | * @f: pointer to a function that writes memory to a file | |
241 | * @cpu: The CPU whose memory is to be dumped | |
242 | * @cpuid: ID number of the CPU | |
243 | * @opaque: pointer to the CPUState struct | |
244 | */ | |
245 | int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, | |
246 | int cpuid, void *opaque); | |
247 | ||
248 | /** | |
249 | * cpu_write_elf64_qemunote: | |
250 | * @f: pointer to a function that writes memory to a file | |
251 | * @cpu: The CPU whose memory is to be dumped | |
252 | * @cpuid: ID number of the CPU | |
253 | * @opaque: pointer to the CPUState struct | |
254 | */ | |
255 | int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu, | |
256 | void *opaque); | |
257 | ||
258 | /** | |
259 | * cpu_write_elf32_note: | |
260 | * @f: pointer to a function that writes memory to a file | |
261 | * @cpu: The CPU whose memory is to be dumped | |
262 | * @cpuid: ID number of the CPU | |
263 | * @opaque: pointer to the CPUState struct | |
264 | */ | |
265 | int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu, | |
266 | int cpuid, void *opaque); | |
267 | ||
268 | /** | |
269 | * cpu_write_elf32_qemunote: | |
270 | * @f: pointer to a function that writes memory to a file | |
271 | * @cpu: The CPU whose memory is to be dumped | |
272 | * @cpuid: ID number of the CPU | |
273 | * @opaque: pointer to the CPUState struct | |
274 | */ | |
275 | int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu, | |
276 | void *opaque); | |
dd83b06a | 277 | |
878096ee AF |
278 | /** |
279 | * CPUDumpFlags: | |
280 | * @CPU_DUMP_CODE: | |
281 | * @CPU_DUMP_FPU: dump FPU register state, not just integer | |
282 | * @CPU_DUMP_CCOP: dump info about TCG QEMU's condition code optimization state | |
283 | */ | |
284 | enum CPUDumpFlags { | |
285 | CPU_DUMP_CODE = 0x00010000, | |
286 | CPU_DUMP_FPU = 0x00020000, | |
287 | CPU_DUMP_CCOP = 0x00040000, | |
288 | }; | |
289 | ||
290 | /** | |
291 | * cpu_dump_state: | |
292 | * @cpu: The CPU whose state is to be dumped. | |
293 | * @f: File to dump to. | |
294 | * @cpu_fprintf: Function to dump with. | |
295 | * @flags: Flags what to dump. | |
296 | * | |
297 | * Dumps CPU state. | |
298 | */ | |
299 | void cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, | |
300 | int flags); | |
301 | ||
302 | /** | |
303 | * cpu_dump_statistics: | |
304 | * @cpu: The CPU whose state is to be dumped. | |
305 | * @f: File to dump to. | |
306 | * @cpu_fprintf: Function to dump with. | |
307 | * @flags: Flags what to dump. | |
308 | * | |
309 | * Dumps CPU statistics. | |
310 | */ | |
311 | void cpu_dump_statistics(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, | |
312 | int flags); | |
313 | ||
00b941e5 AF |
314 | #ifndef CONFIG_USER_ONLY |
315 | /** | |
316 | * cpu_get_phys_page_debug: | |
317 | * @cpu: The CPU to obtain the physical page address for. | |
318 | * @addr: The virtual address. | |
319 | * | |
320 | * Obtains the physical page corresponding to a virtual one. | |
321 | * Use it only for debugging because no protection checks are done. | |
322 | * | |
323 | * Returns: Corresponding physical page address or -1 if no page found. | |
324 | */ | |
325 | static inline hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr) | |
326 | { | |
327 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
328 | ||
329 | return cc->get_phys_page_debug(cpu, addr); | |
330 | } | |
331 | #endif | |
332 | ||
dd83b06a AF |
333 | /** |
334 | * cpu_reset: | |
335 | * @cpu: The CPU whose state is to be reset. | |
336 | */ | |
337 | void cpu_reset(CPUState *cpu); | |
338 | ||
2b8c2754 AF |
339 | /** |
340 | * cpu_class_by_name: | |
341 | * @typename: The CPU base type. | |
342 | * @cpu_model: The model string without any parameters. | |
343 | * | |
344 | * Looks up a CPU #ObjectClass matching name @cpu_model. | |
345 | * | |
346 | * Returns: A #CPUClass or %NULL if not matching class is found. | |
347 | */ | |
348 | ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model); | |
349 | ||
3993c6bd AF |
350 | /** |
351 | * qemu_cpu_has_work: | |
352 | * @cpu: The vCPU to check. | |
353 | * | |
354 | * Checks whether the CPU has work to do. | |
355 | * | |
356 | * Returns: %true if the CPU has work, %false otherwise. | |
357 | */ | |
358 | bool qemu_cpu_has_work(CPUState *cpu); | |
359 | ||
60e82579 AF |
360 | /** |
361 | * qemu_cpu_is_self: | |
362 | * @cpu: The vCPU to check against. | |
363 | * | |
364 | * Checks whether the caller is executing on the vCPU thread. | |
365 | * | |
366 | * Returns: %true if called from @cpu's thread, %false otherwise. | |
367 | */ | |
368 | bool qemu_cpu_is_self(CPUState *cpu); | |
369 | ||
c08d7424 AF |
370 | /** |
371 | * qemu_cpu_kick: | |
372 | * @cpu: The vCPU to kick. | |
373 | * | |
374 | * Kicks @cpu's thread. | |
375 | */ | |
376 | void qemu_cpu_kick(CPUState *cpu); | |
377 | ||
2fa45344 AF |
378 | /** |
379 | * cpu_is_stopped: | |
380 | * @cpu: The CPU to check. | |
381 | * | |
382 | * Checks whether the CPU is stopped. | |
383 | * | |
384 | * Returns: %true if run state is not running or if artificially stopped; | |
385 | * %false otherwise. | |
386 | */ | |
387 | bool cpu_is_stopped(CPUState *cpu); | |
388 | ||
f100f0b3 AF |
389 | /** |
390 | * run_on_cpu: | |
391 | * @cpu: The vCPU to run on. | |
392 | * @func: The function to be executed. | |
393 | * @data: Data to pass to the function. | |
394 | * | |
395 | * Schedules the function @func for execution on the vCPU @cpu. | |
396 | */ | |
397 | void run_on_cpu(CPUState *cpu, void (*func)(void *data), void *data); | |
398 | ||
3c02270d CV |
399 | /** |
400 | * async_run_on_cpu: | |
401 | * @cpu: The vCPU to run on. | |
402 | * @func: The function to be executed. | |
403 | * @data: Data to pass to the function. | |
404 | * | |
405 | * Schedules the function @func for execution on the vCPU @cpu asynchronously. | |
406 | */ | |
407 | void async_run_on_cpu(CPUState *cpu, void (*func)(void *data), void *data); | |
408 | ||
38d8f5c8 AF |
409 | /** |
410 | * qemu_get_cpu: | |
411 | * @index: The CPUState@cpu_index value of the CPU to obtain. | |
412 | * | |
413 | * Gets a CPU matching @index. | |
414 | * | |
415 | * Returns: The CPU or %NULL if there is no matching CPU. | |
416 | */ | |
417 | CPUState *qemu_get_cpu(int index); | |
418 | ||
69e5ff06 IM |
419 | /** |
420 | * cpu_exists: | |
421 | * @id: Guest-exposed CPU ID to lookup. | |
422 | * | |
423 | * Search for CPU with specified ID. | |
424 | * | |
425 | * Returns: %true - CPU is found, %false - CPU isn't found. | |
426 | */ | |
427 | bool cpu_exists(int64_t id); | |
428 | ||
c3affe56 AF |
429 | #ifndef CONFIG_USER_ONLY |
430 | ||
431 | typedef void (*CPUInterruptHandler)(CPUState *, int); | |
432 | ||
433 | extern CPUInterruptHandler cpu_interrupt_handler; | |
434 | ||
435 | /** | |
436 | * cpu_interrupt: | |
437 | * @cpu: The CPU to set an interrupt on. | |
438 | * @mask: The interupts to set. | |
439 | * | |
440 | * Invokes the interrupt handler. | |
441 | */ | |
442 | static inline void cpu_interrupt(CPUState *cpu, int mask) | |
443 | { | |
444 | cpu_interrupt_handler(cpu, mask); | |
445 | } | |
446 | ||
447 | #else /* USER_ONLY */ | |
448 | ||
449 | void cpu_interrupt(CPUState *cpu, int mask); | |
450 | ||
451 | #endif /* USER_ONLY */ | |
452 | ||
c658b94f AF |
453 | #ifndef CONFIG_USER_ONLY |
454 | ||
455 | static inline void cpu_unassigned_access(CPUState *cpu, hwaddr addr, | |
456 | bool is_write, bool is_exec, | |
457 | int opaque, unsigned size) | |
458 | { | |
459 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
460 | ||
461 | if (cc->do_unassigned_access) { | |
462 | cc->do_unassigned_access(cpu, addr, is_write, is_exec, opaque, size); | |
463 | } | |
464 | } | |
465 | ||
466 | #endif | |
467 | ||
d8ed887b AF |
468 | /** |
469 | * cpu_reset_interrupt: | |
470 | * @cpu: The CPU to clear the interrupt on. | |
471 | * @mask: The interrupt mask to clear. | |
472 | * | |
473 | * Resets interrupts on the vCPU @cpu. | |
474 | */ | |
475 | void cpu_reset_interrupt(CPUState *cpu, int mask); | |
476 | ||
60a3e17a AF |
477 | /** |
478 | * cpu_exit: | |
479 | * @cpu: The CPU to exit. | |
480 | * | |
481 | * Requests the CPU @cpu to exit execution. | |
482 | */ | |
483 | void cpu_exit(CPUState *cpu); | |
484 | ||
2993683b IM |
485 | /** |
486 | * cpu_resume: | |
487 | * @cpu: The CPU to resume. | |
488 | * | |
489 | * Resumes CPU, i.e. puts CPU into runnable state. | |
490 | */ | |
491 | void cpu_resume(CPUState *cpu); | |
dd83b06a | 492 | |
c643bed9 AF |
493 | /** |
494 | * qemu_init_vcpu: | |
495 | * @cpu: The vCPU to initialize. | |
496 | * | |
497 | * Initializes a vCPU. | |
498 | */ | |
499 | void qemu_init_vcpu(CPUState *cpu); | |
500 | ||
3825b28f AF |
501 | #define SSTEP_ENABLE 0x1 /* Enable simulated HW single stepping */ |
502 | #define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */ | |
503 | #define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */ | |
504 | ||
505 | /** | |
506 | * cpu_single_step: | |
507 | * @cpu: CPU to the flags for. | |
508 | * @enabled: Flags to enable. | |
509 | * | |
510 | * Enables or disables single-stepping for @cpu. | |
511 | */ | |
512 | void cpu_single_step(CPUState *cpu, int enabled); | |
513 | ||
1a1562f5 AF |
514 | #ifdef CONFIG_SOFTMMU |
515 | extern const struct VMStateDescription vmstate_cpu_common; | |
516 | #else | |
517 | #define vmstate_cpu_common vmstate_dummy | |
518 | #endif | |
519 | ||
520 | #define VMSTATE_CPU() { \ | |
521 | .name = "parent_obj", \ | |
522 | .size = sizeof(CPUState), \ | |
523 | .vmsd = &vmstate_cpu_common, \ | |
524 | .flags = VMS_STRUCT, \ | |
525 | .offset = 0, \ | |
526 | } | |
527 | ||
dd83b06a | 528 | #endif |