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graphical_console_init change (Stefano Stabellini)
[qemu.git] / hw / mips_malta.c
CommitLineData
5856de80
TS		 1/*
2 * QEMU Malta board support
3 *
4 * Copyright (c) 2006 Aurelien Jarno
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
87ecb68b
PB		 25#include "hw.h"
26#include "pc.h"
ded7ba9c 27#include "fdc.h"
87ecb68b
PB		 28#include "net.h"
29#include "boards.h"
30#include "smbus.h"
c8b153d7
TS		 31#include "block.h"
32#include "flash.h"
87ecb68b
PB		 33#include "mips.h"
34#include "pci.h"
35#include "qemu-char.h"
36#include "sysemu.h"
37#include "audio/audio.h"
38#include "boards.h"
3b3fb322 39#include "qemu-log.h"
5856de80 40
c8b153d7
TS		 41//#define DEBUG_BOARD_INIT
42
44cbbf18
TS		 43#ifdef TARGET_WORDS_BIGENDIAN
44#define BIOS_FILENAME "mips_bios.bin"
45#else
46#define BIOS_FILENAME "mipsel_bios.bin"
47#endif
48
60aa19ab 49#ifdef TARGET_MIPS64
74287114 50#define PHYS_TO_VIRT(x) ((x) | ~0x7fffffffULL)
5856de80 51#else
74287114 52#define PHYS_TO_VIRT(x) ((x) | ~0x7fffffffU)
5856de80
TS		 53#endif
54
74287114
TS		 55#define ENVP_ADDR (int32_t)0x80002000
56#define VIRT_TO_PHYS_ADDEND (-((int64_t)(int32_t)0x80000000))
5856de80
TS		 57
58#define ENVP_NB_ENTRIES 16
59#define ENVP_ENTRY_SIZE 256
60
e4bcb14c
TS		 61#define MAX_IDE_BUS 2
62
5856de80
TS		 63typedef struct {
64 uint32_t leds;
65 uint32_t brk;
66 uint32_t gpout;
130751ee 67 uint32_t i2cin;
5856de80
TS		 68 uint32_t i2coe;
69 uint32_t i2cout;
70 uint32_t i2csel;
71 CharDriverState *display;
72 char display_text[9];
a4bc3afc 73 SerialState *uart;
5856de80
TS		 74} MaltaFPGAState;
75
76static PITState *pit;
77
7df526e3
TS		 78static struct _loaderparams {
79 int ram_size;
80 const char *kernel_filename;
81 const char *kernel_cmdline;
82 const char *initrd_filename;
83} loaderparams;
84
5856de80
TS		 85/* Malta FPGA */
86static void malta_fpga_update_display(void *opaque)
87{
88 char leds_text[9];
89 int i;
90 MaltaFPGAState *s = opaque;
91
07cf0ba0
TS		 92 for (i = 7 ; i >= 0 ; i--) {
93 if (s->leds & (1 << i))
94 leds_text[i] = '#';
95 else
96 leds_text[i] = ' ';
87ee1669 97 }
07cf0ba0
TS		 98 leds_text[8] = '\0';
99
100 qemu_chr_printf(s->display, "\e[H\n\n|\e[32m%-8.8s\e[00m|\r\n", leds_text);
101 qemu_chr_printf(s->display, "\n\n\n\n|\e[31m%-8.8s\e[00m|", s->display_text);
5856de80
TS		 102}
103
130751ee
TS		 104/*
105 * EEPROM 24C01 / 24C02 emulation.
106 *
107 * Emulation for serial EEPROMs:
108 * 24C01 - 1024 bit (128 x 8)
109 * 24C02 - 2048 bit (256 x 8)
110 *
111 * Typical device names include Microchip 24C02SC or SGS Thomson ST24C02.
112 */
113
114//~ #define DEBUG
115
116#if defined(DEBUG)
117# define logout(fmt, args...) fprintf(stderr, "MALTA\t%-24s" fmt, __func__, ##args)
118#else
119# define logout(fmt, args...) ((void)0)
120#endif
121
122struct _eeprom24c0x_t {
123 uint8_t tick;
124 uint8_t address;
125 uint8_t command;
126 uint8_t ack;
127 uint8_t scl;
128 uint8_t sda;
129 uint8_t data;
130 //~ uint16_t size;
131 uint8_t contents[256];
132};
133
134typedef struct _eeprom24c0x_t eeprom24c0x_t;
135
136static eeprom24c0x_t eeprom = {
137 contents: {
138 /* 00000000: */ 0x80,0x08,0x04,0x0D,0x0A,0x01,0x40,0x00,
139 /* 00000008: */ 0x01,0x75,0x54,0x00,0x82,0x08,0x00,0x01,
140 /* 00000010: */ 0x8F,0x04,0x02,0x01,0x01,0x00,0x0E,0x00,
141 /* 00000018: */ 0x00,0x00,0x00,0x14,0x0F,0x14,0x2D,0x40,
142 /* 00000020: */ 0x15,0x08,0x15,0x08,0x00,0x00,0x00,0x00,
143 /* 00000028: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
144 /* 00000030: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
145 /* 00000038: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x12,0xD0,
146 /* 00000040: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
147 /* 00000048: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
148 /* 00000050: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
149 /* 00000058: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
150 /* 00000060: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
151 /* 00000068: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
152 /* 00000070: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
153 /* 00000078: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x64,0xF4,
154 },
155};
156
a5f1b965 157static uint8_t eeprom24c0x_read(void)
130751ee
TS		 158{
159 logout("%u: scl = %u, sda = %u, data = 0x%02x\n",
160 eeprom.tick, eeprom.scl, eeprom.sda, eeprom.data);
161 return eeprom.sda;
162}
163
164static void eeprom24c0x_write(int scl, int sda)
165{
166 if (eeprom.scl && scl && (eeprom.sda != sda)) {
167 logout("%u: scl = %u->%u, sda = %u->%u i2c %s\n",
168 eeprom.tick, eeprom.scl, scl, eeprom.sda, sda, sda ? "stop" : "start");
169 if (!sda) {
170 eeprom.tick = 1;
171 eeprom.command = 0;
172 }
173 } else if (eeprom.tick == 0 && !eeprom.ack) {
174 /* Waiting for start. */
175 logout("%u: scl = %u->%u, sda = %u->%u wait for i2c start\n",
176 eeprom.tick, eeprom.scl, scl, eeprom.sda, sda);
177 } else if (!eeprom.scl && scl) {
178 logout("%u: scl = %u->%u, sda = %u->%u trigger bit\n",
179 eeprom.tick, eeprom.scl, scl, eeprom.sda, sda);
180 if (eeprom.ack) {
181 logout("\ti2c ack bit = 0\n");
182 sda = 0;
183 eeprom.ack = 0;
184 } else if (eeprom.sda == sda) {
185 uint8_t bit = (sda != 0);
186 logout("\ti2c bit = %d\n", bit);
187 if (eeprom.tick < 9) {
188 eeprom.command <<= 1;
189 eeprom.command += bit;
190 eeprom.tick++;
191 if (eeprom.tick == 9) {
192 logout("\tcommand 0x%04x, %s\n", eeprom.command, bit ? "read" : "write");
193 eeprom.ack = 1;
194 }
195 } else if (eeprom.tick < 17) {
196 if (eeprom.command & 1) {
197 sda = ((eeprom.data & 0x80) != 0);
198 }
199 eeprom.address <<= 1;
200 eeprom.address += bit;
201 eeprom.tick++;
202 eeprom.data <<= 1;
203 if (eeprom.tick == 17) {
204 eeprom.data = eeprom.contents[eeprom.address];
205 logout("\taddress 0x%04x, data 0x%02x\n", eeprom.address, eeprom.data);
206 eeprom.ack = 1;
207 eeprom.tick = 0;
208 }
209 } else if (eeprom.tick >= 17) {
210 sda = 0;
211 }
212 } else {
213 logout("\tsda changed with raising scl\n");
214 }
215 } else {
216 logout("%u: scl = %u->%u, sda = %u->%u\n", eeprom.tick, eeprom.scl, scl, eeprom.sda, sda);
217 }
218 eeprom.scl = scl;
219 eeprom.sda = sda;
220}
221
5856de80
TS		 222static uint32_t malta_fpga_readl(void *opaque, target_phys_addr_t addr)
223{
224 MaltaFPGAState *s = opaque;
225 uint32_t val = 0;
226 uint32_t saddr;
227
228 saddr = (addr & 0xfffff);
229
230 switch (saddr) {
231
232 /* SWITCH Register */
233 case 0x00200:
234 val = 0x00000000; /* All switches closed */
235 break;
236
237 /* STATUS Register */
238 case 0x00208:
239#ifdef TARGET_WORDS_BIGENDIAN
240 val = 0x00000012;
241#else
242 val = 0x00000010;
243#endif
244 break;
245
246 /* JMPRS Register */
247 case 0x00210:
248 val = 0x00;
249 break;
250
251 /* LEDBAR Register */
252 case 0x00408:
253 val = s->leds;
254 break;
255
256 /* BRKRES Register */
257 case 0x00508:
258 val = s->brk;
259 break;
260
b6dc7ebb 261 /* UART Registers are handled directly by the serial device */
a4bc3afc 262
5856de80
TS		 263 /* GPOUT Register */
264 case 0x00a00:
265 val = s->gpout;
266 break;
267
268 /* XXX: implement a real I2C controller */
269
270 /* GPINP Register */
271 case 0x00a08:
272 /* IN = OUT until a real I2C control is implemented */
273 if (s->i2csel)
274 val = s->i2cout;
275 else
276 val = 0x00;
277 break;
278
279 /* I2CINP Register */
280 case 0x00b00:
130751ee 281 val = ((s->i2cin & ~1) | eeprom24c0x_read());
5856de80
TS		 282 break;
283
284 /* I2COE Register */
285 case 0x00b08:
286 val = s->i2coe;
287 break;
288
289 /* I2COUT Register */
290 case 0x00b10:
291 val = s->i2cout;
292 break;
293
294 /* I2CSEL Register */
295 case 0x00b18:
130751ee 296 val = s->i2csel;
5856de80
TS		 297 break;
298
299 default:
300#if 0
3594c774 301 printf ("malta_fpga_read: Bad register offset 0x" TARGET_FMT_lx "\n",
44cbbf18 302 addr);
5856de80
TS		 303#endif
304 break;
305 }
306 return val;
307}
308
309static void malta_fpga_writel(void *opaque, target_phys_addr_t addr,
310 uint32_t val)
311{
312 MaltaFPGAState *s = opaque;
313 uint32_t saddr;
314
315 saddr = (addr & 0xfffff);
316
317 switch (saddr) {
318
319 /* SWITCH Register */
320 case 0x00200:
321 break;
322
323 /* JMPRS Register */
324 case 0x00210:
325 break;
326
327 /* LEDBAR Register */
328 /* XXX: implement a 8-LED array */
329 case 0x00408:
330 s->leds = val & 0xff;
331 break;
332
333 /* ASCIIWORD Register */
334 case 0x00410:
335 snprintf(s->display_text, 9, "%08X", val);
336 malta_fpga_update_display(s);
337 break;
338
339 /* ASCIIPOS0 to ASCIIPOS7 Registers */
340 case 0x00418:
341 case 0x00420:
342 case 0x00428:
343 case 0x00430:
344 case 0x00438:
345 case 0x00440:
346 case 0x00448:
347 case 0x00450:
348 s->display_text[(saddr - 0x00418) >> 3] = (char) val;
349 malta_fpga_update_display(s);
350 break;
351
352 /* SOFTRES Register */
353 case 0x00500:
354 if (val == 0x42)
355 qemu_system_reset_request ();
356 break;
357
358 /* BRKRES Register */
359 case 0x00508:
360 s->brk = val & 0xff;
361 break;
362
b6dc7ebb 363 /* UART Registers are handled directly by the serial device */
a4bc3afc 364
5856de80
TS		 365 /* GPOUT Register */
366 case 0x00a00:
367 s->gpout = val & 0xff;
368 break;
369
370 /* I2COE Register */
371 case 0x00b08:
372 s->i2coe = val & 0x03;
373 break;
374
375 /* I2COUT Register */
376 case 0x00b10:
130751ee
TS		 377 eeprom24c0x_write(val & 0x02, val & 0x01);
378 s->i2cout = val;
5856de80
TS		 379 break;
380
381 /* I2CSEL Register */
382 case 0x00b18:
130751ee 383 s->i2csel = val & 0x01;
5856de80
TS		 384 break;
385
386 default:
387#if 0
3594c774 388 printf ("malta_fpga_write: Bad register offset 0x" TARGET_FMT_lx "\n",
44cbbf18 389 addr);
5856de80
TS		 390#endif
391 break;
392 }
393}
394
395static CPUReadMemoryFunc *malta_fpga_read[] = {
396 malta_fpga_readl,
397 malta_fpga_readl,
398 malta_fpga_readl
399};
400
401static CPUWriteMemoryFunc *malta_fpga_write[] = {
402 malta_fpga_writel,
403 malta_fpga_writel,
404 malta_fpga_writel
405};
406
9596ebb7 407static void malta_fpga_reset(void *opaque)
5856de80
TS		 408{
409 MaltaFPGAState *s = opaque;
410
411 s->leds = 0x00;
412 s->brk = 0x0a;
413 s->gpout = 0x00;
130751ee 414 s->i2cin = 0x3;
5856de80
TS		 415 s->i2coe = 0x0;
416 s->i2cout = 0x3;
417 s->i2csel = 0x1;
418
419 s->display_text[8] = '\0';
420 snprintf(s->display_text, 9, " ");
421 malta_fpga_update_display(s);
422}
423
9596ebb7 424static MaltaFPGAState *malta_fpga_init(target_phys_addr_t base, CPUState *env)
5856de80
TS		 425{
426 MaltaFPGAState *s;
a4bc3afc 427 CharDriverState *uart_chr;
5856de80
TS		 428 int malta;
429
430 s = (MaltaFPGAState *)qemu_mallocz(sizeof(MaltaFPGAState));
431
432 malta = cpu_register_io_memory(0, malta_fpga_read,
433 malta_fpga_write, s);
a4bc3afc 434
b6dc7ebb 435 cpu_register_physical_memory(base, 0x900, malta);
8da3ff18 436 /* 0xa00 is less than a page, so will still get the right offsets. */
b6dc7ebb 437 cpu_register_physical_memory(base + 0xa00, 0x100000 - 0xa00, malta);
5856de80 438
7cc0dd20 439 s->display = qemu_chr_open("fpga", "vc:320x200");
07cf0ba0
TS		 440 qemu_chr_printf(s->display, "\e[HMalta LEDBAR\r\n");
441 qemu_chr_printf(s->display, "+--------+\r\n");
442 qemu_chr_printf(s->display, "+ +\r\n");
443 qemu_chr_printf(s->display, "+--------+\r\n");
444 qemu_chr_printf(s->display, "\n");
445 qemu_chr_printf(s->display, "Malta ASCII\r\n");
446 qemu_chr_printf(s->display, "+--------+\r\n");
447 qemu_chr_printf(s->display, "+ +\r\n");
448 qemu_chr_printf(s->display, "+--------+\r\n");
449
7cc0dd20 450 uart_chr = qemu_chr_open("cbus", "vc:80Cx24C");
07cf0ba0 451 qemu_chr_printf(uart_chr, "CBUS UART\r\n");
b6cd0ea1
AJ		 452 s->uart =
453 serial_mm_init(base + 0x900, 3, env->irq[2], 230400, uart_chr, 1);
a4bc3afc 454
5856de80
TS		 455 malta_fpga_reset(s);
456 qemu_register_reset(malta_fpga_reset, s);
457
458 return s;
459}
460
461/* Audio support */
462#ifdef HAS_AUDIO
463static void audio_init (PCIBus *pci_bus)
464{
465 struct soundhw *c;
466 int audio_enabled = 0;
467
468 for (c = soundhw; !audio_enabled && c->name; ++c) {
469 audio_enabled = c->enabled;
470 }
471
472 if (audio_enabled) {
473 AudioState *s;
474
475 s = AUD_init ();
476 if (s) {
477 for (c = soundhw; c->name; ++c) {
5066b9f1
TS		 478 if (c->enabled)
479 c->init.init_pci (pci_bus, s);
5856de80
TS		 480 }
481 }
482 }
483}
484#endif
485
486/* Network support */
487static void network_init (PCIBus *pci_bus)
488{
489 int i;
5856de80
TS		 490
491 for(i = 0; i < nb_nics; i++) {
cb457d76
AL		 492 NICInfo *nd = &nd_table[i];
493 int devfn = -1;
494
495 if (i == 0 && (!nd->model || strcmp(nd->model, "pcnet") == 0))
5856de80 496 /* The malta board has a PCNet card using PCI SLOT 11 */
cb457d76
AL		 497 devfn = 88;
498
499 pci_nic_init(pci_bus, nd, devfn, "pcnet");
5856de80
TS		 500 }
501}
502
503/* ROM and pseudo bootloader
504
505 The following code implements a very very simple bootloader. It first
506 loads the registers a0 to a3 to the values expected by the OS, and
507 then jump at the kernel address.
508
509 The bootloader should pass the locations of the kernel arguments and
510 environment variables tables. Those tables contain the 32-bit address
511 of NULL terminated strings. The environment variables table should be
512 terminated by a NULL address.
513
514 For a simpler implementation, the number of kernel arguments is fixed
515 to two (the name of the kernel and the command line), and the two
516 tables are actually the same one.
517
518 The registers a0 to a3 should contain the following values:
519 a0 - number of kernel arguments
520 a1 - 32-bit address of the kernel arguments table
521 a2 - 32-bit address of the environment variables table
522 a3 - RAM size in bytes
523*/
524
74287114 525static void write_bootloader (CPUState *env, unsigned long bios_offset, int64_t kernel_entry)
5856de80
TS		 526{
527 uint32_t *p;
528
529 /* Small bootloader */
530 p = (uint32_t *) (phys_ram_base + bios_offset);
26ea0918 531 stl_raw(p++, 0x0bf00160); /* j 0x1fc00580 */
3ddd0065 532 stl_raw(p++, 0x00000000); /* nop */
5856de80 533
26ea0918 534 /* YAMON service vector */
3b46e624 535 stl_raw(phys_ram_base + bios_offset + 0x500, 0xbfc00580); /* start: */
26ea0918 536 stl_raw(phys_ram_base + bios_offset + 0x504, 0xbfc0083c); /* print_count: */
3b46e624 537 stl_raw(phys_ram_base + bios_offset + 0x520, 0xbfc00580); /* start: */
26ea0918
TS		 538 stl_raw(phys_ram_base + bios_offset + 0x52c, 0xbfc00800); /* flush_cache: */
539 stl_raw(phys_ram_base + bios_offset + 0x534, 0xbfc00808); /* print: */
540 stl_raw(phys_ram_base + bios_offset + 0x538, 0xbfc00800); /* reg_cpu_isr: */
541 stl_raw(phys_ram_base + bios_offset + 0x53c, 0xbfc00800); /* unred_cpu_isr: */
542 stl_raw(phys_ram_base + bios_offset + 0x540, 0xbfc00800); /* reg_ic_isr: */
543 stl_raw(phys_ram_base + bios_offset + 0x544, 0xbfc00800); /* unred_ic_isr: */
544 stl_raw(phys_ram_base + bios_offset + 0x548, 0xbfc00800); /* reg_esr: */
545 stl_raw(phys_ram_base + bios_offset + 0x54c, 0xbfc00800); /* unreg_esr: */
546 stl_raw(phys_ram_base + bios_offset + 0x550, 0xbfc00800); /* getchar: */
547 stl_raw(phys_ram_base + bios_offset + 0x554, 0xbfc00800); /* syscon_read: */
548
549
5856de80 550 /* Second part of the bootloader */
26ea0918 551 p = (uint32_t *) (phys_ram_base + bios_offset + 0x580);
d52fff71
TS		 552 stl_raw(p++, 0x24040002); /* addiu a0, zero, 2 */
553 stl_raw(p++, 0x3c1d0000 | (((ENVP_ADDR - 64) >> 16) & 0xffff)); /* lui sp, high(ENVP_ADDR) */
471ea271 554 stl_raw(p++, 0x37bd0000 | ((ENVP_ADDR - 64) & 0xffff)); /* ori sp, sp, low(ENVP_ADDR) */
3ddd0065 555 stl_raw(p++, 0x3c050000 | ((ENVP_ADDR >> 16) & 0xffff)); /* lui a1, high(ENVP_ADDR) */
471ea271 556 stl_raw(p++, 0x34a50000 | (ENVP_ADDR & 0xffff)); /* ori a1, a1, low(ENVP_ADDR) */
3ddd0065
TS		 557 stl_raw(p++, 0x3c060000 | (((ENVP_ADDR + 8) >> 16) & 0xffff)); /* lui a2, high(ENVP_ADDR + 8) */
558 stl_raw(p++, 0x34c60000 | ((ENVP_ADDR + 8) & 0xffff)); /* ori a2, a2, low(ENVP_ADDR + 8) */
7df526e3
TS		 559 stl_raw(p++, 0x3c070000 | (loaderparams.ram_size >> 16)); /* lui a3, high(ram_size) */
560 stl_raw(p++, 0x34e70000 | (loaderparams.ram_size & 0xffff)); /* ori a3, a3, low(ram_size) */
2802bfe3
TS		 561
562 /* Load BAR registers as done by YAMON */
a0a8793e
TS		 563 stl_raw(p++, 0x3c09b400); /* lui t1, 0xb400 */
564
565#ifdef TARGET_WORDS_BIGENDIAN
566 stl_raw(p++, 0x3c08df00); /* lui t0, 0xdf00 */
567#else
568 stl_raw(p++, 0x340800df); /* ori t0, r0, 0x00df */
569#endif
570 stl_raw(p++, 0xad280068); /* sw t0, 0x0068(t1) */
571
2802bfe3
TS		 572 stl_raw(p++, 0x3c09bbe0); /* lui t1, 0xbbe0 */
573
574#ifdef TARGET_WORDS_BIGENDIAN
575 stl_raw(p++, 0x3c08c000); /* lui t0, 0xc000 */
576#else
577 stl_raw(p++, 0x340800c0); /* ori t0, r0, 0x00c0 */
578#endif
579 stl_raw(p++, 0xad280048); /* sw t0, 0x0048(t1) */
580#ifdef TARGET_WORDS_BIGENDIAN
581 stl_raw(p++, 0x3c084000); /* lui t0, 0x4000 */
582#else
583 stl_raw(p++, 0x34080040); /* ori t0, r0, 0x0040 */
584#endif
585 stl_raw(p++, 0xad280050); /* sw t0, 0x0050(t1) */
586
587#ifdef TARGET_WORDS_BIGENDIAN
588 stl_raw(p++, 0x3c088000); /* lui t0, 0x8000 */
589#else
590 stl_raw(p++, 0x34080080); /* ori t0, r0, 0x0080 */
591#endif
592 stl_raw(p++, 0xad280058); /* sw t0, 0x0058(t1) */
593#ifdef TARGET_WORDS_BIGENDIAN
594 stl_raw(p++, 0x3c083f00); /* lui t0, 0x3f00 */
595#else
596 stl_raw(p++, 0x3408003f); /* ori t0, r0, 0x003f */
597#endif
598 stl_raw(p++, 0xad280060); /* sw t0, 0x0060(t1) */
599
600#ifdef TARGET_WORDS_BIGENDIAN
601 stl_raw(p++, 0x3c08c100); /* lui t0, 0xc100 */
602#else
603 stl_raw(p++, 0x340800c1); /* ori t0, r0, 0x00c1 */
604#endif
605 stl_raw(p++, 0xad280080); /* sw t0, 0x0080(t1) */
606#ifdef TARGET_WORDS_BIGENDIAN
607 stl_raw(p++, 0x3c085e00); /* lui t0, 0x5e00 */
608#else
609 stl_raw(p++, 0x3408005e); /* ori t0, r0, 0x005e */
610#endif
611 stl_raw(p++, 0xad280088); /* sw t0, 0x0088(t1) */
612
613 /* Jump to kernel code */
74287114
TS		 614 stl_raw(p++, 0x3c1f0000 | ((kernel_entry >> 16) & 0xffff)); /* lui ra, high(kernel_entry) */
615 stl_raw(p++, 0x37ff0000 | (kernel_entry & 0xffff)); /* ori ra, ra, low(kernel_entry) */
3ddd0065
TS		 616 stl_raw(p++, 0x03e00008); /* jr ra */
617 stl_raw(p++, 0x00000000); /* nop */
26ea0918
TS		 618
619 /* YAMON subroutines */
620 p = (uint32_t *) (phys_ram_base + bios_offset + 0x800);
621 stl_raw(p++, 0x03e00008); /* jr ra */
622 stl_raw(p++, 0x24020000); /* li v0,0 */
623 /* 808 YAMON print */
624 stl_raw(p++, 0x03e06821); /* move t5,ra */
625 stl_raw(p++, 0x00805821); /* move t3,a0 */
626 stl_raw(p++, 0x00a05021); /* move t2,a1 */
627 stl_raw(p++, 0x91440000); /* lbu a0,0(t2) */
628 stl_raw(p++, 0x254a0001); /* addiu t2,t2,1 */
629 stl_raw(p++, 0x10800005); /* beqz a0,834 */
630 stl_raw(p++, 0x00000000); /* nop */
631 stl_raw(p++, 0x0ff0021c); /* jal 870 */
632 stl_raw(p++, 0x00000000); /* nop */
633 stl_raw(p++, 0x08000205); /* j 814 */
634 stl_raw(p++, 0x00000000); /* nop */
635 stl_raw(p++, 0x01a00008); /* jr t5 */
636 stl_raw(p++, 0x01602021); /* move a0,t3 */
637 /* 0x83c YAMON print_count */
638 stl_raw(p++, 0x03e06821); /* move t5,ra */
639 stl_raw(p++, 0x00805821); /* move t3,a0 */
640 stl_raw(p++, 0x00a05021); /* move t2,a1 */
641 stl_raw(p++, 0x00c06021); /* move t4,a2 */
642 stl_raw(p++, 0x91440000); /* lbu a0,0(t2) */
643 stl_raw(p++, 0x0ff0021c); /* jal 870 */
644 stl_raw(p++, 0x00000000); /* nop */
645 stl_raw(p++, 0x254a0001); /* addiu t2,t2,1 */
646 stl_raw(p++, 0x258cffff); /* addiu t4,t4,-1 */
647 stl_raw(p++, 0x1580fffa); /* bnez t4,84c */
648 stl_raw(p++, 0x00000000); /* nop */
649 stl_raw(p++, 0x01a00008); /* jr t5 */
650 stl_raw(p++, 0x01602021); /* move a0,t3 */
651 /* 0x870 */
652 stl_raw(p++, 0x3c08b800); /* lui t0,0xb400 */
653 stl_raw(p++, 0x350803f8); /* ori t0,t0,0x3f8 */
654 stl_raw(p++, 0x91090005); /* lbu t1,5(t0) */
655 stl_raw(p++, 0x00000000); /* nop */
656 stl_raw(p++, 0x31290040); /* andi t1,t1,0x40 */
657 stl_raw(p++, 0x1120fffc); /* beqz t1,878 <outch+0x8> */
658 stl_raw(p++, 0x00000000); /* nop */
659 stl_raw(p++, 0x03e00008); /* jr ra */
660 stl_raw(p++, 0xa1040000); /* sb a0,0(t0) */
661
5856de80
TS		 662}
663
664static void prom_set(int index, const char *string, ...)
665{
666 va_list ap;
3ddd0065
TS		 667 int32_t *p;
668 int32_t table_addr;
5856de80
TS		 669 char *s;
670
671 if (index >= ENVP_NB_ENTRIES)
672 return;
673
3ddd0065 674 p = (int32_t *) (phys_ram_base + ENVP_ADDR + VIRT_TO_PHYS_ADDEND);
5856de80
TS		 675 p += index;
676
677 if (string == NULL) {
678 stl_raw(p, 0);
679 return;
680 }
681
3ddd0065 682 table_addr = ENVP_ADDR + sizeof(int32_t) * ENVP_NB_ENTRIES + index * ENVP_ENTRY_SIZE;
5856de80
TS		 683 s = (char *) (phys_ram_base + VIRT_TO_PHYS_ADDEND + table_addr);
684
685 stl_raw(p, table_addr);
686
687 va_start(ap, string);
688 vsnprintf (s, ENVP_ENTRY_SIZE, string, ap);
689 va_end(ap);
690}
691
692/* Kernel */
693static int64_t load_kernel (CPUState *env)
694{
74287114 695 int64_t kernel_entry, kernel_low, kernel_high;
5856de80
TS		 696 int index = 0;
697 long initrd_size;
74287114 698 ram_addr_t initrd_offset;
5856de80 699
7df526e3 700 if (load_elf(loaderparams.kernel_filename, VIRT_TO_PHYS_ADDEND,
b55266b5
BS		 701 (uint64_t *)&kernel_entry, (uint64_t *)&kernel_low,
702 (uint64_t *)&kernel_high) < 0) {
5856de80 703 fprintf(stderr, "qemu: could not load kernel '%s'\n",
7df526e3 704 loaderparams.kernel_filename);
acdf72bb 705 exit(1);
5856de80
TS		 706 }
707
708 /* load initrd */
709 initrd_size = 0;
74287114 710 initrd_offset = 0;
7df526e3
TS		 711 if (loaderparams.initrd_filename) {
712 initrd_size = get_image_size (loaderparams.initrd_filename);
74287114
TS		 713 if (initrd_size > 0) {
714 initrd_offset = (kernel_high + ~TARGET_PAGE_MASK) & TARGET_PAGE_MASK;
7df526e3 715 if (initrd_offset + initrd_size > ram_size) {
74287114
TS		 716 fprintf(stderr,
717 "qemu: memory too small for initial ram disk '%s'\n",
7df526e3 718 loaderparams.initrd_filename);
74287114
TS		 719 exit(1);
720 }
7df526e3 721 initrd_size = load_image(loaderparams.initrd_filename,
74287114
TS		 722 phys_ram_base + initrd_offset);
723 }
5856de80
TS		 724 if (initrd_size == (target_ulong) -1) {
725 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
7df526e3 726 loaderparams.initrd_filename);
5856de80
TS		 727 exit(1);
728 }
729 }
730
731 /* Store command line. */
7df526e3 732 prom_set(index++, loaderparams.kernel_filename);
5856de80 733 if (initrd_size > 0)
74287114
TS		 734 prom_set(index++, "rd_start=0x" TARGET_FMT_lx " rd_size=%li %s",
735 PHYS_TO_VIRT(initrd_offset), initrd_size,
7df526e3 736 loaderparams.kernel_cmdline);
5856de80 737 else
7df526e3 738 prom_set(index++, loaderparams.kernel_cmdline);
5856de80
TS		 739
740 /* Setup minimum environment variables */
741 prom_set(index++, "memsize");
7df526e3 742 prom_set(index++, "%i", loaderparams.ram_size);
5856de80
TS		 743 prom_set(index++, "modetty0");
744 prom_set(index++, "38400n8r");
745 prom_set(index++, NULL);
746
74287114 747 return kernel_entry;
5856de80
TS		 748}
749
750static void main_cpu_reset(void *opaque)
751{
752 CPUState *env = opaque;
753 cpu_reset(env);
754
755 /* The bootload does not need to be rewritten as it is located in a
756 read only location. The kernel location and the arguments table
757 location does not change. */
7df526e3 758 if (loaderparams.kernel_filename) {
fb82fea0 759 env->CP0_Status &= ~((1 << CP0St_BEV) | (1 << CP0St_ERL));
5856de80 760 load_kernel (env);
fb82fea0 761 }
5856de80
TS		 762}
763
70705261 764static
00f82b8a 765void mips_malta_init (ram_addr_t ram_size, int vga_ram_size,
3023f332 766 const char *boot_device,
5856de80 767 const char *kernel_filename, const char *kernel_cmdline,
94fc95cd 768 const char *initrd_filename, const char *cpu_model)
5856de80
TS		 769{
770 char buf[1024];
771 unsigned long bios_offset;
c8b153d7 772 target_long bios_size;
74287114 773 int64_t kernel_entry;
5856de80
TS		 774 PCIBus *pci_bus;
775 CPUState *env;
776 RTCState *rtc_state;
ded7ba9c 777 fdctrl_t *floppy_controller;
5856de80 778 MaltaFPGAState *malta_fpga;
d537cf6c 779 qemu_irq *i8259;
7b717336
TS		 780 int piix4_devfn;
781 uint8_t *eeprom_buf;
782 i2c_bus *smbus;
783 int i;
e4bcb14c
TS		 784 int index;
785 BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
786 BlockDriverState *fd[MAX_FD];
c8b153d7
TS		 787 int fl_idx = 0;
788 int fl_sectors = 0;
5856de80 789
33d68b5f
TS		 790 /* init CPUs */
791 if (cpu_model == NULL) {
60aa19ab 792#ifdef TARGET_MIPS64
c9c1a064 793 cpu_model = "20Kc";
33d68b5f 794#else
1c32f43e 795 cpu_model = "24Kf";
33d68b5f
TS		 796#endif
797 }
aaed909a
FB		 798 env = cpu_init(cpu_model);
799 if (!env) {
800 fprintf(stderr, "Unable to find CPU definition\n");
801 exit(1);
802 }
5856de80
TS		 803 qemu_register_reset(main_cpu_reset, env);
804
805 /* allocate RAM */
806 cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
807
c8b153d7 808 /* Map the bios at two physical locations, as on the real board. */
5856de80
TS		 809 bios_offset = ram_size + vga_ram_size;
810 cpu_register_physical_memory(0x1e000000LL,
811 BIOS_SIZE, bios_offset | IO_MEM_ROM);
812 cpu_register_physical_memory(0x1fc00000LL,
813 BIOS_SIZE, bios_offset | IO_MEM_ROM);
814
070ce5ed
TS		 815 /* FPGA */
816 malta_fpga = malta_fpga_init(0x1f000000LL, env);
817
c8b153d7
TS		 818 /* Load firmware in flash / BIOS unless we boot directly into a kernel. */
819 if (kernel_filename) {
820 /* Write a small bootloader to the flash location. */
821 loaderparams.ram_size = ram_size;
822 loaderparams.kernel_filename = kernel_filename;
823 loaderparams.kernel_cmdline = kernel_cmdline;
824 loaderparams.initrd_filename = initrd_filename;
825 kernel_entry = load_kernel(env);
826 env->CP0_Status &= ~((1 << CP0St_BEV) | (1 << CP0St_ERL));
827 write_bootloader(env, bios_offset, kernel_entry);
828 } else {
829 index = drive_get_index(IF_PFLASH, 0, fl_idx);
830 if (index != -1) {
831 /* Load firmware from flash. */
832 bios_size = 0x400000;
833 fl_sectors = bios_size >> 16;
834#ifdef DEBUG_BOARD_INIT
835 printf("Register parallel flash %d size " TARGET_FMT_lx " at "
836 "offset %08lx addr %08llx '%s' %x\n",
837 fl_idx, bios_size, bios_offset, 0x1e000000LL,
838 bdrv_get_device_name(drives_table[index].bdrv), fl_sectors);
839#endif
840 pflash_cfi01_register(0x1e000000LL, bios_offset,
841 drives_table[index].bdrv, 65536, fl_sectors,
842 4, 0x0000, 0x0000, 0x0000, 0x0000);
843 fl_idx++;
844 } else {
845 /* Load a BIOS image. */
846 if (bios_name == NULL)
847 bios_name = BIOS_FILENAME;
848 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
849 bios_size = load_image(buf, phys_ram_base + bios_offset);
850 if ((bios_size < 0 || bios_size > BIOS_SIZE) && !kernel_filename) {
851 fprintf(stderr,
852 "qemu: Could not load MIPS bios '%s', and no -kernel argument was specified\n",
853 buf);
854 exit(1);
855 }
070ce5ed 856 }
3187ef03
TS		 857 /* In little endian mode the 32bit words in the bios are swapped,
858 a neat trick which allows bi-endian firmware. */
859#ifndef TARGET_WORDS_BIGENDIAN
860 {
861 uint32_t *addr;
862 for (addr = (uint32_t *)(phys_ram_base + bios_offset);
c8b153d7
TS		 863 addr < (uint32_t *)(phys_ram_base + bios_offset + bios_size);
864 addr++) {
3187ef03
TS		 865 *addr = bswap32(*addr);
866 }
867 }
868#endif
070ce5ed
TS		 869 }
870
5856de80
TS		 871 /* Board ID = 0x420 (Malta Board with CoreLV)
872 XXX: theoretically 0x1e000010 should map to flash and 0x1fc00010 should
873 map to the board ID. */
874 stl_raw(phys_ram_base + bios_offset + 0x10, 0x00000420);
875
876 /* Init internal devices */
d537cf6c 877 cpu_mips_irq_init_cpu(env);
5856de80 878 cpu_mips_clock_init(env);
5856de80 879
5856de80 880 /* Interrupt controller */
d537cf6c
PB		 881 /* The 8259 is attached to the MIPS CPU INT0 pin, ie interrupt 2 */
882 i8259 = i8259_init(env->irq[2]);
5856de80
TS		 883
884 /* Northbridge */
d537cf6c 885 pci_bus = pci_gt64120_init(i8259);
5856de80
TS		 886
887 /* Southbridge */
e4bcb14c
TS		 888
889 if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
890 fprintf(stderr, "qemu: too many IDE bus\n");
891 exit(1);
892 }
893
894 for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
895 index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
896 if (index != -1)
897 hd[i] = drives_table[index].bdrv;
898 else
899 hd[i] = NULL;
900 }
901
7b717336 902 piix4_devfn = piix4_init(pci_bus, 80);
e4bcb14c 903 pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1, i8259);
afcc3cdf 904 usb_uhci_piix4_init(pci_bus, piix4_devfn + 2);
cf7a2fe2 905 smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100, i8259[9]);
7b717336
TS		 906 eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */
907 for (i = 0; i < 8; i++) {
908 /* TODO: Populate SPD eeprom data. */
909 smbus_eeprom_device_init(smbus, 0x50 + i, eeprom_buf + (i * 256));
910 }
d537cf6c 911 pit = pit_init(0x40, i8259[0]);
5856de80
TS		 912 DMA_init(0);
913
914 /* Super I/O */
d537cf6c
PB		 915 i8042_init(i8259[1], i8259[12], 0x60);
916 rtc_state = rtc_init(0x70, i8259[8]);
7bcc17dc 917 if (serial_hds[0])
b6cd0ea1 918 serial_init(0x3f8, i8259[4], 115200, serial_hds[0]);
7bcc17dc 919 if (serial_hds[1])
b6cd0ea1 920 serial_init(0x2f8, i8259[3], 115200, serial_hds[1]);
7bcc17dc 921 if (parallel_hds[0])
d537cf6c 922 parallel_init(0x378, i8259[7], parallel_hds[0]);
e4bcb14c
TS		 923 for(i = 0; i < MAX_FD; i++) {
924 index = drive_get_index(IF_FLOPPY, 0, i);
925 if (index != -1)
926 fd[i] = drives_table[index].bdrv;
927 else
928 fd[i] = NULL;
929 }
930 floppy_controller = fdctrl_init(i8259[6], 2, 0, 0x3f0, fd);
5856de80
TS		 931
932 /* Sound card */
933#ifdef HAS_AUDIO
934 audio_init(pci_bus);
935#endif
936
937 /* Network card */
938 network_init(pci_bus);
11f29511
TS		 939
940 /* Optional PCI video card */
3023f332 941 pci_cirrus_vga_init(pci_bus, phys_ram_base + ram_size,
11f29511 942 ram_size, vga_ram_size);
5856de80
TS		 943}
944
945QEMUMachine mips_malta_machine = {
eec2743e
TS		 946 .name = "malta",
947 .desc = "MIPS Malta Core LV",
948 .init = mips_malta_init,
949 .ram_require = VGA_RAM_SIZE + BIOS_SIZE,
950 .nodisk_ok = 1,
5856de80 951};
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