[qemu.git] / hw / sun4u.c

/*
 * QEMU Sun4u System Emulator
 *
 * Copyright (c) 2005 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "hw.h"
#include "pci.h"
#include "pc.h"
#include "nvram.h"
#include "fdc.h"
#include "net.h"
#include "qemu-timer.h"
#include "sysemu.h"
#include "boards.h"
#include "firmware_abi.h"

#define KERNEL_LOAD_ADDR     0x00404000
#define CMDLINE_ADDR         0x003ff000
#define INITRD_LOAD_ADDR     0x00300000
#define PROM_SIZE_MAX        (4 * 1024 * 1024)
#define PROM_ADDR            0x1fff0000000ULL
#define PROM_VADDR           0x000ffd00000ULL
#define APB_SPECIAL_BASE     0x1fe00000000ULL
#define APB_MEM_BASE         0x1ff00000000ULL
#define VGA_BASE             (APB_MEM_BASE + 0x400000ULL)
#define PROM_FILENAME        "openbios-sparc64"
#define NVRAM_SIZE           0x2000
#define MAX_IDE_BUS          2

int DMA_get_channel_mode (int nchan)
{
    return 0;
}
int DMA_read_memory (int nchan, void *buf, int pos, int size)
{
    return 0;
}
int DMA_write_memory (int nchan, void *buf, int pos, int size)
{
    return 0;
}
void DMA_hold_DREQ (int nchan) {}
void DMA_release_DREQ (int nchan) {}
void DMA_schedule(int nchan) {}
void DMA_run (void) {}
void DMA_init (int high_page_enable) {}
void DMA_register_channel (int nchan,
                           DMA_transfer_handler transfer_handler,
                           void *opaque)
{
}

static int nvram_boot_set(void *opaque, const char *boot_device)
{
    unsigned int i;
    uint8_t image[sizeof(ohwcfg_v3_t)];
    ohwcfg_v3_t *header = (ohwcfg_v3_t *)&image;
    m48t59_t *nvram = (m48t59_t *)opaque;

    for (i = 0; i < sizeof(image); i++)
        image[i] = m48t59_read(nvram, i) & 0xff;

    strcpy((char *)header->boot_devices, boot_device);
    header->nboot_devices = strlen(boot_device) & 0xff;
    header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));

    for (i = 0; i < sizeof(image); i++)
        m48t59_write(nvram, i, image[i]);

    return 0;
}

extern int nographic;

static int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
                                   const char *arch,
                                   ram_addr_t RAM_size,
                                   const char *boot_devices,
                                   uint32_t kernel_image, uint32_t kernel_size,
                                   const char *cmdline,
                                   uint32_t initrd_image, uint32_t initrd_size,
                                   uint32_t NVRAM_image,
                                   int width, int height, int depth)
{
    unsigned int i;
    uint32_t start, end;
    uint8_t image[0x1ff0];
    ohwcfg_v3_t *header = (ohwcfg_v3_t *)&image;
    struct sparc_arch_cfg *sparc_header;
    struct OpenBIOS_nvpart_v1 *part_header;

    memset(image, '\0', sizeof(image));

    // Try to match PPC NVRAM
    strcpy((char *)header->struct_ident, "QEMU_BIOS");
    header->struct_version = cpu_to_be32(3); /* structure v3 */

    header->nvram_size = cpu_to_be16(NVRAM_size);
    header->nvram_arch_ptr = cpu_to_be16(sizeof(ohwcfg_v3_t));
    header->nvram_arch_size = cpu_to_be16(sizeof(struct sparc_arch_cfg));
    strcpy((char *)header->arch, arch);
    header->nb_cpus = smp_cpus & 0xff;
    header->RAM0_base = 0;
    header->RAM0_size = cpu_to_be64((uint64_t)RAM_size);
    strcpy((char *)header->boot_devices, boot_devices);
    header->nboot_devices = strlen(boot_devices) & 0xff;
    header->kernel_image = cpu_to_be64((uint64_t)kernel_image);
    header->kernel_size = cpu_to_be64((uint64_t)kernel_size);
    if (cmdline) {
        pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, cmdline);
        header->cmdline = cpu_to_be64((uint64_t)CMDLINE_ADDR);
        header->cmdline_size = cpu_to_be64((uint64_t)strlen(cmdline));
    }
    header->initrd_image = cpu_to_be64((uint64_t)initrd_image);
    header->initrd_size = cpu_to_be64((uint64_t)initrd_size);
    header->NVRAM_image = cpu_to_be64((uint64_t)NVRAM_image);

    header->width = cpu_to_be16(width);
    header->height = cpu_to_be16(height);
    header->depth = cpu_to_be16(depth);
    if (nographic)
        header->graphic_flags = cpu_to_be16(OHW_GF_NOGRAPHICS);

    header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));

    // Architecture specific header
    start = sizeof(ohwcfg_v3_t);
    sparc_header = (struct sparc_arch_cfg *)&image[start];
    sparc_header->valid = 0;
    start += sizeof(struct sparc_arch_cfg);

    // OpenBIOS nvram variables
    // Variable partition
    part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
    part_header->signature = OPENBIOS_PART_SYSTEM;
    strcpy(part_header->name, "system");

    end = start + sizeof(struct OpenBIOS_nvpart_v1);
    for (i = 0; i < nb_prom_envs; i++)
        end = OpenBIOS_set_var(image, end, prom_envs[i]);

    // End marker
    image[end++] = '\0';

    end = start + ((end - start + 15) & ~15);
    OpenBIOS_finish_partition(part_header, end - start);

    // free partition
    start = end;
    part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
    part_header->signature = OPENBIOS_PART_FREE;
    strcpy(part_header->name, "free");

    end = 0x1fd0;
    OpenBIOS_finish_partition(part_header, end - start);

    for (i = 0; i < sizeof(image); i++)
        m48t59_write(nvram, i, image[i]);

    qemu_register_boot_set(nvram_boot_set, nvram);

    return 0;
}

void pic_info(void)
{
}

void irq_info(void)
{
}

void qemu_system_powerdown(void)
{
}

static void main_cpu_reset(void *opaque)
{
    CPUState *env = opaque;

    cpu_reset(env);
    ptimer_set_limit(env->tick, 0x7fffffffffffffffULL, 1);
    ptimer_run(env->tick, 0);
    ptimer_set_limit(env->stick, 0x7fffffffffffffffULL, 1);
    ptimer_run(env->stick, 0);
    ptimer_set_limit(env->hstick, 0x7fffffffffffffffULL, 1);
    ptimer_run(env->hstick, 0);
}

static void tick_irq(void *opaque)
{
    CPUState *env = opaque;

    cpu_interrupt(env, CPU_INTERRUPT_TIMER);
}

static void stick_irq(void *opaque)
{
    CPUState *env = opaque;

    cpu_interrupt(env, CPU_INTERRUPT_TIMER);
}

static void hstick_irq(void *opaque)
{
    CPUState *env = opaque;

    cpu_interrupt(env, CPU_INTERRUPT_TIMER);
}

static void dummy_cpu_set_irq(void *opaque, int irq, int level)
{
}

static const int ide_iobase[2] = { 0x1f0, 0x170 };
static const int ide_iobase2[2] = { 0x3f6, 0x376 };
static const int ide_irq[2] = { 14, 15 };

static const int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
static const int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };

static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };

static fdctrl_t *floppy_controller;

/* Sun4u hardware initialisation */
static void sun4u_init(ram_addr_t RAM_size, int vga_ram_size,
                       const char *boot_devices, DisplayState *ds,
                       const char *kernel_filename, const char *kernel_cmdline,
                       const char *initrd_filename, const char *cpu_model)
{
    CPUState *env;
    char buf[1024];
    m48t59_t *nvram;
    int ret, linux_boot;
    unsigned int i;
    long prom_offset, initrd_size, kernel_size;
    PCIBus *pci_bus;
    QEMUBH *bh;
    qemu_irq *irq;
    int drive_index;
    BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
    BlockDriverState *fd[MAX_FD];

    linux_boot = (kernel_filename != NULL);

    /* init CPUs */
    if (cpu_model == NULL)
        cpu_model = "TI UltraSparc II";
    env = cpu_init(cpu_model);
    if (!env) {
        fprintf(stderr, "Unable to find Sparc CPU definition\n");
        exit(1);
    }
    bh = qemu_bh_new(tick_irq, env);
    env->tick = ptimer_init(bh);
    ptimer_set_period(env->tick, 1ULL);

    bh = qemu_bh_new(stick_irq, env);
    env->stick = ptimer_init(bh);
    ptimer_set_period(env->stick, 1ULL);

    bh = qemu_bh_new(hstick_irq, env);
    env->hstick = ptimer_init(bh);
    ptimer_set_period(env->hstick, 1ULL);
    register_savevm("cpu", 0, 4, cpu_save, cpu_load, env);
    qemu_register_reset(main_cpu_reset, env);
    main_cpu_reset(env);

    /* allocate RAM */
    cpu_register_physical_memory(0, RAM_size, 0);

    prom_offset = RAM_size + vga_ram_size;
    cpu_register_physical_memory(PROM_ADDR,
                                 (PROM_SIZE_MAX + TARGET_PAGE_SIZE) &
                                 TARGET_PAGE_MASK,
                                 prom_offset | IO_MEM_ROM);

    if (bios_name == NULL)
        bios_name = PROM_FILENAME;
    snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
    ret = load_elf(buf, PROM_ADDR - PROM_VADDR, NULL, NULL, NULL);
    if (ret < 0) {
        fprintf(stderr, "qemu: could not load prom '%s'\n",
                buf);
        exit(1);
    }

    kernel_size = 0;
    initrd_size = 0;
    if (linux_boot) {
        /* XXX: put correct offset */
        kernel_size = load_elf(kernel_filename, 0, NULL, NULL, NULL);
        if (kernel_size < 0)
            kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
                                    ram_size - KERNEL_LOAD_ADDR);
        if (kernel_size < 0)
            kernel_size = load_image_targphys(kernel_filename,
                                              KERNEL_LOAD_ADDR,
                                              ram_size - KERNEL_LOAD_ADDR);
        if (kernel_size < 0) {
            fprintf(stderr, "qemu: could not load kernel '%s'\n",
                    kernel_filename);
            exit(1);
        }

        /* load initrd */
        if (initrd_filename) {
            initrd_size = load_image_targphys(initrd_filename,
                                              INITRD_LOAD_ADDR,
                                              ram_size - INITRD_LOAD_ADDR);
            if (initrd_size < 0) {
                fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
                        initrd_filename);
                exit(1);
            }
        }
        if (initrd_size > 0) {
            for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
                if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS
                    stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
                    stl_phys(KERNEL_LOAD_ADDR + i + 20, initrd_size);
                    break;
                }
            }
        }
    }
    pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, NULL);
    isa_mem_base = VGA_BASE;
    pci_cirrus_vga_init(pci_bus, ds, phys_ram_base + RAM_size, RAM_size,
                        vga_ram_size);

    for(i = 0; i < MAX_SERIAL_PORTS; i++) {
        if (serial_hds[i]) {
            serial_init(serial_io[i], NULL/*serial_irq[i]*/, 115200,
                        serial_hds[i]);
        }
    }

    for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
        if (parallel_hds[i]) {
            parallel_init(parallel_io[i], NULL/*parallel_irq[i]*/,
                          parallel_hds[i]);
        }
    }

    for(i = 0; i < nb_nics; i++) {
        if (!nd_table[i].model)
            nd_table[i].model = "ne2k_pci";
        pci_nic_init(pci_bus, &nd_table[i], -1);
    }

    irq = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, 32);
    if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
        fprintf(stderr, "qemu: too many IDE bus\n");
        exit(1);
    }
    for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
        drive_index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS,
                                      i % MAX_IDE_DEVS);
       if (drive_index != -1)
           hd[i] = drives_table[drive_index].bdrv;
       else
           hd[i] = NULL;
    }

    // XXX pci_cmd646_ide_init(pci_bus, hd, 1);
    pci_piix3_ide_init(pci_bus, hd, -1, irq);
    /* FIXME: wire up interrupts.  */
    i8042_init(NULL/*1*/, NULL/*12*/, 0x60);
    for(i = 0; i < MAX_FD; i++) {
        drive_index = drive_get_index(IF_FLOPPY, 0, i);
       if (drive_index != -1)
           fd[i] = drives_table[drive_index].bdrv;
       else
           fd[i] = NULL;
    }
    floppy_controller = fdctrl_init(NULL/*6*/, 2, 0, 0x3f0, fd);
    nvram = m48t59_init(NULL/*8*/, 0, 0x0074, NVRAM_SIZE, 59);
    sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", RAM_size, boot_devices,
                         KERNEL_LOAD_ADDR, kernel_size,
                         kernel_cmdline,
                         INITRD_LOAD_ADDR, initrd_size,
                         /* XXX: need an option to load a NVRAM image */
                         0,
                         graphic_width, graphic_height, graphic_depth);

}

QEMUMachine sun4u_machine = {
    "sun4u",
    "Sun4u platform",
    sun4u_init,
    PROM_SIZE_MAX + VGA_RAM_SIZE,
};
Commit	Line	Data
3475187d FB	1	/*
3475187d FB	2	* QEMU Sun4u System Emulator
5fafdf24	3	*
3475187d	4	* Copyright (c) 2005 Fabrice Bellard
5fafdf24	5	*
3475187d FB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
87ecb68b PB	24	#include "hw.h"
	25	#include "pci.h"
	26	#include "pc.h"
	27	#include "nvram.h"
	28	#include "fdc.h"
	29	#include "net.h"
	30	#include "qemu-timer.h"
	31	#include "sysemu.h"
	32	#include "boards.h"
d2c63fc1	33	#include "firmware_abi.h"
3475187d	34
83469015 FB	35	#define KERNEL_LOAD_ADDR 0x00404000
	36	#define CMDLINE_ADDR 0x003ff000
	37	#define INITRD_LOAD_ADDR 0x00300000
ac2e9d66	38	#define PROM_SIZE_MAX (4 * 1024 * 1024)
f930d07e BS	39	#define PROM_ADDR 0x1fff0000000ULL
f930d07e BS	40	#define PROM_VADDR 0x000ffd00000ULL
83469015	41	#define APB_SPECIAL_BASE 0x1fe00000000ULL
f930d07e BS	42	#define APB_MEM_BASE 0x1ff00000000ULL
	43	#define VGA_BASE (APB_MEM_BASE + 0x400000ULL)
	44	#define PROM_FILENAME "openbios-sparc64"
83469015	45	#define NVRAM_SIZE 0x2000
e4bcb14c	46	#define MAX_IDE_BUS 2
3475187d	47
3475187d FB	48	int DMA_get_channel_mode (int nchan)
	49	{
	50	return 0;
	51	}
	52	int DMA_read_memory (int nchan, void *buf, int pos, int size)
	53	{
	54	return 0;
	55	}
	56	int DMA_write_memory (int nchan, void *buf, int pos, int size)
	57	{
	58	return 0;
	59	}
	60	void DMA_hold_DREQ (int nchan) {}
	61	void DMA_release_DREQ (int nchan) {}
	62	void DMA_schedule(int nchan) {}
	63	void DMA_run (void) {}
	64	void DMA_init (int high_page_enable) {}
	65	void DMA_register_channel (int nchan,
	66	DMA_transfer_handler transfer_handler,
	67	void *opaque)
	68	{
	69	}
	70
81864572 BS	71	static int nvram_boot_set(void opaque, const char boot_device)
	72	{
	73	unsigned int i;
	74	uint8_t image[sizeof(ohwcfg_v3_t)];
	75	ohwcfg_v3_t header = (ohwcfg_v3_t )&image;
	76	m48t59_t nvram = (m48t59_t )opaque;
	77
	78	for (i = 0; i < sizeof(image); i++)
	79	image[i] = m48t59_read(nvram, i) & 0xff;
	80
e7fb1406	81	strcpy((char *)header->boot_devices, boot_device);
81864572 BS	82	header->nboot_devices = strlen(boot_device) & 0xff;
	83	header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
	84
	85	for (i = 0; i < sizeof(image); i++)
	86	m48t59_write(nvram, i, image[i]);
	87
	88	return 0;
	89	}
	90
3475187d FB	91	extern int nographic;
3475187d FB	92
d2c63fc1	93	static int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
e7fb1406	94	const char *arch,
77f193da BS	95	ram_addr_t RAM_size,
77f193da BS	96	const char *boot_devices,
d2c63fc1 BS	97	uint32_t kernel_image, uint32_t kernel_size,
	98	const char *cmdline,
	99	uint32_t initrd_image, uint32_t initrd_size,
	100	uint32_t NVRAM_image,
	101	int width, int height, int depth)
83469015	102	{
66508601 BS	103	unsigned int i;
66508601 BS	104	uint32_t start, end;
d2c63fc1 BS	105	uint8_t image[0x1ff0];
	106	ohwcfg_v3_t header = (ohwcfg_v3_t )&image;
	107	struct sparc_arch_cfg *sparc_header;
	108	struct OpenBIOS_nvpart_v1 *part_header;
	109
	110	memset(image, '\0', sizeof(image));
	111
	112	// Try to match PPC NVRAM
e7fb1406	113	strcpy((char *)header->struct_ident, "QEMU_BIOS");
d2c63fc1 BS	114	header->struct_version = cpu_to_be32(3); /* structure v3 */
	115
	116	header->nvram_size = cpu_to_be16(NVRAM_size);
	117	header->nvram_arch_ptr = cpu_to_be16(sizeof(ohwcfg_v3_t));
	118	header->nvram_arch_size = cpu_to_be16(sizeof(struct sparc_arch_cfg));
e7fb1406	119	strcpy((char *)header->arch, arch);
d2c63fc1 BS	120	header->nb_cpus = smp_cpus & 0xff;
	121	header->RAM0_base = 0;
	122	header->RAM0_size = cpu_to_be64((uint64_t)RAM_size);
e7fb1406	123	strcpy((char *)header->boot_devices, boot_devices);
d2c63fc1 BS	124	header->nboot_devices = strlen(boot_devices) & 0xff;
	125	header->kernel_image = cpu_to_be64((uint64_t)kernel_image);
	126	header->kernel_size = cpu_to_be64((uint64_t)kernel_size);
3475187d	127	if (cmdline) {
293f78bc	128	pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, cmdline);
d2c63fc1 BS	129	header->cmdline = cpu_to_be64((uint64_t)CMDLINE_ADDR);
d2c63fc1 BS	130	header->cmdline_size = cpu_to_be64((uint64_t)strlen(cmdline));
3475187d	131	}
d2c63fc1 BS	132	header->initrd_image = cpu_to_be64((uint64_t)initrd_image);
	133	header->initrd_size = cpu_to_be64((uint64_t)initrd_size);
	134	header->NVRAM_image = cpu_to_be64((uint64_t)NVRAM_image);
	135
	136	header->width = cpu_to_be16(width);
	137	header->height = cpu_to_be16(height);
	138	header->depth = cpu_to_be16(depth);
	139	if (nographic)
	140	header->graphic_flags = cpu_to_be16(OHW_GF_NOGRAPHICS);
83469015	141
d2c63fc1 BS	142	header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
	143
	144	// Architecture specific header
	145	start = sizeof(ohwcfg_v3_t);
	146	sparc_header = (struct sparc_arch_cfg *)&image[start];
	147	sparc_header->valid = 0;
	148	start += sizeof(struct sparc_arch_cfg);
83469015	149
66508601 BS	150	// OpenBIOS nvram variables
66508601 BS	151	// Variable partition
d2c63fc1 BS	152	part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
	153	part_header->signature = OPENBIOS_PART_SYSTEM;
	154	strcpy(part_header->name, "system");
66508601	155
d2c63fc1	156	end = start + sizeof(struct OpenBIOS_nvpart_v1);
66508601	157	for (i = 0; i < nb_prom_envs; i++)
d2c63fc1 BS	158	end = OpenBIOS_set_var(image, end, prom_envs[i]);
	159
	160	// End marker
	161	image[end++] = '\0';
66508601	162
66508601	163	end = start + ((end - start + 15) & ~15);
d2c63fc1	164	OpenBIOS_finish_partition(part_header, end - start);
66508601 BS	165
	166	// free partition
	167	start = end;
d2c63fc1 BS	168	part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
	169	part_header->signature = OPENBIOS_PART_FREE;
	170	strcpy(part_header->name, "free");
66508601 BS	171
66508601 BS	172	end = 0x1fd0;
d2c63fc1 BS	173	OpenBIOS_finish_partition(part_header, end - start);
	174
	175	for (i = 0; i < sizeof(image); i++)
	176	m48t59_write(nvram, i, image[i]);
66508601	177
81864572 BS	178	qemu_register_boot_set(nvram_boot_set, nvram);
81864572 BS	179
83469015	180	return 0;
3475187d FB	181	}
3475187d FB	182
22548760	183	void pic_info(void)
3475187d FB	184	{
	185	}
	186
22548760	187	void irq_info(void)
3475187d FB	188	{
	189	}
	190
83469015	191	void qemu_system_powerdown(void)
3475187d FB	192	{
	193	}
	194
c68ea704 FB	195	static void main_cpu_reset(void *opaque)
	196	{
	197	CPUState *env = opaque;
20c9f095	198
c68ea704	199	cpu_reset(env);
20c9f095 BS	200	ptimer_set_limit(env->tick, 0x7fffffffffffffffULL, 1);
	201	ptimer_run(env->tick, 0);
	202	ptimer_set_limit(env->stick, 0x7fffffffffffffffULL, 1);
	203	ptimer_run(env->stick, 0);
	204	ptimer_set_limit(env->hstick, 0x7fffffffffffffffULL, 1);
	205	ptimer_run(env->hstick, 0);
	206	}
	207
22548760	208	static void tick_irq(void *opaque)
20c9f095 BS	209	{
	210	CPUState *env = opaque;
	211
	212	cpu_interrupt(env, CPU_INTERRUPT_TIMER);
	213	}
	214
22548760	215	static void stick_irq(void *opaque)
20c9f095 BS	216	{
	217	CPUState *env = opaque;
	218
	219	cpu_interrupt(env, CPU_INTERRUPT_TIMER);
	220	}
	221
22548760	222	static void hstick_irq(void *opaque)
20c9f095 BS	223	{
	224	CPUState *env = opaque;
	225
	226	cpu_interrupt(env, CPU_INTERRUPT_TIMER);
c68ea704 FB	227	}
c68ea704 FB	228
f19e918d BS	229	static void dummy_cpu_set_irq(void *opaque, int irq, int level)
	230	{
	231	}
	232
83469015 FB	233	static const int ide_iobase[2] = { 0x1f0, 0x170 };
	234	static const int ide_iobase2[2] = { 0x3f6, 0x376 };
	235	static const int ide_irq[2] = { 14, 15 };
3475187d	236
83469015 FB	237	static const int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
	238	static const int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
	239
	240	static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
	241	static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
	242
	243	static fdctrl_t *floppy_controller;
3475187d FB	244
3475187d FB	245	/* Sun4u hardware initialisation */
22548760	246	static void sun4u_init(ram_addr_t RAM_size, int vga_ram_size,
b881c2c6 BS	247	const char boot_devices, DisplayState ds,
	248	const char kernel_filename, const char kernel_cmdline,
	249	const char initrd_filename, const char cpu_model)
3475187d	250	{
c68ea704	251	CPUState *env;
3475187d	252	char buf[1024];
83469015	253	m48t59_t *nvram;
3475187d FB	254	int ret, linux_boot;
3475187d FB	255	unsigned int i;
83469015 FB	256	long prom_offset, initrd_size, kernel_size;
83469015 FB	257	PCIBus *pci_bus;
20c9f095	258	QEMUBH *bh;
f19e918d	259	qemu_irq *irq;
22548760	260	int drive_index;
e4bcb14c TS	261	BlockDriverState hd[MAX_IDE_BUS MAX_IDE_DEVS];
e4bcb14c TS	262	BlockDriverState *fd[MAX_FD];
3475187d FB	263
	264	linux_boot = (kernel_filename != NULL);
	265
62724a37 BS	266	/* init CPUs */
	267	if (cpu_model == NULL)
	268	cpu_model = "TI UltraSparc II";
aaed909a FB	269	env = cpu_init(cpu_model);
aaed909a FB	270	if (!env) {
62724a37 BS	271	fprintf(stderr, "Unable to find Sparc CPU definition\n");
	272	exit(1);
	273	}
20c9f095 BS	274	bh = qemu_bh_new(tick_irq, env);
	275	env->tick = ptimer_init(bh);
	276	ptimer_set_period(env->tick, 1ULL);
	277
	278	bh = qemu_bh_new(stick_irq, env);
	279	env->stick = ptimer_init(bh);
	280	ptimer_set_period(env->stick, 1ULL);
	281
	282	bh = qemu_bh_new(hstick_irq, env);
	283	env->hstick = ptimer_init(bh);
	284	ptimer_set_period(env->hstick, 1ULL);
1a14026e	285	register_savevm("cpu", 0, 4, cpu_save, cpu_load, env);
c68ea704	286	qemu_register_reset(main_cpu_reset, env);
20c9f095	287	main_cpu_reset(env);
c68ea704	288
3475187d	289	/* allocate RAM */
22548760	290	cpu_register_physical_memory(0, RAM_size, 0);
3475187d	291
22548760	292	prom_offset = RAM_size + vga_ram_size;
5fafdf24	293	cpu_register_physical_memory(PROM_ADDR,
77f193da BS	294	(PROM_SIZE_MAX + TARGET_PAGE_SIZE) &
77f193da BS	295	TARGET_PAGE_MASK,
b3783731	296	prom_offset \| IO_MEM_ROM);
3475187d	297
1192dad8 JM	298	if (bios_name == NULL)
	299	bios_name = PROM_FILENAME;
	300	snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
f19e918d	301	ret = load_elf(buf, PROM_ADDR - PROM_VADDR, NULL, NULL, NULL);
3475187d	302	if (ret < 0) {
f930d07e BS	303	fprintf(stderr, "qemu: could not load prom '%s'\n",
	304	buf);
	305	exit(1);
3475187d	306	}
3475187d FB	307
3475187d FB	308	kernel_size = 0;
83469015	309	initrd_size = 0;
3475187d	310	if (linux_boot) {
b3783731	311	/* XXX: put correct offset */
74287114	312	kernel_size = load_elf(kernel_filename, 0, NULL, NULL, NULL);
3475187d	313	if (kernel_size < 0)
293f78bc BS	314	kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
293f78bc BS	315	ram_size - KERNEL_LOAD_ADDR);
f930d07e	316	if (kernel_size < 0)
293f78bc BS	317	kernel_size = load_image_targphys(kernel_filename,
	318	KERNEL_LOAD_ADDR,
	319	ram_size - KERNEL_LOAD_ADDR);
3475187d	320	if (kernel_size < 0) {
5fafdf24	321	fprintf(stderr, "qemu: could not load kernel '%s'\n",
3475187d	322	kernel_filename);
f930d07e	323	exit(1);
3475187d FB	324	}
	325
	326	/* load initrd */
3475187d	327	if (initrd_filename) {
293f78bc BS	328	initrd_size = load_image_targphys(initrd_filename,
	329	INITRD_LOAD_ADDR,
	330	ram_size - INITRD_LOAD_ADDR);
3475187d	331	if (initrd_size < 0) {
5fafdf24	332	fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
3475187d FB	333	initrd_filename);
	334	exit(1);
	335	}
	336	}
	337	if (initrd_size > 0) {
f930d07e	338	for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
293f78bc BS	339	if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS
	340	stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
	341	stl_phys(KERNEL_LOAD_ADDR + i + 20, initrd_size);
f930d07e BS	342	break;
	343	}
	344	}
3475187d FB	345	}
3475187d FB	346	}
502a5395	347	pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, NULL);
83469015	348	isa_mem_base = VGA_BASE;
77f193da BS	349	pci_cirrus_vga_init(pci_bus, ds, phys_ram_base + RAM_size, RAM_size,
77f193da BS	350	vga_ram_size);
83469015 FB	351
	352	for(i = 0; i < MAX_SERIAL_PORTS; i++) {
	353	if (serial_hds[i]) {
cbf5c748 BS	354	serial_init(serial_io[i], NULL/serial_irq[i]/, 115200,
cbf5c748 BS	355	serial_hds[i]);
83469015 FB	356	}
	357	}
	358
	359	for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
	360	if (parallel_hds[i]) {
77f193da BS	361	parallel_init(parallel_io[i], NULL/parallel_irq[i]/,
77f193da BS	362	parallel_hds[i]);
83469015 FB	363	}
	364	}
	365
	366	for(i = 0; i < nb_nics; i++) {
a41b2ff2 PB	367	if (!nd_table[i].model)
a41b2ff2 PB	368	nd_table[i].model = "ne2k_pci";
f930d07e	369	pci_nic_init(pci_bus, &nd_table[i], -1);
83469015 FB	370	}
83469015 FB	371
f19e918d	372	irq = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, 32);
e4bcb14c TS	373	if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
	374	fprintf(stderr, "qemu: too many IDE bus\n");
	375	exit(1);
	376	}
	377	for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
22548760 BS	378	drive_index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS,
	379	i % MAX_IDE_DEVS);
	380	if (drive_index != -1)
	381	hd[i] = drives_table[drive_index].bdrv;
e4bcb14c TS	382	else
	383	hd[i] = NULL;
	384	}
	385
	386	// XXX pci_cmd646_ide_init(pci_bus, hd, 1);
	387	pci_piix3_ide_init(pci_bus, hd, -1, irq);
d537cf6c PB	388	/* FIXME: wire up interrupts. */
d537cf6c PB	389	i8042_init(NULL/1/, NULL/12/, 0x60);
e4bcb14c	390	for(i = 0; i < MAX_FD; i++) {
22548760 BS	391	drive_index = drive_get_index(IF_FLOPPY, 0, i);
	392	if (drive_index != -1)
	393	fd[i] = drives_table[drive_index].bdrv;
e4bcb14c TS	394	else
	395	fd[i] = NULL;
	396	}
	397	floppy_controller = fdctrl_init(NULL/6/, 2, 0, 0x3f0, fd);
d537cf6c	398	nvram = m48t59_init(NULL/8/, 0, 0x0074, NVRAM_SIZE, 59);
22548760	399	sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", RAM_size, boot_devices,
83469015 FB	400	KERNEL_LOAD_ADDR, kernel_size,
	401	kernel_cmdline,
	402	INITRD_LOAD_ADDR, initrd_size,
	403	/* XXX: need an option to load a NVRAM image */
	404	0,
	405	graphic_width, graphic_height, graphic_depth);
	406
3475187d FB	407	}
	408
	409	QEMUMachine sun4u_machine = {
	410	"sun4u",
	411	"Sun4u platform",
	412	sun4u_init,
7fb4fdcf	413	PROM_SIZE_MAX + VGA_RAM_SIZE,
3475187d	414	};