[qemu.git] / hw / msix.c

/*
 * MSI-X device support
 *
 * This module includes support for MSI-X in pci devices.
 *
 * Author: Michael S. Tsirkin <[email protected]>
 *
 *  Copyright (c) 2009, Red Hat Inc, Michael S. Tsirkin ([email protected])
 *
 * This work is licensed under the terms of the GNU GPL, version 2.  See
 * the COPYING file in the top-level directory.
 */

#include "hw.h"
#include "msix.h"
#include "pci.h"

/* Declaration from linux/pci_regs.h */
#define  PCI_CAP_ID_MSIX 0x11 /* MSI-X */
#define  PCI_MSIX_FLAGS 2     /* Table at lower 11 bits */
#define  PCI_MSIX_FLAGS_QSIZE	0x7FF
#define  PCI_MSIX_FLAGS_ENABLE	(1 << 15)
#define  PCI_MSIX_FLAGS_MASKALL	(1 << 14)
#define  PCI_MSIX_FLAGS_BIRMASK	(7 << 0)

/* MSI-X capability structure */
#define MSIX_TABLE_OFFSET 4
#define MSIX_PBA_OFFSET 8
#define MSIX_CAP_LENGTH 12

/* MSI enable bit and maskall bit are in byte 1 in FLAGS register */
#define MSIX_CONTROL_OFFSET (PCI_MSIX_FLAGS + 1)
#define MSIX_ENABLE_MASK (PCI_MSIX_FLAGS_ENABLE >> 8)
#define MSIX_MASKALL_MASK (PCI_MSIX_FLAGS_MASKALL >> 8)

/* MSI-X table format */
#define MSIX_MSG_ADDR 0
#define MSIX_MSG_UPPER_ADDR 4
#define MSIX_MSG_DATA 8
#define MSIX_VECTOR_CTRL 12
#define MSIX_ENTRY_SIZE 16
#define MSIX_VECTOR_MASK 0x1

/* How much space does an MSIX table need. */
/* The spec requires giving the table structure
 * a 4K aligned region all by itself. */
#define MSIX_PAGE_SIZE 0x1000
/* Reserve second half of the page for pending bits */
#define MSIX_PAGE_PENDING (MSIX_PAGE_SIZE / 2)
#define MSIX_MAX_ENTRIES 32


#ifdef MSIX_DEBUG
#define DEBUG(fmt, ...)                                       \
    do {                                                      \
      fprintf(stderr, "%s: " fmt, __func__ , __VA_ARGS__);    \
    } while (0)
#else
#define DEBUG(fmt, ...) do { } while(0)
#endif

/* Flag for interrupt controller to declare MSI-X support */
int msix_supported;

/* Add MSI-X capability to the config space for the device. */
/* Given a bar and its size, add MSI-X table on top of it
 * and fill MSI-X capability in the config space.
 * Original bar size must be a power of 2 or 0.
 * New bar size is returned. */
static int msix_add_config(struct PCIDevice *pdev, unsigned short nentries,
                           unsigned bar_nr, unsigned bar_size)
{
    int config_offset;
    uint8_t *config;
    uint32_t new_size;

    if (nentries < 1 || nentries > PCI_MSIX_FLAGS_QSIZE + 1)
        return -EINVAL;
    if (bar_size > 0x80000000)
        return -ENOSPC;

    /* Add space for MSI-X structures */
    if (!bar_size) {
        new_size = MSIX_PAGE_SIZE;
    } else if (bar_size < MSIX_PAGE_SIZE) {
        bar_size = MSIX_PAGE_SIZE;
        new_size = MSIX_PAGE_SIZE * 2;
    } else {
        new_size = bar_size * 2;
    }

    pdev->msix_bar_size = new_size;
    config_offset = pci_add_capability(pdev, PCI_CAP_ID_MSIX, MSIX_CAP_LENGTH);
    if (config_offset < 0)
        return config_offset;
    config = pdev->config + config_offset;

    pci_set_word(config + PCI_MSIX_FLAGS, nentries - 1);
    /* Table on top of BAR */
    pci_set_long(config + MSIX_TABLE_OFFSET, bar_size | bar_nr);
    /* Pending bits on top of that */
    pci_set_long(config + MSIX_PBA_OFFSET, (bar_size + MSIX_PAGE_PENDING) |
                 bar_nr);
    pdev->msix_cap = config_offset;
    /* Make flags bit writeable. */
    pdev->wmask[config_offset + MSIX_CONTROL_OFFSET] |= MSIX_ENABLE_MASK |
	    MSIX_MASKALL_MASK;
    return 0;
}

static uint32_t msix_mmio_readl(void *opaque, target_phys_addr_t addr)
{
    PCIDevice *dev = opaque;
    unsigned int offset = addr & (MSIX_PAGE_SIZE - 1) & ~0x3;
    void *page = dev->msix_table_page;

    return pci_get_long(page + offset);
}

static uint32_t msix_mmio_read_unallowed(void *opaque, target_phys_addr_t addr)
{
    fprintf(stderr, "MSI-X: only dword read is allowed!\n");
    return 0;
}

static uint8_t msix_pending_mask(int vector)
{
    return 1 << (vector % 8);
}

static uint8_t *msix_pending_byte(PCIDevice *dev, int vector)
{
    return dev->msix_table_page + MSIX_PAGE_PENDING + vector / 8;
}

static int msix_is_pending(PCIDevice *dev, int vector)
{
    return *msix_pending_byte(dev, vector) & msix_pending_mask(vector);
}

static void msix_set_pending(PCIDevice *dev, int vector)
{
    *msix_pending_byte(dev, vector) |= msix_pending_mask(vector);
}

static void msix_clr_pending(PCIDevice *dev, int vector)
{
    *msix_pending_byte(dev, vector) &= ~msix_pending_mask(vector);
}

static int msix_function_masked(PCIDevice *dev)
{
    return dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] & MSIX_MASKALL_MASK;
}

static int msix_is_masked(PCIDevice *dev, int vector)
{
    unsigned offset = vector * MSIX_ENTRY_SIZE + MSIX_VECTOR_CTRL;
    return msix_function_masked(dev) ||
	   dev->msix_table_page[offset] & MSIX_VECTOR_MASK;
}

static void msix_handle_mask_update(PCIDevice *dev, int vector)
{
    if (!msix_is_masked(dev, vector) && msix_is_pending(dev, vector)) {
        msix_clr_pending(dev, vector);
        msix_notify(dev, vector);
    }
}

/* Handle MSI-X capability config write. */
void msix_write_config(PCIDevice *dev, uint32_t addr,
                       uint32_t val, int len)
{
    unsigned enable_pos = dev->msix_cap + MSIX_CONTROL_OFFSET;
    int vector;

    if (addr + len <= enable_pos || addr > enable_pos) {
        return;
    }

    if (!msix_enabled(dev)) {
        return;
    }

    qemu_set_irq(dev->irq[0], 0);

    if (msix_function_masked(dev)) {
        return;
    }

    for (vector = 0; vector < dev->msix_entries_nr; ++vector) {
        msix_handle_mask_update(dev, vector);
    }
}

static void msix_mmio_writel(void *opaque, target_phys_addr_t addr,
                             uint32_t val)
{
    PCIDevice *dev = opaque;
    unsigned int offset = addr & (MSIX_PAGE_SIZE - 1) & ~0x3;
    int vector = offset / MSIX_ENTRY_SIZE;
    pci_set_long(dev->msix_table_page + offset, val);
    msix_handle_mask_update(dev, vector);
}

static void msix_mmio_write_unallowed(void *opaque, target_phys_addr_t addr,
                                      uint32_t val)
{
    fprintf(stderr, "MSI-X: only dword write is allowed!\n");
}

static CPUWriteMemoryFunc * const msix_mmio_write[] = {
    msix_mmio_write_unallowed, msix_mmio_write_unallowed, msix_mmio_writel
};

static CPUReadMemoryFunc * const msix_mmio_read[] = {
    msix_mmio_read_unallowed, msix_mmio_read_unallowed, msix_mmio_readl
};

/* Should be called from device's map method. */
void msix_mmio_map(PCIDevice *d, int region_num,
                   pcibus_t addr, pcibus_t size, int type)
{
    uint8_t *config = d->config + d->msix_cap;
    uint32_t table = pci_get_long(config + MSIX_TABLE_OFFSET);
    uint32_t offset = table & ~(MSIX_PAGE_SIZE - 1);
    /* TODO: for assigned devices, we'll want to make it possible to map
     * pending bits separately in case they are in a separate bar. */
    int table_bir = table & PCI_MSIX_FLAGS_BIRMASK;

    if (table_bir != region_num)
        return;
    if (size <= offset)
        return;
    cpu_register_physical_memory(addr + offset, size - offset,
                                 d->msix_mmio_index);
}

static void msix_mask_all(struct PCIDevice *dev, unsigned nentries)
{
    int vector;
    for (vector = 0; vector < nentries; ++vector) {
        unsigned offset = vector * MSIX_ENTRY_SIZE + MSIX_VECTOR_CTRL;
        dev->msix_table_page[offset] |= MSIX_VECTOR_MASK;
    }
}

/* Initialize the MSI-X structures. Note: if MSI-X is supported, BAR size is
 * modified, it should be retrieved with msix_bar_size. */
int msix_init(struct PCIDevice *dev, unsigned short nentries,
              unsigned bar_nr, unsigned bar_size)
{
    int ret;
    /* Nothing to do if MSI is not supported by interrupt controller */
    if (!msix_supported)
        return -ENOTSUP;

    if (nentries > MSIX_MAX_ENTRIES)
        return -EINVAL;

    dev->msix_entry_used = qemu_mallocz(MSIX_MAX_ENTRIES *
                                        sizeof *dev->msix_entry_used);

    dev->msix_table_page = qemu_mallocz(MSIX_PAGE_SIZE);
    msix_mask_all(dev, nentries);

    dev->msix_mmio_index = cpu_register_io_memory(msix_mmio_read,
                                                  msix_mmio_write, dev);
    if (dev->msix_mmio_index == -1) {
        ret = -EBUSY;
        goto err_index;
    }

    dev->msix_entries_nr = nentries;
    ret = msix_add_config(dev, nentries, bar_nr, bar_size);
    if (ret)
        goto err_config;

    dev->cap_present |= QEMU_PCI_CAP_MSIX;
    return 0;

err_config:
    dev->msix_entries_nr = 0;
    cpu_unregister_io_memory(dev->msix_mmio_index);
err_index:
    qemu_free(dev->msix_table_page);
    dev->msix_table_page = NULL;
    qemu_free(dev->msix_entry_used);
    dev->msix_entry_used = NULL;
    return ret;
}

static void msix_free_irq_entries(PCIDevice *dev)
{
    int vector;

    for (vector = 0; vector < dev->msix_entries_nr; ++vector) {
        dev->msix_entry_used[vector] = 0;
        msix_clr_pending(dev, vector);
    }
}

/* Clean up resources for the device. */
int msix_uninit(PCIDevice *dev)
{
    if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
        return 0;
    pci_del_capability(dev, PCI_CAP_ID_MSIX, MSIX_CAP_LENGTH);
    dev->msix_cap = 0;
    msix_free_irq_entries(dev);
    dev->msix_entries_nr = 0;
    cpu_unregister_io_memory(dev->msix_mmio_index);
    qemu_free(dev->msix_table_page);
    dev->msix_table_page = NULL;
    qemu_free(dev->msix_entry_used);
    dev->msix_entry_used = NULL;
    dev->cap_present &= ~QEMU_PCI_CAP_MSIX;
    return 0;
}

void msix_save(PCIDevice *dev, QEMUFile *f)
{
    unsigned n = dev->msix_entries_nr;

    if (!(dev->cap_present & QEMU_PCI_CAP_MSIX)) {
        return;
    }

    qemu_put_buffer(f, dev->msix_table_page, n * MSIX_ENTRY_SIZE);
    qemu_put_buffer(f, dev->msix_table_page + MSIX_PAGE_PENDING, (n + 7) / 8);
}

/* Should be called after restoring the config space. */
void msix_load(PCIDevice *dev, QEMUFile *f)
{
    unsigned n = dev->msix_entries_nr;

    if (!(dev->cap_present & QEMU_PCI_CAP_MSIX)) {
        return;
    }

    msix_free_irq_entries(dev);
    qemu_get_buffer(f, dev->msix_table_page, n * MSIX_ENTRY_SIZE);
    qemu_get_buffer(f, dev->msix_table_page + MSIX_PAGE_PENDING, (n + 7) / 8);
}

/* Does device support MSI-X? */
int msix_present(PCIDevice *dev)
{
    return dev->cap_present & QEMU_PCI_CAP_MSIX;
}

/* Is MSI-X enabled? */
int msix_enabled(PCIDevice *dev)
{
    return (dev->cap_present & QEMU_PCI_CAP_MSIX) &&
        (dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &
         MSIX_ENABLE_MASK);
}

/* Size of bar where MSI-X table resides, or 0 if MSI-X not supported. */
uint32_t msix_bar_size(PCIDevice *dev)
{
    return (dev->cap_present & QEMU_PCI_CAP_MSIX) ?
        dev->msix_bar_size : 0;
}

/* Send an MSI-X message */
void msix_notify(PCIDevice *dev, unsigned vector)
{
    uint8_t *table_entry = dev->msix_table_page + vector * MSIX_ENTRY_SIZE;
    uint64_t address;
    uint32_t data;

    if (vector >= dev->msix_entries_nr || !dev->msix_entry_used[vector])
        return;
    if (msix_is_masked(dev, vector)) {
        msix_set_pending(dev, vector);
        return;
    }

    address = pci_get_long(table_entry + MSIX_MSG_UPPER_ADDR);
    address = (address << 32) | pci_get_long(table_entry + MSIX_MSG_ADDR);
    data = pci_get_long(table_entry + MSIX_MSG_DATA);
    stl_phys(address, data);
}

void msix_reset(PCIDevice *dev)
{
    if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
        return;
    msix_free_irq_entries(dev);
    dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &=
	    ~dev->wmask[dev->msix_cap + MSIX_CONTROL_OFFSET];
    memset(dev->msix_table_page, 0, MSIX_PAGE_SIZE);
    msix_mask_all(dev, dev->msix_entries_nr);
}

/* PCI spec suggests that devices make it possible for software to configure
 * less vectors than supported by the device, but does not specify a standard
 * mechanism for devices to do so.
 *
 * We support this by asking devices to declare vectors software is going to
 * actually use, and checking this on the notification path. Devices that
 * don't want to follow the spec suggestion can declare all vectors as used. */

/* Mark vector as used. */
int msix_vector_use(PCIDevice *dev, unsigned vector)
{
    if (vector >= dev->msix_entries_nr)
        return -EINVAL;
    dev->msix_entry_used[vector]++;
    return 0;
}

/* Mark vector as unused. */
void msix_vector_unuse(PCIDevice *dev, unsigned vector)
{
    if (vector >= dev->msix_entries_nr || !dev->msix_entry_used[vector]) {
        return;
    }
    if (--dev->msix_entry_used[vector]) {
        return;
    }
    msix_clr_pending(dev, vector);
}

void msix_unuse_all_vectors(PCIDevice *dev)
{
    if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
        return;
    msix_free_irq_entries(dev);
}
Commit	Line	Data
02eb84d0 MT	1	/*
	2	* MSI-X device support
	3	*
	4	* This module includes support for MSI-X in pci devices.
	5	*
	6	* Author: Michael S. Tsirkin <[email protected]>
	7	*
	8	* Copyright (c) 2009, Red Hat Inc, Michael S. Tsirkin ([email protected])
	9	*
	10	* This work is licensed under the terms of the GNU GPL, version 2. See
	11	* the COPYING file in the top-level directory.
	12	*/
	13
	14	#include "hw.h"
	15	#include "msix.h"
	16	#include "pci.h"
	17
	18	/* Declaration from linux/pci_regs.h */
	19	#define PCI_CAP_ID_MSIX 0x11 /* MSI-X */
	20	#define PCI_MSIX_FLAGS 2 /* Table at lower 11 bits */
	21	#define PCI_MSIX_FLAGS_QSIZE 0x7FF
	22	#define PCI_MSIX_FLAGS_ENABLE (1 << 15)
5b5cb086	23	#define PCI_MSIX_FLAGS_MASKALL (1 << 14)
02eb84d0 MT	24	#define PCI_MSIX_FLAGS_BIRMASK (7 << 0)
	25
	26	/* MSI-X capability structure */
	27	#define MSIX_TABLE_OFFSET 4
	28	#define MSIX_PBA_OFFSET 8
	29	#define MSIX_CAP_LENGTH 12
	30
2760952b MT	31	/* MSI enable bit and maskall bit are in byte 1 in FLAGS register */
2760952b MT	32	#define MSIX_CONTROL_OFFSET (PCI_MSIX_FLAGS + 1)
02eb84d0	33	#define MSIX_ENABLE_MASK (PCI_MSIX_FLAGS_ENABLE >> 8)
5b5cb086	34	#define MSIX_MASKALL_MASK (PCI_MSIX_FLAGS_MASKALL >> 8)
02eb84d0 MT	35
	36	/* MSI-X table format */
	37	#define MSIX_MSG_ADDR 0
	38	#define MSIX_MSG_UPPER_ADDR 4
	39	#define MSIX_MSG_DATA 8
	40	#define MSIX_VECTOR_CTRL 12
	41	#define MSIX_ENTRY_SIZE 16
	42	#define MSIX_VECTOR_MASK 0x1
5a1fc5e8 MT	43
	44	/* How much space does an MSIX table need. */
	45	/* The spec requires giving the table structure
	46	* a 4K aligned region all by itself. */
	47	#define MSIX_PAGE_SIZE 0x1000
	48	/* Reserve second half of the page for pending bits */
	49	#define MSIX_PAGE_PENDING (MSIX_PAGE_SIZE / 2)
02eb84d0 MT	50	#define MSIX_MAX_ENTRIES 32
	51
	52
	53	#ifdef MSIX_DEBUG
	54	#define DEBUG(fmt, ...) \
	55	do { \
	56	fprintf(stderr, "%s: " fmt, __func__ , __VA_ARGS__); \
	57	} while (0)
	58	#else
	59	#define DEBUG(fmt, ...) do { } while(0)
	60	#endif
	61
	62	/* Flag for interrupt controller to declare MSI-X support */
	63	int msix_supported;
	64
	65	/* Add MSI-X capability to the config space for the device. */
	66	/* Given a bar and its size, add MSI-X table on top of it
	67	* and fill MSI-X capability in the config space.
	68	* Original bar size must be a power of 2 or 0.
	69	* New bar size is returned. */
	70	static int msix_add_config(struct PCIDevice *pdev, unsigned short nentries,
	71	unsigned bar_nr, unsigned bar_size)
	72	{
	73	int config_offset;
	74	uint8_t *config;
	75	uint32_t new_size;
	76
	77	if (nentries < 1 \|\| nentries > PCI_MSIX_FLAGS_QSIZE + 1)
	78	return -EINVAL;
	79	if (bar_size > 0x80000000)
	80	return -ENOSPC;
	81
	82	/* Add space for MSI-X structures */
5e520a7d	83	if (!bar_size) {
5a1fc5e8 MT	84	new_size = MSIX_PAGE_SIZE;
	85	} else if (bar_size < MSIX_PAGE_SIZE) {
	86	bar_size = MSIX_PAGE_SIZE;
	87	new_size = MSIX_PAGE_SIZE * 2;
	88	} else {
02eb84d0	89	new_size = bar_size * 2;
5a1fc5e8	90	}
02eb84d0 MT	91
	92	pdev->msix_bar_size = new_size;
	93	config_offset = pci_add_capability(pdev, PCI_CAP_ID_MSIX, MSIX_CAP_LENGTH);
	94	if (config_offset < 0)
	95	return config_offset;
	96	config = pdev->config + config_offset;
	97
	98	pci_set_word(config + PCI_MSIX_FLAGS, nentries - 1);
	99	/* Table on top of BAR */
	100	pci_set_long(config + MSIX_TABLE_OFFSET, bar_size \| bar_nr);
	101	/* Pending bits on top of that */
5a1fc5e8 MT	102	pci_set_long(config + MSIX_PBA_OFFSET, (bar_size + MSIX_PAGE_PENDING) \|
5a1fc5e8 MT	103	bar_nr);
02eb84d0 MT	104	pdev->msix_cap = config_offset;
02eb84d0 MT	105	/* Make flags bit writeable. */
5b5cb086 MT	106	pdev->wmask[config_offset + MSIX_CONTROL_OFFSET] \|= MSIX_ENABLE_MASK \|
5b5cb086 MT	107	MSIX_MASKALL_MASK;
02eb84d0 MT	108	return 0;
	109	}
	110
c227f099	111	static uint32_t msix_mmio_readl(void *opaque, target_phys_addr_t addr)
02eb84d0 MT	112	{
02eb84d0 MT	113	PCIDevice *dev = opaque;
76f5159d	114	unsigned int offset = addr & (MSIX_PAGE_SIZE - 1) & ~0x3;
02eb84d0	115	void *page = dev->msix_table_page;
02eb84d0	116
76f5159d	117	return pci_get_long(page + offset);
02eb84d0 MT	118	}
02eb84d0 MT	119
c227f099	120	static uint32_t msix_mmio_read_unallowed(void *opaque, target_phys_addr_t addr)
02eb84d0 MT	121	{
	122	fprintf(stderr, "MSI-X: only dword read is allowed!\n");
	123	return 0;
	124	}
	125
	126	static uint8_t msix_pending_mask(int vector)
	127	{
	128	return 1 << (vector % 8);
	129	}
	130
	131	static uint8_t msix_pending_byte(PCIDevice dev, int vector)
	132	{
5a1fc5e8	133	return dev->msix_table_page + MSIX_PAGE_PENDING + vector / 8;
02eb84d0 MT	134	}
	135
	136	static int msix_is_pending(PCIDevice *dev, int vector)
	137	{
	138	return *msix_pending_byte(dev, vector) & msix_pending_mask(vector);
	139	}
	140
	141	static void msix_set_pending(PCIDevice *dev, int vector)
	142	{
	143	*msix_pending_byte(dev, vector) \|= msix_pending_mask(vector);
	144	}
	145
	146	static void msix_clr_pending(PCIDevice *dev, int vector)
	147	{
	148	*msix_pending_byte(dev, vector) &= ~msix_pending_mask(vector);
	149	}
	150
5b5cb086 MT	151	static int msix_function_masked(PCIDevice *dev)
	152	{
	153	return dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] & MSIX_MASKALL_MASK;
	154	}
	155
02eb84d0 MT	156	static int msix_is_masked(PCIDevice *dev, int vector)
	157	{
	158	unsigned offset = vector * MSIX_ENTRY_SIZE + MSIX_VECTOR_CTRL;
5b5cb086 MT	159	return msix_function_masked(dev) \|\|
	160	dev->msix_table_page[offset] & MSIX_VECTOR_MASK;
	161	}
	162
	163	static void msix_handle_mask_update(PCIDevice *dev, int vector)
	164	{
	165	if (!msix_is_masked(dev, vector) && msix_is_pending(dev, vector)) {
	166	msix_clr_pending(dev, vector);
	167	msix_notify(dev, vector);
	168	}
	169	}
	170
	171	/* Handle MSI-X capability config write. */
	172	void msix_write_config(PCIDevice *dev, uint32_t addr,
	173	uint32_t val, int len)
	174	{
	175	unsigned enable_pos = dev->msix_cap + MSIX_CONTROL_OFFSET;
	176	int vector;
	177
	178	if (addr + len <= enable_pos \|\| addr > enable_pos) {
	179	return;
	180	}
	181
	182	if (!msix_enabled(dev)) {
	183	return;
	184	}
	185
	186	qemu_set_irq(dev->irq[0], 0);
	187
	188	if (msix_function_masked(dev)) {
	189	return;
	190	}
	191
	192	for (vector = 0; vector < dev->msix_entries_nr; ++vector) {
	193	msix_handle_mask_update(dev, vector);
	194	}
02eb84d0 MT	195	}
02eb84d0 MT	196
c227f099	197	static void msix_mmio_writel(void *opaque, target_phys_addr_t addr,
02eb84d0 MT	198	uint32_t val)
	199	{
	200	PCIDevice *dev = opaque;
76f5159d	201	unsigned int offset = addr & (MSIX_PAGE_SIZE - 1) & ~0x3;
02eb84d0	202	int vector = offset / MSIX_ENTRY_SIZE;
76f5159d	203	pci_set_long(dev->msix_table_page + offset, val);
5b5cb086	204	msix_handle_mask_update(dev, vector);
02eb84d0 MT	205	}
02eb84d0 MT	206
c227f099	207	static void msix_mmio_write_unallowed(void *opaque, target_phys_addr_t addr,
02eb84d0 MT	208	uint32_t val)
	209	{
	210	fprintf(stderr, "MSI-X: only dword write is allowed!\n");
	211	}
	212
d60efc6b	213	static CPUWriteMemoryFunc * const msix_mmio_write[] = {
02eb84d0 MT	214	msix_mmio_write_unallowed, msix_mmio_write_unallowed, msix_mmio_writel
	215	};
	216
d60efc6b	217	static CPUReadMemoryFunc * const msix_mmio_read[] = {
02eb84d0 MT	218	msix_mmio_read_unallowed, msix_mmio_read_unallowed, msix_mmio_readl
	219	};
	220
	221	/* Should be called from device's map method. */
	222	void msix_mmio_map(PCIDevice *d, int region_num,
6e355d90	223	pcibus_t addr, pcibus_t size, int type)
02eb84d0 MT	224	{
	225	uint8_t *config = d->config + d->msix_cap;
	226	uint32_t table = pci_get_long(config + MSIX_TABLE_OFFSET);
5a1fc5e8	227	uint32_t offset = table & ~(MSIX_PAGE_SIZE - 1);
02eb84d0 MT	228	/* TODO: for assigned devices, we'll want to make it possible to map
	229	* pending bits separately in case they are in a separate bar. */
	230	int table_bir = table & PCI_MSIX_FLAGS_BIRMASK;
	231
	232	if (table_bir != region_num)
	233	return;
	234	if (size <= offset)
	235	return;
	236	cpu_register_physical_memory(addr + offset, size - offset,
	237	d->msix_mmio_index);
	238	}
	239
ae1be0bb MT	240	static void msix_mask_all(struct PCIDevice *dev, unsigned nentries)
	241	{
	242	int vector;
	243	for (vector = 0; vector < nentries; ++vector) {
	244	unsigned offset = vector * MSIX_ENTRY_SIZE + MSIX_VECTOR_CTRL;
	245	dev->msix_table_page[offset] \|= MSIX_VECTOR_MASK;
	246	}
	247	}
	248
02eb84d0 MT	249	/* Initialize the MSI-X structures. Note: if MSI-X is supported, BAR size is
	250	* modified, it should be retrieved with msix_bar_size. */
	251	int msix_init(struct PCIDevice *dev, unsigned short nentries,
5a1fc5e8	252	unsigned bar_nr, unsigned bar_size)
02eb84d0 MT	253	{
	254	int ret;
	255	/* Nothing to do if MSI is not supported by interrupt controller */
	256	if (!msix_supported)
	257	return -ENOTSUP;
	258
	259	if (nentries > MSIX_MAX_ENTRIES)
	260	return -EINVAL;
	261
	262	dev->msix_entry_used = qemu_mallocz(MSIX_MAX_ENTRIES *
	263	sizeof *dev->msix_entry_used);
	264
5a1fc5e8	265	dev->msix_table_page = qemu_mallocz(MSIX_PAGE_SIZE);
ae1be0bb	266	msix_mask_all(dev, nentries);
02eb84d0 MT	267
	268	dev->msix_mmio_index = cpu_register_io_memory(msix_mmio_read,
	269	msix_mmio_write, dev);
	270	if (dev->msix_mmio_index == -1) {
	271	ret = -EBUSY;
	272	goto err_index;
	273	}
	274
	275	dev->msix_entries_nr = nentries;
	276	ret = msix_add_config(dev, nentries, bar_nr, bar_size);
	277	if (ret)
	278	goto err_config;
	279
	280	dev->cap_present \|= QEMU_PCI_CAP_MSIX;
	281	return 0;
	282
	283	err_config:
3174ecd1	284	dev->msix_entries_nr = 0;
02eb84d0 MT	285	cpu_unregister_io_memory(dev->msix_mmio_index);
	286	err_index:
	287	qemu_free(dev->msix_table_page);
	288	dev->msix_table_page = NULL;
	289	qemu_free(dev->msix_entry_used);
	290	dev->msix_entry_used = NULL;
	291	return ret;
	292	}
	293
98304c84 MT	294	static void msix_free_irq_entries(PCIDevice *dev)
	295	{
	296	int vector;
	297
	298	for (vector = 0; vector < dev->msix_entries_nr; ++vector) {
	299	dev->msix_entry_used[vector] = 0;
	300	msix_clr_pending(dev, vector);
	301	}
	302	}
	303
02eb84d0 MT	304	/* Clean up resources for the device. */
	305	int msix_uninit(PCIDevice *dev)
	306	{
	307	if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
	308	return 0;
	309	pci_del_capability(dev, PCI_CAP_ID_MSIX, MSIX_CAP_LENGTH);
	310	dev->msix_cap = 0;
	311	msix_free_irq_entries(dev);
	312	dev->msix_entries_nr = 0;
	313	cpu_unregister_io_memory(dev->msix_mmio_index);
	314	qemu_free(dev->msix_table_page);
	315	dev->msix_table_page = NULL;
	316	qemu_free(dev->msix_entry_used);
	317	dev->msix_entry_used = NULL;
	318	dev->cap_present &= ~QEMU_PCI_CAP_MSIX;
	319	return 0;
	320	}
	321
	322	void msix_save(PCIDevice dev, QEMUFile f)
	323	{
9a3e12c8 MT	324	unsigned n = dev->msix_entries_nr;
9a3e12c8 MT	325
72755a70	326	if (!(dev->cap_present & QEMU_PCI_CAP_MSIX)) {
9a3e12c8	327	return;
72755a70	328	}
9a3e12c8 MT	329
9a3e12c8 MT	330	qemu_put_buffer(f, dev->msix_table_page, n * MSIX_ENTRY_SIZE);
5a1fc5e8	331	qemu_put_buffer(f, dev->msix_table_page + MSIX_PAGE_PENDING, (n + 7) / 8);
02eb84d0 MT	332	}
	333
	334	/* Should be called after restoring the config space. */
	335	void msix_load(PCIDevice dev, QEMUFile f)
	336	{
	337	unsigned n = dev->msix_entries_nr;
	338
98846d73	339	if (!(dev->cap_present & QEMU_PCI_CAP_MSIX)) {
02eb84d0	340	return;
98846d73	341	}
02eb84d0	342
4bfd1712	343	msix_free_irq_entries(dev);
02eb84d0	344	qemu_get_buffer(f, dev->msix_table_page, n * MSIX_ENTRY_SIZE);
5a1fc5e8	345	qemu_get_buffer(f, dev->msix_table_page + MSIX_PAGE_PENDING, (n + 7) / 8);
02eb84d0 MT	346	}
	347
	348	/* Does device support MSI-X? */
	349	int msix_present(PCIDevice *dev)
	350	{
	351	return dev->cap_present & QEMU_PCI_CAP_MSIX;
	352	}
	353
	354	/* Is MSI-X enabled? */
	355	int msix_enabled(PCIDevice *dev)
	356	{
	357	return (dev->cap_present & QEMU_PCI_CAP_MSIX) &&
2760952b	358	(dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &
02eb84d0 MT	359	MSIX_ENABLE_MASK);
	360	}
	361
	362	/* Size of bar where MSI-X table resides, or 0 if MSI-X not supported. */
	363	uint32_t msix_bar_size(PCIDevice *dev)
	364	{
	365	return (dev->cap_present & QEMU_PCI_CAP_MSIX) ?
	366	dev->msix_bar_size : 0;
	367	}
	368
	369	/* Send an MSI-X message */
	370	void msix_notify(PCIDevice *dev, unsigned vector)
	371	{
	372	uint8_t table_entry = dev->msix_table_page + vector MSIX_ENTRY_SIZE;
	373	uint64_t address;
	374	uint32_t data;
	375
	376	if (vector >= dev->msix_entries_nr \|\| !dev->msix_entry_used[vector])
	377	return;
	378	if (msix_is_masked(dev, vector)) {
	379	msix_set_pending(dev, vector);
	380	return;
	381	}
	382
	383	address = pci_get_long(table_entry + MSIX_MSG_UPPER_ADDR);
	384	address = (address << 32) \| pci_get_long(table_entry + MSIX_MSG_ADDR);
	385	data = pci_get_long(table_entry + MSIX_MSG_DATA);
	386	stl_phys(address, data);
	387	}
	388
	389	void msix_reset(PCIDevice *dev)
	390	{
	391	if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
	392	return;
	393	msix_free_irq_entries(dev);
2760952b MT	394	dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &=
2760952b MT	395	~dev->wmask[dev->msix_cap + MSIX_CONTROL_OFFSET];
5a1fc5e8	396	memset(dev->msix_table_page, 0, MSIX_PAGE_SIZE);
ae1be0bb	397	msix_mask_all(dev, dev->msix_entries_nr);
02eb84d0 MT	398	}
	399
	400	/* PCI spec suggests that devices make it possible for software to configure
	401	* less vectors than supported by the device, but does not specify a standard
	402	* mechanism for devices to do so.
	403	*
	404	* We support this by asking devices to declare vectors software is going to
	405	* actually use, and checking this on the notification path. Devices that
	406	* don't want to follow the spec suggestion can declare all vectors as used. */
	407
	408	/* Mark vector as used. */
	409	int msix_vector_use(PCIDevice *dev, unsigned vector)
	410	{
	411	if (vector >= dev->msix_entries_nr)
	412	return -EINVAL;
	413	dev->msix_entry_used[vector]++;
	414	return 0;
	415	}
	416
	417	/* Mark vector as unused. */
	418	void msix_vector_unuse(PCIDevice *dev, unsigned vector)
	419	{
98304c84 MT	420	if (vector >= dev->msix_entries_nr \|\| !dev->msix_entry_used[vector]) {
	421	return;
	422	}
	423	if (--dev->msix_entry_used[vector]) {
	424	return;
	425	}
	426	msix_clr_pending(dev, vector);
02eb84d0	427	}
b5f28bca MT	428
	429	void msix_unuse_all_vectors(PCIDevice *dev)
	430	{
	431	if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
	432	return;
	433	msix_free_irq_entries(dev);
	434	}