[qemu.git] / hw / xen / xen_pt.h

#ifndef XEN_PT_H
#define XEN_PT_H

#include "qemu-common.h"
#include "hw/xen/xen_common.h"
#include "hw/pci/pci.h"
#include "xen-host-pci-device.h"

void xen_pt_log(const PCIDevice *d, const char *f, ...) GCC_FMT_ATTR(2, 3);

#define XEN_PT_ERR(d, _f, _a...) xen_pt_log(d, "%s: Error: "_f, __func__, ##_a)

#ifdef XEN_PT_LOGGING_ENABLED
#  define XEN_PT_LOG(d, _f, _a...)  xen_pt_log(d, "%s: " _f, __func__, ##_a)
#  define XEN_PT_WARN(d, _f, _a...) \
    xen_pt_log(d, "%s: Warning: "_f, __func__, ##_a)
#else
#  define XEN_PT_LOG(d, _f, _a...)
#  define XEN_PT_WARN(d, _f, _a...)
#endif

#ifdef XEN_PT_DEBUG_PCI_CONFIG_ACCESS
#  define XEN_PT_LOG_CONFIG(d, addr, val, len) \
    xen_pt_log(d, "%s: address=0x%04x val=0x%08x len=%d\n", \
               __func__, addr, val, len)
#else
#  define XEN_PT_LOG_CONFIG(d, addr, val, len)
#endif


/* Helper */
#define XEN_PFN(x) ((x) >> XC_PAGE_SHIFT)

typedef const struct XenPTRegInfo XenPTRegInfo;
typedef struct XenPTReg XenPTReg;

typedef struct XenPCIPassthroughState XenPCIPassthroughState;

#define TYPE_XEN_PT_DEVICE "xen-pci-passthrough"
#define XEN_PT_DEVICE(obj) \
    OBJECT_CHECK(XenPCIPassthroughState, (obj), TYPE_XEN_PT_DEVICE)

uint32_t igd_read_opregion(XenPCIPassthroughState *s);
void igd_write_opregion(XenPCIPassthroughState *s, uint32_t val);

/* function type for config reg */
typedef int (*xen_pt_conf_reg_init)
    (XenPCIPassthroughState *, XenPTRegInfo *, uint32_t real_offset,
     uint32_t *data);
typedef int (*xen_pt_conf_dword_write)
    (XenPCIPassthroughState *, XenPTReg *cfg_entry,
     uint32_t *val, uint32_t dev_value, uint32_t valid_mask);
typedef int (*xen_pt_conf_word_write)
    (XenPCIPassthroughState *, XenPTReg *cfg_entry,
     uint16_t *val, uint16_t dev_value, uint16_t valid_mask);
typedef int (*xen_pt_conf_byte_write)
    (XenPCIPassthroughState *, XenPTReg *cfg_entry,
     uint8_t *val, uint8_t dev_value, uint8_t valid_mask);
typedef int (*xen_pt_conf_dword_read)
    (XenPCIPassthroughState *, XenPTReg *cfg_entry,
     uint32_t *val, uint32_t valid_mask);
typedef int (*xen_pt_conf_word_read)
    (XenPCIPassthroughState *, XenPTReg *cfg_entry,
     uint16_t *val, uint16_t valid_mask);
typedef int (*xen_pt_conf_byte_read)
    (XenPCIPassthroughState *, XenPTReg *cfg_entry,
     uint8_t *val, uint8_t valid_mask);

#define XEN_PT_BAR_ALLF 0xFFFFFFFF
#define XEN_PT_BAR_UNMAPPED (-1)

#define XEN_PCI_CAP_MAX 48

#define XEN_PCI_INTEL_OPREGION 0xfc

typedef enum {
    XEN_PT_GRP_TYPE_HARDWIRED = 0,  /* 0 Hardwired reg group */
    XEN_PT_GRP_TYPE_EMU,            /* emul reg group */
} XenPTRegisterGroupType;

typedef enum {
    XEN_PT_BAR_FLAG_MEM = 0,        /* Memory type BAR */
    XEN_PT_BAR_FLAG_IO,             /* I/O type BAR */
    XEN_PT_BAR_FLAG_UPPER,          /* upper 64bit BAR */
    XEN_PT_BAR_FLAG_UNUSED,         /* unused BAR */
} XenPTBarFlag;


typedef struct XenPTRegion {
    /* BAR flag */
    XenPTBarFlag bar_flag;
    /* Translation of the emulated address */
    union {
        uint64_t maddr;
        uint64_t pio_base;
        uint64_t u;
    } access;
} XenPTRegion;

/* XenPTRegInfo declaration
 * - only for emulated register (either a part or whole bit).
 * - for passthrough register that need special behavior (like interacting with
 *   other component), set emu_mask to all 0 and specify r/w func properly.
 * - do NOT use ALL F for init_val, otherwise the tbl will not be registered.
 */

/* emulated register information */
struct XenPTRegInfo {
    uint32_t offset;
    uint32_t size;
    uint32_t init_val;
    /* reg reserved field mask (ON:reserved, OFF:defined) */
    uint32_t res_mask;
    /* reg read only field mask (ON:RO/ROS, OFF:other) */
    uint32_t ro_mask;
    /* reg read/write-1-clear field mask (ON:RW1C/RW1CS, OFF:other) */
    uint32_t rw1c_mask;
    /* reg emulate field mask (ON:emu, OFF:passthrough) */
    uint32_t emu_mask;
    xen_pt_conf_reg_init init;
    /* read/write function pointer
     * for double_word/word/byte size */
    union {
        struct {
            xen_pt_conf_dword_write write;
            xen_pt_conf_dword_read read;
        } dw;
        struct {
            xen_pt_conf_word_write write;
            xen_pt_conf_word_read read;
        } w;
        struct {
            xen_pt_conf_byte_write write;
            xen_pt_conf_byte_read read;
        } b;
    } u;
};

/* emulated register management */
struct XenPTReg {
    QLIST_ENTRY(XenPTReg) entries;
    XenPTRegInfo *reg;
    union {
        uint8_t *byte;
        uint16_t *half_word;
        uint32_t *word;
    } ptr; /* pointer to dev.config. */
};

typedef const struct XenPTRegGroupInfo XenPTRegGroupInfo;

/* emul reg group size initialize method */
typedef int (*xen_pt_reg_size_init_fn)
    (XenPCIPassthroughState *, XenPTRegGroupInfo *,
     uint32_t base_offset, uint8_t *size);

/* emulated register group information */
struct XenPTRegGroupInfo {
    uint8_t grp_id;
    XenPTRegisterGroupType grp_type;
    uint8_t grp_size;
    xen_pt_reg_size_init_fn size_init;
    XenPTRegInfo *emu_regs;
};

/* emul register group management table */
typedef struct XenPTRegGroup {
    QLIST_ENTRY(XenPTRegGroup) entries;
    XenPTRegGroupInfo *reg_grp;
    uint32_t base_offset;
    uint8_t size;
    QLIST_HEAD(, XenPTReg) reg_tbl_list;
} XenPTRegGroup;


#define XEN_PT_UNASSIGNED_PIRQ (-1)
typedef struct XenPTMSI {
    uint16_t flags;
    uint32_t addr_lo;  /* guest message address */
    uint32_t addr_hi;  /* guest message upper address */
    uint16_t data;     /* guest message data */
    uint32_t ctrl_offset; /* saved control offset */
    uint32_t mask;     /* guest mask bits */
    int pirq;          /* guest pirq corresponding */
    bool initialized;  /* when guest MSI is initialized */
    bool mapped;       /* when pirq is mapped */
} XenPTMSI;

typedef struct XenPTMSIXEntry {
    int pirq;
    uint64_t addr;
    uint32_t data;
    uint32_t latch[4];
    bool updated; /* indicate whether MSI ADDR or DATA is updated */
} XenPTMSIXEntry;
typedef struct XenPTMSIX {
    uint32_t ctrl_offset;
    bool enabled;
    bool maskall;
    int total_entries;
    int bar_index;
    uint64_t table_base;
    uint32_t table_offset_adjust; /* page align mmap */
    uint64_t mmio_base_addr;
    MemoryRegion mmio;
    void *phys_iomem_base;
    XenPTMSIXEntry msix_entry[0];
} XenPTMSIX;

struct XenPCIPassthroughState {
    PCIDevice dev;

    PCIHostDeviceAddress hostaddr;
    bool is_virtfn;
    bool permissive;
    bool permissive_warned;
    XenHostPCIDevice real_device;
    XenPTRegion bases[PCI_NUM_REGIONS]; /* Access regions */
    QLIST_HEAD(, XenPTRegGroup) reg_grps;

    uint32_t machine_irq;

    XenPTMSI *msi;
    XenPTMSIX *msix;

    MemoryRegion bar[PCI_NUM_REGIONS - 1];
    MemoryRegion rom;

    MemoryListener memory_listener;
    MemoryListener io_listener;
    bool listener_set;
};

void xen_pt_config_init(XenPCIPassthroughState *s, Error **errp);
void xen_pt_config_delete(XenPCIPassthroughState *s);
XenPTRegGroup *xen_pt_find_reg_grp(XenPCIPassthroughState *s, uint32_t address);
XenPTReg *xen_pt_find_reg(XenPTRegGroup *reg_grp, uint32_t address);
int xen_pt_bar_offset_to_index(uint32_t offset);

static inline pcibus_t xen_pt_get_emul_size(XenPTBarFlag flag, pcibus_t r_size)
{
    /* align resource size (memory type only) */
    if (flag == XEN_PT_BAR_FLAG_MEM) {
        return (r_size + XC_PAGE_SIZE - 1) & XC_PAGE_MASK;
    } else {
        return r_size;
    }
}

/* INTx */
/* The PCI Local Bus Specification, Rev. 3.0,
 * Section 6.2.4 Miscellaneous Registers, pp 223
 * outlines 5 valid values for the interrupt pin (intx).
 *  0: For devices (or device functions) that don't use an interrupt in
 *  1: INTA#
 *  2: INTB#
 *  3: INTC#
 *  4: INTD#
 *
 * Xen uses the following 4 values for intx
 *  0: INTA#
 *  1: INTB#
 *  2: INTC#
 *  3: INTD#
 *
 * Observing that these list of values are not the same, xen_pt_pci_read_intx()
 * uses the following mapping from hw to xen values.
 * This seems to reflect the current usage within Xen.
 *
 * PCI hardware    | Xen | Notes
 * ----------------+-----+----------------------------------------------------
 * 0               | 0   | No interrupt
 * 1               | 0   | INTA#
 * 2               | 1   | INTB#
 * 3               | 2   | INTC#
 * 4               | 3   | INTD#
 * any other value | 0   | This should never happen, log error message
 */

static inline uint8_t xen_pt_pci_read_intx(XenPCIPassthroughState *s)
{
    uint8_t v = 0;
    xen_host_pci_get_byte(&s->real_device, PCI_INTERRUPT_PIN, &v);
    return v;
}

static inline uint8_t xen_pt_pci_intx(XenPCIPassthroughState *s)
{
    uint8_t r_val = xen_pt_pci_read_intx(s);

    XEN_PT_LOG(&s->dev, "intx=%i\n", r_val);
    if (r_val < 1 || r_val > 4) {
        XEN_PT_LOG(&s->dev, "Interrupt pin read from hardware is out of range:"
                   " value=%i, acceptable range is 1 - 4\n", r_val);
        r_val = 0;
    } else {
        /* Note that if s.real_device.config_fd is closed we make 0xff. */
        r_val -= 1;
    }

    return r_val;
}

/* MSI/MSI-X */
int xen_pt_msi_setup(XenPCIPassthroughState *s);
int xen_pt_msi_update(XenPCIPassthroughState *d);
void xen_pt_msi_disable(XenPCIPassthroughState *s);

int xen_pt_msix_init(XenPCIPassthroughState *s, uint32_t base);
void xen_pt_msix_delete(XenPCIPassthroughState *s);
void xen_pt_msix_unmap(XenPCIPassthroughState *s);
int xen_pt_msix_update(XenPCIPassthroughState *s);
int xen_pt_msix_update_remap(XenPCIPassthroughState *s, int bar_index);
void xen_pt_msix_disable(XenPCIPassthroughState *s);

static inline bool xen_pt_has_msix_mapping(XenPCIPassthroughState *s, int bar)
{
    return s->msix && s->msix->bar_index == bar;
}

extern void *pci_assign_dev_load_option_rom(PCIDevice *dev,
                                            int *size,
                                            unsigned int domain,
                                            unsigned int bus, unsigned int slot,
                                            unsigned int function);
extern bool has_igd_gfx_passthru;
static inline bool is_igd_vga_passthrough(XenHostPCIDevice *dev)
{
    return (has_igd_gfx_passthru
            && ((dev->class_code >> 0x8) == PCI_CLASS_DISPLAY_VGA));
}
int xen_pt_register_vga_regions(XenHostPCIDevice *dev);
int xen_pt_unregister_vga_regions(XenHostPCIDevice *dev);
void xen_pt_setup_vga(XenPCIPassthroughState *s, XenHostPCIDevice *dev,
                     Error **errp);
#endif /* XEN_PT_H */
Commit	Line	Data
eaab4d60 AK	1	#ifndef XEN_PT_H
	2	#define XEN_PT_H
	3
	4	#include "qemu-common.h"
0d09e41a	5	#include "hw/xen/xen_common.h"
83c9f4ca	6	#include "hw/pci/pci.h"
47b43a1f	7	#include "xen-host-pci-device.h"
eaab4d60 AK	8
	9	void xen_pt_log(const PCIDevice d, const char f, ...) GCC_FMT_ATTR(2, 3);
	10
	11	#define XEN_PT_ERR(d, _f, _a...) xen_pt_log(d, "%s: Error: "_f, __func__, ##_a)
	12
	13	#ifdef XEN_PT_LOGGING_ENABLED
	14	# define XEN_PT_LOG(d, _f, _a...) xen_pt_log(d, "%s: " _f, __func__, ##_a)
	15	# define XEN_PT_WARN(d, _f, _a...) \
	16	xen_pt_log(d, "%s: Warning: "_f, __func__, ##_a)
	17	#else
	18	# define XEN_PT_LOG(d, _f, _a...)
	19	# define XEN_PT_WARN(d, _f, _a...)
	20	#endif
	21
	22	#ifdef XEN_PT_DEBUG_PCI_CONFIG_ACCESS
	23	# define XEN_PT_LOG_CONFIG(d, addr, val, len) \
	24	xen_pt_log(d, "%s: address=0x%04x val=0x%08x len=%d\n", \
	25	__func__, addr, val, len)
	26	#else
	27	# define XEN_PT_LOG_CONFIG(d, addr, val, len)
	28	#endif
	29
	30
	31	/* Helper */
	32	#define XEN_PFN(x) ((x) >> XC_PAGE_SHIFT)
	33
74526eb0	34	typedef const struct XenPTRegInfo XenPTRegInfo;
eaab4d60 AK	35	typedef struct XenPTReg XenPTReg;
	36
	37	typedef struct XenPCIPassthroughState XenPCIPassthroughState;
	38
f9b9d292 GA	39	#define TYPE_XEN_PT_DEVICE "xen-pci-passthrough"
	40	#define XEN_PT_DEVICE(obj) \
	41	OBJECT_CHECK(XenPCIPassthroughState, (obj), TYPE_XEN_PT_DEVICE)
	42
5cec8aa3 TC	43	uint32_t igd_read_opregion(XenPCIPassthroughState *s);
	44	void igd_write_opregion(XenPCIPassthroughState *s, uint32_t val);
	45
eaab4d60 AK	46	/* function type for config reg */
	47	typedef int (*xen_pt_conf_reg_init)
	48	(XenPCIPassthroughState , XenPTRegInfo , uint32_t real_offset,
	49	uint32_t *data);
	50	typedef int (*xen_pt_conf_dword_write)
	51	(XenPCIPassthroughState , XenPTReg cfg_entry,
	52	uint32_t *val, uint32_t dev_value, uint32_t valid_mask);
	53	typedef int (*xen_pt_conf_word_write)
	54	(XenPCIPassthroughState , XenPTReg cfg_entry,
	55	uint16_t *val, uint16_t dev_value, uint16_t valid_mask);
	56	typedef int (*xen_pt_conf_byte_write)
	57	(XenPCIPassthroughState , XenPTReg cfg_entry,
	58	uint8_t *val, uint8_t dev_value, uint8_t valid_mask);
	59	typedef int (*xen_pt_conf_dword_read)
	60	(XenPCIPassthroughState , XenPTReg cfg_entry,
	61	uint32_t *val, uint32_t valid_mask);
	62	typedef int (*xen_pt_conf_word_read)
	63	(XenPCIPassthroughState , XenPTReg cfg_entry,
	64	uint16_t *val, uint16_t valid_mask);
	65	typedef int (*xen_pt_conf_byte_read)
	66	(XenPCIPassthroughState , XenPTReg cfg_entry,
	67	uint8_t *val, uint8_t valid_mask);
	68
	69	#define XEN_PT_BAR_ALLF 0xFFFFFFFF
	70	#define XEN_PT_BAR_UNMAPPED (-1)
	71
5cec8aa3	72	#define XEN_PCI_CAP_MAX 48
93d7ae8e	73
5cec8aa3	74	#define XEN_PCI_INTEL_OPREGION 0xfc
eaab4d60 AK	75
	76	typedef enum {
	77	XEN_PT_GRP_TYPE_HARDWIRED = 0, /* 0 Hardwired reg group */
	78	XEN_PT_GRP_TYPE_EMU, /* emul reg group */
	79	} XenPTRegisterGroupType;
	80
	81	typedef enum {
	82	XEN_PT_BAR_FLAG_MEM = 0, /* Memory type BAR */
	83	XEN_PT_BAR_FLAG_IO, /* I/O type BAR */
	84	XEN_PT_BAR_FLAG_UPPER, /* upper 64bit BAR */
	85	XEN_PT_BAR_FLAG_UNUSED, /* unused BAR */
	86	} XenPTBarFlag;
	87
	88
	89	typedef struct XenPTRegion {
	90	/* BAR flag */
	91	XenPTBarFlag bar_flag;
	92	/* Translation of the emulated address */
	93	union {
	94	uint64_t maddr;
	95	uint64_t pio_base;
	96	uint64_t u;
	97	} access;
	98	} XenPTRegion;
	99
	100	/* XenPTRegInfo declaration
	101	* - only for emulated register (either a part or whole bit).
	102	* - for passthrough register that need special behavior (like interacting with
	103	* other component), set emu_mask to all 0 and specify r/w func properly.
	104	* - do NOT use ALL F for init_val, otherwise the tbl will not be registered.
	105	*/
	106
0546b8c2	107	/* emulated register information */
eaab4d60 AK	108	struct XenPTRegInfo {
	109	uint32_t offset;
	110	uint32_t size;
	111	uint32_t init_val;
0ad3393a JB	112	/* reg reserved field mask (ON:reserved, OFF:defined) */
0ad3393a JB	113	uint32_t res_mask;
eaab4d60 AK	114	/* reg read only field mask (ON:RO/ROS, OFF:other) */
eaab4d60 AK	115	uint32_t ro_mask;
55c8672c JB	116	/* reg read/write-1-clear field mask (ON:RW1C/RW1CS, OFF:other) */
55c8672c JB	117	uint32_t rw1c_mask;
eaab4d60 AK	118	/* reg emulate field mask (ON:emu, OFF:passthrough) */
eaab4d60 AK	119	uint32_t emu_mask;
eaab4d60 AK	120	xen_pt_conf_reg_init init;
	121	/* read/write function pointer
	122	* for double_word/word/byte size */
	123	union {
	124	struct {
	125	xen_pt_conf_dword_write write;
	126	xen_pt_conf_dword_read read;
	127	} dw;
	128	struct {
	129	xen_pt_conf_word_write write;
	130	xen_pt_conf_word_read read;
	131	} w;
	132	struct {
	133	xen_pt_conf_byte_write write;
	134	xen_pt_conf_byte_read read;
	135	} b;
	136	} u;
	137	};
	138
	139	/* emulated register management */
	140	struct XenPTReg {
	141	QLIST_ENTRY(XenPTReg) entries;
	142	XenPTRegInfo *reg;
e2779de0 KRW	143	union {
	144	uint8_t *byte;
	145	uint16_t *half_word;
	146	uint32_t *word;
	147	} ptr; /* pointer to dev.config. */
eaab4d60 AK	148	};
eaab4d60 AK	149
74526eb0	150	typedef const struct XenPTRegGroupInfo XenPTRegGroupInfo;
eaab4d60 AK	151
	152	/* emul reg group size initialize method */
	153	typedef int (*xen_pt_reg_size_init_fn)
74526eb0	154	(XenPCIPassthroughState , XenPTRegGroupInfo ,
eaab4d60 AK	155	uint32_t base_offset, uint8_t *size);
eaab4d60 AK	156
0546b8c2	157	/* emulated register group information */
eaab4d60 AK	158	struct XenPTRegGroupInfo {
	159	uint8_t grp_id;
	160	XenPTRegisterGroupType grp_type;
	161	uint8_t grp_size;
	162	xen_pt_reg_size_init_fn size_init;
	163	XenPTRegInfo *emu_regs;
	164	};
	165
	166	/* emul register group management table */
	167	typedef struct XenPTRegGroup {
	168	QLIST_ENTRY(XenPTRegGroup) entries;
74526eb0	169	XenPTRegGroupInfo *reg_grp;
eaab4d60 AK	170	uint32_t base_offset;
	171	uint8_t size;
	172	QLIST_HEAD(, XenPTReg) reg_tbl_list;
	173	} XenPTRegGroup;
	174
	175
	176	#define XEN_PT_UNASSIGNED_PIRQ (-1)
3854ca57 JY	177	typedef struct XenPTMSI {
	178	uint16_t flags;
	179	uint32_t addr_lo; /* guest message address */
	180	uint32_t addr_hi; /* guest message upper address */
	181	uint16_t data; /* guest message data */
	182	uint32_t ctrl_offset; /* saved control offset */
a8036336	183	uint32_t mask; /* guest mask bits */
3854ca57 JY	184	int pirq; /* guest pirq corresponding */
	185	bool initialized; /* when guest MSI is initialized */
	186	bool mapped; /* when pirq is mapped */
	187	} XenPTMSI;
	188
	189	typedef struct XenPTMSIXEntry {
	190	int pirq;
	191	uint64_t addr;
	192	uint32_t data;
f0ada360	193	uint32_t latch[4];
3854ca57 JY	194	bool updated; /* indicate whether MSI ADDR or DATA is updated */
	195	} XenPTMSIXEntry;
	196	typedef struct XenPTMSIX {
	197	uint32_t ctrl_offset;
	198	bool enabled;
f0ada360	199	bool maskall;
3854ca57 JY	200	int total_entries;
	201	int bar_index;
	202	uint64_t table_base;
	203	uint32_t table_offset_adjust; /* page align mmap */
	204	uint64_t mmio_base_addr;
	205	MemoryRegion mmio;
	206	void *phys_iomem_base;
	207	XenPTMSIXEntry msix_entry[0];
	208	} XenPTMSIX;
eaab4d60 AK	209
	210	struct XenPCIPassthroughState {
	211	PCIDevice dev;
	212
	213	PCIHostDeviceAddress hostaddr;
	214	bool is_virtfn;
c25bbf15 JB	215	bool permissive;
c25bbf15 JB	216	bool permissive_warned;
eaab4d60 AK	217	XenHostPCIDevice real_device;
	218	XenPTRegion bases[PCI_NUM_REGIONS]; /* Access regions */
	219	QLIST_HEAD(, XenPTRegGroup) reg_grps;
	220
	221	uint32_t machine_irq;
	222
3854ca57 JY	223	XenPTMSI *msi;
	224	XenPTMSIX *msix;
	225
eaab4d60 AK	226	MemoryRegion bar[PCI_NUM_REGIONS - 1];
	227	MemoryRegion rom;
	228
	229	MemoryListener memory_listener;
12b40e47	230	MemoryListener io_listener;
bce33948	231	bool listener_set;
eaab4d60 AK	232	};
eaab4d60 AK	233
d50a6e58	234	void xen_pt_config_init(XenPCIPassthroughState s, Error *errp);
eaab4d60 AK	235	void xen_pt_config_delete(XenPCIPassthroughState *s);
	236	XenPTRegGroup xen_pt_find_reg_grp(XenPCIPassthroughState s, uint32_t address);
	237	XenPTReg xen_pt_find_reg(XenPTRegGroup reg_grp, uint32_t address);
	238	int xen_pt_bar_offset_to_index(uint32_t offset);
	239
	240	static inline pcibus_t xen_pt_get_emul_size(XenPTBarFlag flag, pcibus_t r_size)
	241	{
	242	/* align resource size (memory type only) */
	243	if (flag == XEN_PT_BAR_FLAG_MEM) {
	244	return (r_size + XC_PAGE_SIZE - 1) & XC_PAGE_MASK;
	245	} else {
	246	return r_size;
	247	}
	248	}
	249
	250	/* INTx */
	251	/* The PCI Local Bus Specification, Rev. 3.0,
	252	* Section 6.2.4 Miscellaneous Registers, pp 223
	253	* outlines 5 valid values for the interrupt pin (intx).
	254	* 0: For devices (or device functions) that don't use an interrupt in
	255	* 1: INTA#
	256	* 2: INTB#
	257	* 3: INTC#
	258	* 4: INTD#
	259	*
	260	* Xen uses the following 4 values for intx
	261	* 0: INTA#
	262	* 1: INTB#
	263	* 2: INTC#
	264	* 3: INTD#
	265	*
	266	* Observing that these list of values are not the same, xen_pt_pci_read_intx()
	267	* uses the following mapping from hw to xen values.
	268	* This seems to reflect the current usage within Xen.
	269	*
	270	* PCI hardware \| Xen \| Notes
	271	* ----------------+-----+----------------------------------------------------
	272	* 0 \| 0 \| No interrupt
	273	* 1 \| 0 \| INTA#
	274	* 2 \| 1 \| INTB#
	275	* 3 \| 2 \| INTC#
	276	* 4 \| 3 \| INTD#
	277	* any other value \| 0 \| This should never happen, log error message
	278	*/
	279
	280	static inline uint8_t xen_pt_pci_read_intx(XenPCIPassthroughState *s)
	281	{
	282	uint8_t v = 0;
	283	xen_host_pci_get_byte(&s->real_device, PCI_INTERRUPT_PIN, &v);
	284	return v;
	285	}
	286
	287	static inline uint8_t xen_pt_pci_intx(XenPCIPassthroughState *s)
	288	{
	289	uint8_t r_val = xen_pt_pci_read_intx(s);
	290
	291	XEN_PT_LOG(&s->dev, "intx=%i\n", r_val);
	292	if (r_val < 1 \|\| r_val > 4) {
	293	XEN_PT_LOG(&s->dev, "Interrupt pin read from hardware is out of range:"
	294	" value=%i, acceptable range is 1 - 4\n", r_val);
	295	r_val = 0;
	296	} else {
bce33948	297	/* Note that if s.real_device.config_fd is closed we make 0xff. */
eaab4d60 AK	298	r_val -= 1;
	299	}
	300
	301	return r_val;
	302	}
	303
3854ca57	304	/* MSI/MSI-X */
3854ca57 JY	305	int xen_pt_msi_setup(XenPCIPassthroughState *s);
	306	int xen_pt_msi_update(XenPCIPassthroughState *d);
	307	void xen_pt_msi_disable(XenPCIPassthroughState *s);
	308
	309	int xen_pt_msix_init(XenPCIPassthroughState *s, uint32_t base);
	310	void xen_pt_msix_delete(XenPCIPassthroughState *s);
4e494de6	311	void xen_pt_msix_unmap(XenPCIPassthroughState *s);
3854ca57 JY	312	int xen_pt_msix_update(XenPCIPassthroughState *s);
	313	int xen_pt_msix_update_remap(XenPCIPassthroughState *s, int bar_index);
	314	void xen_pt_msix_disable(XenPCIPassthroughState *s);
	315
	316	static inline bool xen_pt_has_msix_mapping(XenPCIPassthroughState *s, int bar)
	317	{
	318	return s->msix && s->msix->bar_index == bar;
	319	}
	320
881213f1	321	extern void pci_assign_dev_load_option_rom(PCIDevice dev,
6dad8260	322	int *size,
881213f1 TC	323	unsigned int domain,
	324	unsigned int bus, unsigned int slot,
	325	unsigned int function);
79814179 TC	326	extern bool has_igd_gfx_passthru;
	327	static inline bool is_igd_vga_passthrough(XenHostPCIDevice *dev)
	328	{
	329	return (has_igd_gfx_passthru
	330	&& ((dev->class_code >> 0x8) == PCI_CLASS_DISPLAY_VGA));
	331	}
	332	int xen_pt_register_vga_regions(XenHostPCIDevice *dev);
	333	int xen_pt_unregister_vga_regions(XenHostPCIDevice *dev);
5226bb59 C	334	void xen_pt_setup_vga(XenPCIPassthroughState s, XenHostPCIDevice dev,
5226bb59 C	335	Error **errp);
175de524	336	#endif /* XEN_PT_H */