[qemu.git] / target / i386 / arch_memory_mapping.c

/*
 * i386 memory mapping
 *
 * Copyright Fujitsu, Corp. 2011, 2012
 *
 * Authors:
 *     Wen Congyang <[email protected]>
 *
 * This work is licensed under the terms of the GNU GPL, version 2 or later.
 * See the COPYING file in the top-level directory.
 *
 */

#include "qemu/osdep.h"
#include "cpu.h"
#include "exec/cpu-all.h"
#include "sysemu/memory_mapping.h"

/* PAE Paging or IA-32e Paging */
static void walk_pte(MemoryMappingList *list, AddressSpace *as,
                     hwaddr pte_start_addr,
                     int32_t a20_mask, target_ulong start_line_addr)
{
    hwaddr pte_addr, start_paddr;
    uint64_t pte;
    target_ulong start_vaddr;
    int i;

    for (i = 0; i < 512; i++) {
        pte_addr = (pte_start_addr + i * 8) & a20_mask;
        pte = address_space_ldq(as, pte_addr, MEMTXATTRS_UNSPECIFIED, NULL);
        if (!(pte & PG_PRESENT_MASK)) {
            /* not present */
            continue;
        }

        start_paddr = (pte & ~0xfff) & ~(0x1ULL << 63);
        if (cpu_physical_memory_is_io(start_paddr)) {
            /* I/O region */
            continue;
        }

        start_vaddr = start_line_addr | ((i & 0x1ff) << 12);
        memory_mapping_list_add_merge_sorted(list, start_paddr,
                                             start_vaddr, 1 << 12);
    }
}

/* 32-bit Paging */
static void walk_pte2(MemoryMappingList *list, AddressSpace *as,
                      hwaddr pte_start_addr, int32_t a20_mask,
                      target_ulong start_line_addr)
{
    hwaddr pte_addr, start_paddr;
    uint32_t pte;
    target_ulong start_vaddr;
    int i;

    for (i = 0; i < 1024; i++) {
        pte_addr = (pte_start_addr + i * 4) & a20_mask;
        pte = address_space_ldl(as, pte_addr, MEMTXATTRS_UNSPECIFIED, NULL);
        if (!(pte & PG_PRESENT_MASK)) {
            /* not present */
            continue;
        }

        start_paddr = pte & ~0xfff;
        if (cpu_physical_memory_is_io(start_paddr)) {
            /* I/O region */
            continue;
        }

        start_vaddr = start_line_addr | ((i & 0x3ff) << 12);
        memory_mapping_list_add_merge_sorted(list, start_paddr,
                                             start_vaddr, 1 << 12);
    }
}

/* PAE Paging or IA-32e Paging */
#define PLM4_ADDR_MASK 0xffffffffff000ULL /* selects bits 51:12 */

static void walk_pde(MemoryMappingList *list, AddressSpace *as,
                     hwaddr pde_start_addr,
                     int32_t a20_mask, target_ulong start_line_addr)
{
    hwaddr pde_addr, pte_start_addr, start_paddr;
    uint64_t pde;
    target_ulong line_addr, start_vaddr;
    int i;

    for (i = 0; i < 512; i++) {
        pde_addr = (pde_start_addr + i * 8) & a20_mask;
        pde = address_space_ldq(as, pde_addr, MEMTXATTRS_UNSPECIFIED, NULL);
        if (!(pde & PG_PRESENT_MASK)) {
            /* not present */
            continue;
        }

        line_addr = start_line_addr | ((i & 0x1ff) << 21);
        if (pde & PG_PSE_MASK) {
            /* 2 MB page */
            start_paddr = (pde & ~0x1fffff) & ~(0x1ULL << 63);
            if (cpu_physical_memory_is_io(start_paddr)) {
                /* I/O region */
                continue;
            }
            start_vaddr = line_addr;
            memory_mapping_list_add_merge_sorted(list, start_paddr,
                                                 start_vaddr, 1 << 21);
            continue;
        }

        pte_start_addr = (pde & PLM4_ADDR_MASK) & a20_mask;
        walk_pte(list, as, pte_start_addr, a20_mask, line_addr);
    }
}

/* 32-bit Paging */
static void walk_pde2(MemoryMappingList *list, AddressSpace *as,
                      hwaddr pde_start_addr, int32_t a20_mask,
                      bool pse)
{
    hwaddr pde_addr, pte_start_addr, start_paddr, high_paddr;
    uint32_t pde;
    target_ulong line_addr, start_vaddr;
    int i;

    for (i = 0; i < 1024; i++) {
        pde_addr = (pde_start_addr + i * 4) & a20_mask;
        pde = address_space_ldl(as, pde_addr, MEMTXATTRS_UNSPECIFIED, NULL);
        if (!(pde & PG_PRESENT_MASK)) {
            /* not present */
            continue;
        }

        line_addr = (((unsigned int)i & 0x3ff) << 22);
        if ((pde & PG_PSE_MASK) && pse) {
            /*
             * 4 MB page:
             * bits 39:32 are bits 20:13 of the PDE
             * bit3 31:22 are bits 31:22 of the PDE
             */
            high_paddr = ((hwaddr)(pde & 0x1fe000) << 19);
            start_paddr = (pde & ~0x3fffff) | high_paddr;
            if (cpu_physical_memory_is_io(start_paddr)) {
                /* I/O region */
                continue;
            }
            start_vaddr = line_addr;
            memory_mapping_list_add_merge_sorted(list, start_paddr,
                                                 start_vaddr, 1 << 22);
            continue;
        }

        pte_start_addr = (pde & ~0xfff) & a20_mask;
        walk_pte2(list, as, pte_start_addr, a20_mask, line_addr);
    }
}

/* PAE Paging */
static void walk_pdpe2(MemoryMappingList *list, AddressSpace *as,
                       hwaddr pdpe_start_addr, int32_t a20_mask)
{
    hwaddr pdpe_addr, pde_start_addr;
    uint64_t pdpe;
    target_ulong line_addr;
    int i;

    for (i = 0; i < 4; i++) {
        pdpe_addr = (pdpe_start_addr + i * 8) & a20_mask;
        pdpe = address_space_ldq(as, pdpe_addr, MEMTXATTRS_UNSPECIFIED, NULL);
        if (!(pdpe & PG_PRESENT_MASK)) {
            /* not present */
            continue;
        }

        line_addr = (((unsigned int)i & 0x3) << 30);
        pde_start_addr = (pdpe & ~0xfff) & a20_mask;
        walk_pde(list, as, pde_start_addr, a20_mask, line_addr);
    }
}

#ifdef TARGET_X86_64
/* IA-32e Paging */
static void walk_pdpe(MemoryMappingList *list, AddressSpace *as,
                      hwaddr pdpe_start_addr, int32_t a20_mask,
                      target_ulong start_line_addr)
{
    hwaddr pdpe_addr, pde_start_addr, start_paddr;
    uint64_t pdpe;
    target_ulong line_addr, start_vaddr;
    int i;

    for (i = 0; i < 512; i++) {
        pdpe_addr = (pdpe_start_addr + i * 8) & a20_mask;
        pdpe = address_space_ldq(as, pdpe_addr, MEMTXATTRS_UNSPECIFIED, NULL);
        if (!(pdpe & PG_PRESENT_MASK)) {
            /* not present */
            continue;
        }

        line_addr = start_line_addr | ((i & 0x1ffULL) << 30);
        if (pdpe & PG_PSE_MASK) {
            /* 1 GB page */
            start_paddr = (pdpe & ~0x3fffffff) & ~(0x1ULL << 63);
            if (cpu_physical_memory_is_io(start_paddr)) {
                /* I/O region */
                continue;
            }
            start_vaddr = line_addr;
            memory_mapping_list_add_merge_sorted(list, start_paddr,
                                                 start_vaddr, 1 << 30);
            continue;
        }

        pde_start_addr = (pdpe & PLM4_ADDR_MASK) & a20_mask;
        walk_pde(list, as, pde_start_addr, a20_mask, line_addr);
    }
}

/* IA-32e Paging */
static void walk_pml4e(MemoryMappingList *list, AddressSpace *as,
                       hwaddr pml4e_start_addr, int32_t a20_mask,
                       target_ulong start_line_addr)
{
    hwaddr pml4e_addr, pdpe_start_addr;
    uint64_t pml4e;
    target_ulong line_addr;
    int i;

    for (i = 0; i < 512; i++) {
        pml4e_addr = (pml4e_start_addr + i * 8) & a20_mask;
        pml4e = address_space_ldq(as, pml4e_addr, MEMTXATTRS_UNSPECIFIED,
                                  NULL);
        if (!(pml4e & PG_PRESENT_MASK)) {
            /* not present */
            continue;
        }

        line_addr = start_line_addr | ((i & 0x1ffULL) << 39);
        pdpe_start_addr = (pml4e & PLM4_ADDR_MASK) & a20_mask;
        walk_pdpe(list, as, pdpe_start_addr, a20_mask, line_addr);
    }
}

static void walk_pml5e(MemoryMappingList *list, AddressSpace *as,
                       hwaddr pml5e_start_addr, int32_t a20_mask)
{
    hwaddr pml5e_addr, pml4e_start_addr;
    uint64_t pml5e;
    target_ulong line_addr;
    int i;

    for (i = 0; i < 512; i++) {
        pml5e_addr = (pml5e_start_addr + i * 8) & a20_mask;
        pml5e = address_space_ldq(as, pml5e_addr, MEMTXATTRS_UNSPECIFIED,
                                  NULL);
        if (!(pml5e & PG_PRESENT_MASK)) {
            /* not present */
            continue;
        }

        line_addr = (0x7fULL << 57) | ((i & 0x1ffULL) << 48);
        pml4e_start_addr = (pml5e & PLM4_ADDR_MASK) & a20_mask;
        walk_pml4e(list, as, pml4e_start_addr, a20_mask, line_addr);
    }
}
#endif

void x86_cpu_get_memory_mapping(CPUState *cs, MemoryMappingList *list,
                                Error **errp)
{
    X86CPU *cpu = X86_CPU(cs);
    CPUX86State *env = &cpu->env;

    if (!cpu_paging_enabled(cs)) {
        /* paging is disabled */
        return;
    }

    if (env->cr[4] & CR4_PAE_MASK) {
#ifdef TARGET_X86_64
        if (env->hflags & HF_LMA_MASK) {
            if (env->cr[4] & CR4_LA57_MASK) {
                hwaddr pml5e_addr;

                pml5e_addr = (env->cr[3] & PLM4_ADDR_MASK) & env->a20_mask;
                walk_pml5e(list, cs->as, pml5e_addr, env->a20_mask);
            } else {
                hwaddr pml4e_addr;

                pml4e_addr = (env->cr[3] & PLM4_ADDR_MASK) & env->a20_mask;
                walk_pml4e(list, cs->as, pml4e_addr, env->a20_mask,
                        0xffffULL << 48);
            }
        } else
#endif
        {
            hwaddr pdpe_addr;

            pdpe_addr = (env->cr[3] & ~0x1f) & env->a20_mask;
            walk_pdpe2(list, cs->as, pdpe_addr, env->a20_mask);
        }
    } else {
        hwaddr pde_addr;
        bool pse;

        pde_addr = (env->cr[3] & ~0xfff) & env->a20_mask;
        pse = !!(env->cr[4] & CR4_PSE_MASK);
        walk_pde2(list, cs->as, pde_addr, env->a20_mask, pse);
    }
}
Commit	Line	Data
fae001f5 WC	1	/*
	2	* i386 memory mapping
	3	*
	4	* Copyright Fujitsu, Corp. 2011, 2012
	5	*
	6	* Authors:
	7	* Wen Congyang <[email protected]>
	8	*
fc0608ac SW	9	* This work is licensed under the terms of the GNU GPL, version 2 or later.
fc0608ac SW	10	* See the COPYING file in the top-level directory.
fae001f5 WC	11	*
	12	*/
	13
b6a0aa05	14	#include "qemu/osdep.h"
fae001f5	15	#include "cpu.h"
022c62cb	16	#include "exec/cpu-all.h"
9c17d615	17	#include "sysemu/memory_mapping.h"
fae001f5 WC	18
fae001f5 WC	19	/* PAE Paging or IA-32e Paging */
fdfba1a2 EI	20	static void walk_pte(MemoryMappingList list, AddressSpace as,
fdfba1a2 EI	21	hwaddr pte_start_addr,
fae001f5 WC	22	int32_t a20_mask, target_ulong start_line_addr)
fae001f5 WC	23	{
a8170e5e	24	hwaddr pte_addr, start_paddr;
fae001f5 WC	25	uint64_t pte;
	26	target_ulong start_vaddr;
	27	int i;
	28
	29	for (i = 0; i < 512; i++) {
	30	pte_addr = (pte_start_addr + i * 8) & a20_mask;
42874d3a	31	pte = address_space_ldq(as, pte_addr, MEMTXATTRS_UNSPECIFIED, NULL);
fae001f5 WC	32	if (!(pte & PG_PRESENT_MASK)) {
	33	/* not present */
	34	continue;
	35	}
	36
	37	start_paddr = (pte & ~0xfff) & ~(0x1ULL << 63);
	38	if (cpu_physical_memory_is_io(start_paddr)) {
	39	/* I/O region */
	40	continue;
	41	}
	42
bff63471	43	start_vaddr = start_line_addr \| ((i & 0x1ff) << 12);
fae001f5 WC	44	memory_mapping_list_add_merge_sorted(list, start_paddr,
	45	start_vaddr, 1 << 12);
	46	}
	47	}
	48
	49	/* 32-bit Paging */
fdfba1a2	50	static void walk_pte2(MemoryMappingList list, AddressSpace as,
a8170e5e	51	hwaddr pte_start_addr, int32_t a20_mask,
fae001f5 WC	52	target_ulong start_line_addr)
fae001f5 WC	53	{
a8170e5e	54	hwaddr pte_addr, start_paddr;
fae001f5 WC	55	uint32_t pte;
	56	target_ulong start_vaddr;
	57	int i;
	58
	59	for (i = 0; i < 1024; i++) {
	60	pte_addr = (pte_start_addr + i * 4) & a20_mask;
42874d3a	61	pte = address_space_ldl(as, pte_addr, MEMTXATTRS_UNSPECIFIED, NULL);
fae001f5 WC	62	if (!(pte & PG_PRESENT_MASK)) {
	63	/* not present */
	64	continue;
	65	}
	66
	67	start_paddr = pte & ~0xfff;
	68	if (cpu_physical_memory_is_io(start_paddr)) {
	69	/* I/O region */
	70	continue;
	71	}
	72
	73	start_vaddr = start_line_addr \| ((i & 0x3ff) << 12);
	74	memory_mapping_list_add_merge_sorted(list, start_paddr,
	75	start_vaddr, 1 << 12);
	76	}
	77	}
	78
	79	/* PAE Paging or IA-32e Paging */
00fdef65	80	#define PLM4_ADDR_MASK 0xffffffffff000ULL /* selects bits 51:12 */
fbc2ed95	81
fdfba1a2 EI	82	static void walk_pde(MemoryMappingList list, AddressSpace as,
fdfba1a2 EI	83	hwaddr pde_start_addr,
fae001f5 WC	84	int32_t a20_mask, target_ulong start_line_addr)
fae001f5 WC	85	{
a8170e5e	86	hwaddr pde_addr, pte_start_addr, start_paddr;
fae001f5 WC	87	uint64_t pde;
	88	target_ulong line_addr, start_vaddr;
	89	int i;
	90
	91	for (i = 0; i < 512; i++) {
	92	pde_addr = (pde_start_addr + i * 8) & a20_mask;
42874d3a	93	pde = address_space_ldq(as, pde_addr, MEMTXATTRS_UNSPECIFIED, NULL);
fae001f5 WC	94	if (!(pde & PG_PRESENT_MASK)) {
	95	/* not present */
	96	continue;
	97	}
	98
	99	line_addr = start_line_addr \| ((i & 0x1ff) << 21);
	100	if (pde & PG_PSE_MASK) {
	101	/* 2 MB page */
	102	start_paddr = (pde & ~0x1fffff) & ~(0x1ULL << 63);
	103	if (cpu_physical_memory_is_io(start_paddr)) {
	104	/* I/O region */
	105	continue;
	106	}
	107	start_vaddr = line_addr;
	108	memory_mapping_list_add_merge_sorted(list, start_paddr,
	109	start_vaddr, 1 << 21);
	110	continue;
	111	}
	112
fbc2ed95	113	pte_start_addr = (pde & PLM4_ADDR_MASK) & a20_mask;
fdfba1a2	114	walk_pte(list, as, pte_start_addr, a20_mask, line_addr);
fae001f5 WC	115	}
	116	}
	117
	118	/* 32-bit Paging */
fdfba1a2	119	static void walk_pde2(MemoryMappingList list, AddressSpace as,
a8170e5e	120	hwaddr pde_start_addr, int32_t a20_mask,
fae001f5 WC	121	bool pse)
fae001f5 WC	122	{
6ad53bdf	123	hwaddr pde_addr, pte_start_addr, start_paddr, high_paddr;
fae001f5 WC	124	uint32_t pde;
	125	target_ulong line_addr, start_vaddr;
	126	int i;
	127
	128	for (i = 0; i < 1024; i++) {
	129	pde_addr = (pde_start_addr + i * 4) & a20_mask;
42874d3a	130	pde = address_space_ldl(as, pde_addr, MEMTXATTRS_UNSPECIFIED, NULL);
fae001f5 WC	131	if (!(pde & PG_PRESENT_MASK)) {
	132	/* not present */
	133	continue;
	134	}
	135
	136	line_addr = (((unsigned int)i & 0x3ff) << 22);
	137	if ((pde & PG_PSE_MASK) && pse) {
6ad53bdf WC	138	/*
	139	* 4 MB page:
	140	* bits 39:32 are bits 20:13 of the PDE
	141	* bit3 31:22 are bits 31:22 of the PDE
	142	*/
	143	high_paddr = ((hwaddr)(pde & 0x1fe000) << 19);
	144	start_paddr = (pde & ~0x3fffff) \| high_paddr;
fae001f5 WC	145	if (cpu_physical_memory_is_io(start_paddr)) {
	146	/* I/O region */
	147	continue;
	148	}
	149	start_vaddr = line_addr;
	150	memory_mapping_list_add_merge_sorted(list, start_paddr,
	151	start_vaddr, 1 << 22);
	152	continue;
	153	}
	154
	155	pte_start_addr = (pde & ~0xfff) & a20_mask;
fdfba1a2	156	walk_pte2(list, as, pte_start_addr, a20_mask, line_addr);
fae001f5 WC	157	}
	158	}
	159
	160	/* PAE Paging */
fdfba1a2	161	static void walk_pdpe2(MemoryMappingList list, AddressSpace as,
a8170e5e	162	hwaddr pdpe_start_addr, int32_t a20_mask)
fae001f5	163	{
a8170e5e	164	hwaddr pdpe_addr, pde_start_addr;
fae001f5 WC	165	uint64_t pdpe;
	166	target_ulong line_addr;
	167	int i;
	168
	169	for (i = 0; i < 4; i++) {
	170	pdpe_addr = (pdpe_start_addr + i * 8) & a20_mask;
42874d3a	171	pdpe = address_space_ldq(as, pdpe_addr, MEMTXATTRS_UNSPECIFIED, NULL);
fae001f5 WC	172	if (!(pdpe & PG_PRESENT_MASK)) {
	173	/* not present */
	174	continue;
	175	}
	176
	177	line_addr = (((unsigned int)i & 0x3) << 30);
	178	pde_start_addr = (pdpe & ~0xfff) & a20_mask;
fdfba1a2	179	walk_pde(list, as, pde_start_addr, a20_mask, line_addr);
fae001f5 WC	180	}
	181	}
	182
	183	#ifdef TARGET_X86_64
	184	/* IA-32e Paging */
fdfba1a2	185	static void walk_pdpe(MemoryMappingList list, AddressSpace as,
a8170e5e	186	hwaddr pdpe_start_addr, int32_t a20_mask,
fae001f5 WC	187	target_ulong start_line_addr)
fae001f5 WC	188	{
a8170e5e	189	hwaddr pdpe_addr, pde_start_addr, start_paddr;
fae001f5 WC	190	uint64_t pdpe;
	191	target_ulong line_addr, start_vaddr;
	192	int i;
	193
	194	for (i = 0; i < 512; i++) {
	195	pdpe_addr = (pdpe_start_addr + i * 8) & a20_mask;
42874d3a	196	pdpe = address_space_ldq(as, pdpe_addr, MEMTXATTRS_UNSPECIFIED, NULL);
fae001f5 WC	197	if (!(pdpe & PG_PRESENT_MASK)) {
	198	/* not present */
	199	continue;
	200	}
	201
	202	line_addr = start_line_addr \| ((i & 0x1ffULL) << 30);
	203	if (pdpe & PG_PSE_MASK) {
	204	/* 1 GB page */
	205	start_paddr = (pdpe & ~0x3fffffff) & ~(0x1ULL << 63);
	206	if (cpu_physical_memory_is_io(start_paddr)) {
	207	/* I/O region */
	208	continue;
	209	}
	210	start_vaddr = line_addr;
	211	memory_mapping_list_add_merge_sorted(list, start_paddr,
	212	start_vaddr, 1 << 30);
	213	continue;
	214	}
	215
fbc2ed95	216	pde_start_addr = (pdpe & PLM4_ADDR_MASK) & a20_mask;
fdfba1a2	217	walk_pde(list, as, pde_start_addr, a20_mask, line_addr);
fae001f5 WC	218	}
	219	}
	220
	221	/* IA-32e Paging */
fdfba1a2	222	static void walk_pml4e(MemoryMappingList list, AddressSpace as,
6c7c3c21 KS	223	hwaddr pml4e_start_addr, int32_t a20_mask,
6c7c3c21 KS	224	target_ulong start_line_addr)
fae001f5	225	{
a8170e5e	226	hwaddr pml4e_addr, pdpe_start_addr;
fae001f5 WC	227	uint64_t pml4e;
	228	target_ulong line_addr;
	229	int i;
	230
	231	for (i = 0; i < 512; i++) {
	232	pml4e_addr = (pml4e_start_addr + i * 8) & a20_mask;
42874d3a PM	233	pml4e = address_space_ldq(as, pml4e_addr, MEMTXATTRS_UNSPECIFIED,
42874d3a PM	234	NULL);
fae001f5 WC	235	if (!(pml4e & PG_PRESENT_MASK)) {
	236	/* not present */
	237	continue;
	238	}
	239
6c7c3c21	240	line_addr = start_line_addr \| ((i & 0x1ffULL) << 39);
fbc2ed95	241	pdpe_start_addr = (pml4e & PLM4_ADDR_MASK) & a20_mask;
fdfba1a2	242	walk_pdpe(list, as, pdpe_start_addr, a20_mask, line_addr);
fae001f5 WC	243	}
fae001f5 WC	244	}
6c7c3c21 KS	245
	246	static void walk_pml5e(MemoryMappingList list, AddressSpace as,
	247	hwaddr pml5e_start_addr, int32_t a20_mask)
	248	{
	249	hwaddr pml5e_addr, pml4e_start_addr;
	250	uint64_t pml5e;
	251	target_ulong line_addr;
	252	int i;
	253
	254	for (i = 0; i < 512; i++) {
	255	pml5e_addr = (pml5e_start_addr + i * 8) & a20_mask;
	256	pml5e = address_space_ldq(as, pml5e_addr, MEMTXATTRS_UNSPECIFIED,
	257	NULL);
	258	if (!(pml5e & PG_PRESENT_MASK)) {
	259	/* not present */
	260	continue;
	261	}
	262
	263	line_addr = (0x7fULL << 57) \| ((i & 0x1ffULL) << 48);
	264	pml4e_start_addr = (pml5e & PLM4_ADDR_MASK) & a20_mask;
	265	walk_pml4e(list, as, pml4e_start_addr, a20_mask, line_addr);
	266	}
	267	}
fae001f5 WC	268	#endif
fae001f5 WC	269
a23bbfda AF	270	void x86_cpu_get_memory_mapping(CPUState cs, MemoryMappingList list,
a23bbfda AF	271	Error **errp)
fae001f5	272	{
a23bbfda AF	273	X86CPU *cpu = X86_CPU(cs);
	274	CPUX86State *env = &cpu->env;
	275
	276	if (!cpu_paging_enabled(cs)) {
fae001f5	277	/* paging is disabled */
a23bbfda	278	return;
fae001f5 WC	279	}
	280
	281	if (env->cr[4] & CR4_PAE_MASK) {
	282	#ifdef TARGET_X86_64
	283	if (env->hflags & HF_LMA_MASK) {
6c7c3c21 KS	284	if (env->cr[4] & CR4_LA57_MASK) {
	285	hwaddr pml5e_addr;
	286
	287	pml5e_addr = (env->cr[3] & PLM4_ADDR_MASK) & env->a20_mask;
	288	walk_pml5e(list, cs->as, pml5e_addr, env->a20_mask);
	289	} else {
	290	hwaddr pml4e_addr;
fae001f5	291
6c7c3c21 KS	292	pml4e_addr = (env->cr[3] & PLM4_ADDR_MASK) & env->a20_mask;
	293	walk_pml4e(list, cs->as, pml4e_addr, env->a20_mask,
	294	0xffffULL << 48);
	295	}
fae001f5 WC	296	} else
	297	#endif
	298	{
a8170e5e	299	hwaddr pdpe_addr;
fae001f5 WC	300
fae001f5 WC	301	pdpe_addr = (env->cr[3] & ~0x1f) & env->a20_mask;
fdfba1a2	302	walk_pdpe2(list, cs->as, pdpe_addr, env->a20_mask);
fae001f5 WC	303	}
fae001f5 WC	304	} else {
a8170e5e	305	hwaddr pde_addr;
fae001f5 WC	306	bool pse;
	307
	308	pde_addr = (env->cr[3] & ~0xfff) & env->a20_mask;
	309	pse = !!(env->cr[4] & CR4_PSE_MASK);
fdfba1a2	310	walk_pde2(list, cs->as, pde_addr, env->a20_mask, pse);
fae001f5	311	}
fae001f5	312	}
31a2207a	313