[qemu.git] / hw / char / serial-pci.c

/*
 * QEMU 16550A UART emulation
 *
 * Copyright (c) 2003-2004 Fabrice Bellard
 * Copyright (c) 2008 Citrix Systems, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

/* see docs/specs/pci-serial.txt */

#include "hw/char/serial.h"
#include "hw/pci/pci.h"
#include "qapi/qmp/qerror.h"

#define PCI_SERIAL_MAX_PORTS 4

typedef struct PCISerialState {
    PCIDevice dev;
    SerialState state;
    uint8_t prog_if;
} PCISerialState;

typedef struct PCIMultiSerialState {
    PCIDevice    dev;
    MemoryRegion iobar;
    uint32_t     ports;
    char         *name[PCI_SERIAL_MAX_PORTS];
    SerialState  state[PCI_SERIAL_MAX_PORTS];
    uint32_t     level[PCI_SERIAL_MAX_PORTS];
    qemu_irq     *irqs;
    uint8_t      prog_if;
} PCIMultiSerialState;

static int serial_pci_init(PCIDevice *dev)
{
    PCISerialState *pci = DO_UPCAST(PCISerialState, dev, dev);
    SerialState *s = &pci->state;
    Error *err = NULL;

    s->baudbase = 115200;
    serial_realize_core(s, &err);
    if (err != NULL) {
        qerror_report_err(err);
        error_free(err);
        return -1;
    }

    pci->dev.config[PCI_CLASS_PROG] = pci->prog_if;
    pci->dev.config[PCI_INTERRUPT_PIN] = 0x01;
    s->irq = pci_allocate_irq(&pci->dev);

    memory_region_init_io(&s->io, OBJECT(pci), &serial_io_ops, s, "serial", 8);
    pci_register_bar(&pci->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io);
    return 0;
}

static void multi_serial_irq_mux(void *opaque, int n, int level)
{
    PCIMultiSerialState *pci = opaque;
    int i, pending = 0;

    pci->level[n] = level;
    for (i = 0; i < pci->ports; i++) {
        if (pci->level[i]) {
            pending = 1;
        }
    }
    pci_set_irq(&pci->dev, pending);
}

static int multi_serial_pci_init(PCIDevice *dev)
{
    PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
    PCIMultiSerialState *pci = DO_UPCAST(PCIMultiSerialState, dev, dev);
    SerialState *s;
    Error *err = NULL;
    int i;

    switch (pc->device_id) {
    case 0x0003:
        pci->ports = 2;
        break;
    case 0x0004:
        pci->ports = 4;
        break;
    }
    assert(pci->ports > 0);
    assert(pci->ports <= PCI_SERIAL_MAX_PORTS);

    pci->dev.config[PCI_CLASS_PROG] = pci->prog_if;
    pci->dev.config[PCI_INTERRUPT_PIN] = 0x01;
    memory_region_init(&pci->iobar, OBJECT(pci), "multiserial", 8 * pci->ports);
    pci_register_bar(&pci->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &pci->iobar);
    pci->irqs = qemu_allocate_irqs(multi_serial_irq_mux, pci,
                                   pci->ports);

    for (i = 0; i < pci->ports; i++) {
        s = pci->state + i;
        s->baudbase = 115200;
        serial_realize_core(s, &err);
        if (err != NULL) {
            qerror_report_err(err);
            error_free(err);
            return -1;
        }
        s->irq = pci->irqs[i];
        pci->name[i] = g_strdup_printf("uart #%d", i+1);
        memory_region_init_io(&s->io, OBJECT(pci), &serial_io_ops, s,
                              pci->name[i], 8);
        memory_region_add_subregion(&pci->iobar, 8 * i, &s->io);
    }
    return 0;
}

static void serial_pci_exit(PCIDevice *dev)
{
    PCISerialState *pci = DO_UPCAST(PCISerialState, dev, dev);
    SerialState *s = &pci->state;

    serial_exit_core(s);
    memory_region_destroy(&s->io);
    qemu_free_irq(s->irq);
}

static void multi_serial_pci_exit(PCIDevice *dev)
{
    PCIMultiSerialState *pci = DO_UPCAST(PCIMultiSerialState, dev, dev);
    SerialState *s;
    int i;

    for (i = 0; i < pci->ports; i++) {
        s = pci->state + i;
        serial_exit_core(s);
        memory_region_del_subregion(&pci->iobar, &s->io);
        memory_region_destroy(&s->io);
        g_free(pci->name[i]);
    }
    memory_region_destroy(&pci->iobar);
    qemu_free_irqs(pci->irqs, pci->ports);
}

static const VMStateDescription vmstate_pci_serial = {
    .name = "pci-serial",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_PCI_DEVICE(dev, PCISerialState),
        VMSTATE_STRUCT(state, PCISerialState, 0, vmstate_serial, SerialState),
        VMSTATE_END_OF_LIST()
    }
};

static const VMStateDescription vmstate_pci_multi_serial = {
    .name = "pci-serial-multi",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_PCI_DEVICE(dev, PCIMultiSerialState),
        VMSTATE_STRUCT_ARRAY(state, PCIMultiSerialState, PCI_SERIAL_MAX_PORTS,
                             0, vmstate_serial, SerialState),
        VMSTATE_UINT32_ARRAY(level, PCIMultiSerialState, PCI_SERIAL_MAX_PORTS),
        VMSTATE_END_OF_LIST()
    }
};

static Property serial_pci_properties[] = {
    DEFINE_PROP_CHR("chardev",  PCISerialState, state.chr),
    DEFINE_PROP_UINT8("prog_if",  PCISerialState, prog_if, 0x02),
    DEFINE_PROP_END_OF_LIST(),
};

static Property multi_2x_serial_pci_properties[] = {
    DEFINE_PROP_CHR("chardev1",  PCIMultiSerialState, state[0].chr),
    DEFINE_PROP_CHR("chardev2",  PCIMultiSerialState, state[1].chr),
    DEFINE_PROP_UINT8("prog_if",  PCIMultiSerialState, prog_if, 0x02),
    DEFINE_PROP_END_OF_LIST(),
};

static Property multi_4x_serial_pci_properties[] = {
    DEFINE_PROP_CHR("chardev1",  PCIMultiSerialState, state[0].chr),
    DEFINE_PROP_CHR("chardev2",  PCIMultiSerialState, state[1].chr),
    DEFINE_PROP_CHR("chardev3",  PCIMultiSerialState, state[2].chr),
    DEFINE_PROP_CHR("chardev4",  PCIMultiSerialState, state[3].chr),
    DEFINE_PROP_UINT8("prog_if",  PCIMultiSerialState, prog_if, 0x02),
    DEFINE_PROP_END_OF_LIST(),
};

static void serial_pci_class_initfn(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass);
    pc->init = serial_pci_init;
    pc->exit = serial_pci_exit;
    pc->vendor_id = PCI_VENDOR_ID_REDHAT;
    pc->device_id = PCI_DEVICE_ID_REDHAT_SERIAL;
    pc->revision = 1;
    pc->class_id = PCI_CLASS_COMMUNICATION_SERIAL;
    dc->vmsd = &vmstate_pci_serial;
    dc->props = serial_pci_properties;
    set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
}

static void multi_2x_serial_pci_class_initfn(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass);
    pc->init = multi_serial_pci_init;
    pc->exit = multi_serial_pci_exit;
    pc->vendor_id = PCI_VENDOR_ID_REDHAT;
    pc->device_id = PCI_DEVICE_ID_REDHAT_SERIAL2;
    pc->revision = 1;
    pc->class_id = PCI_CLASS_COMMUNICATION_SERIAL;
    dc->vmsd = &vmstate_pci_multi_serial;
    dc->props = multi_2x_serial_pci_properties;
    set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
}

static void multi_4x_serial_pci_class_initfn(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass);
    pc->init = multi_serial_pci_init;
    pc->exit = multi_serial_pci_exit;
    pc->vendor_id = PCI_VENDOR_ID_REDHAT;
    pc->device_id = PCI_DEVICE_ID_REDHAT_SERIAL4;
    pc->revision = 1;
    pc->class_id = PCI_CLASS_COMMUNICATION_SERIAL;
    dc->vmsd = &vmstate_pci_multi_serial;
    dc->props = multi_4x_serial_pci_properties;
    set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
}

static const TypeInfo serial_pci_info = {
    .name          = "pci-serial",
    .parent        = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCISerialState),
    .class_init    = serial_pci_class_initfn,
};

static const TypeInfo multi_2x_serial_pci_info = {
    .name          = "pci-serial-2x",
    .parent        = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCIMultiSerialState),
    .class_init    = multi_2x_serial_pci_class_initfn,
};

static const TypeInfo multi_4x_serial_pci_info = {
    .name          = "pci-serial-4x",
    .parent        = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCIMultiSerialState),
    .class_init    = multi_4x_serial_pci_class_initfn,
};

static void serial_pci_register_types(void)
{
    type_register_static(&serial_pci_info);
    type_register_static(&multi_2x_serial_pci_info);
    type_register_static(&multi_4x_serial_pci_info);
}

type_init(serial_pci_register_types)
Commit	Line	Data
419ad672 GH	1	/*
	2	* QEMU 16550A UART emulation
	3	*
	4	* Copyright (c) 2003-2004 Fabrice Bellard
	5	* Copyright (c) 2008 Citrix Systems, Inc.
	6	*
	7	* Permission is hereby granted, free of charge, to any person obtaining a copy
	8	* of this software and associated documentation files (the "Software"), to deal
	9	* in the Software without restriction, including without limitation the rights
	10	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	11	* copies of the Software, and to permit persons to whom the Software is
	12	* furnished to do so, subject to the following conditions:
	13	*
	14	* The above copyright notice and this permission notice shall be included in
	15	* all copies or substantial portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	22	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	23	* THE SOFTWARE.
	24	*/
	25
90734e02 GH	26	/* see docs/specs/pci-serial.txt */
90734e02 GH	27
0d09e41a	28	#include "hw/char/serial.h"
83c9f4ca	29	#include "hw/pci/pci.h"
db895a1e	30	#include "qapi/qmp/qerror.h"
419ad672	31
d66bbea4 GH	32	#define PCI_SERIAL_MAX_PORTS 4
d66bbea4 GH	33
419ad672 GH	34	typedef struct PCISerialState {
	35	PCIDevice dev;
	36	SerialState state;
13cc2c3e	37	uint8_t prog_if;
419ad672 GH	38	} PCISerialState;
419ad672 GH	39
d66bbea4 GH	40	typedef struct PCIMultiSerialState {
	41	PCIDevice dev;
	42	MemoryRegion iobar;
	43	uint32_t ports;
	44	char *name[PCI_SERIAL_MAX_PORTS];
	45	SerialState state[PCI_SERIAL_MAX_PORTS];
	46	uint32_t level[PCI_SERIAL_MAX_PORTS];
	47	qemu_irq *irqs;
13cc2c3e	48	uint8_t prog_if;
d66bbea4 GH	49	} PCIMultiSerialState;
d66bbea4 GH	50
419ad672 GH	51	static int serial_pci_init(PCIDevice *dev)
	52	{
	53	PCISerialState *pci = DO_UPCAST(PCISerialState, dev, dev);
	54	SerialState *s = &pci->state;
db895a1e	55	Error *err = NULL;
419ad672 GH	56
419ad672 GH	57	s->baudbase = 115200;
db895a1e AF	58	serial_realize_core(s, &err);
	59	if (err != NULL) {
	60	qerror_report_err(err);
	61	error_free(err);
	62	return -1;
	63	}
419ad672	64
13cc2c3e	65	pci->dev.config[PCI_CLASS_PROG] = pci->prog_if;
419ad672	66	pci->dev.config[PCI_INTERRUPT_PIN] = 0x01;
9e64f8a3	67	s->irq = pci_allocate_irq(&pci->dev);
419ad672	68
300b1fc6	69	memory_region_init_io(&s->io, OBJECT(pci), &serial_io_ops, s, "serial", 8);
419ad672 GH	70	pci_register_bar(&pci->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io);
	71	return 0;
	72	}
	73
d66bbea4 GH	74	static void multi_serial_irq_mux(void *opaque, int n, int level)
	75	{
	76	PCIMultiSerialState *pci = opaque;
	77	int i, pending = 0;
	78
	79	pci->level[n] = level;
	80	for (i = 0; i < pci->ports; i++) {
	81	if (pci->level[i]) {
	82	pending = 1;
	83	}
	84	}
9e64f8a3	85	pci_set_irq(&pci->dev, pending);
d66bbea4 GH	86	}
	87
	88	static int multi_serial_pci_init(PCIDevice *dev)
	89	{
	90	PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
	91	PCIMultiSerialState *pci = DO_UPCAST(PCIMultiSerialState, dev, dev);
	92	SerialState *s;
db895a1e	93	Error *err = NULL;
d66bbea4 GH	94	int i;
	95
	96	switch (pc->device_id) {
	97	case 0x0003:
	98	pci->ports = 2;
	99	break;
	100	case 0x0004:
	101	pci->ports = 4;
	102	break;
	103	}
	104	assert(pci->ports > 0);
	105	assert(pci->ports <= PCI_SERIAL_MAX_PORTS);
	106
13cc2c3e	107	pci->dev.config[PCI_CLASS_PROG] = pci->prog_if;
d66bbea4	108	pci->dev.config[PCI_INTERRUPT_PIN] = 0x01;
300b1fc6	109	memory_region_init(&pci->iobar, OBJECT(pci), "multiserial", 8 * pci->ports);
d66bbea4 GH	110	pci_register_bar(&pci->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &pci->iobar);
	111	pci->irqs = qemu_allocate_irqs(multi_serial_irq_mux, pci,
	112	pci->ports);
	113
	114	for (i = 0; i < pci->ports; i++) {
	115	s = pci->state + i;
	116	s->baudbase = 115200;
db895a1e AF	117	serial_realize_core(s, &err);
	118	if (err != NULL) {
	119	qerror_report_err(err);
	120	error_free(err);
	121	return -1;
	122	}
d66bbea4 GH	123	s->irq = pci->irqs[i];
d66bbea4 GH	124	pci->name[i] = g_strdup_printf("uart #%d", i+1);
300b1fc6 PB	125	memory_region_init_io(&s->io, OBJECT(pci), &serial_io_ops, s,
300b1fc6 PB	126	pci->name[i], 8);
d66bbea4 GH	127	memory_region_add_subregion(&pci->iobar, 8 * i, &s->io);
	128	}
	129	return 0;
	130	}
	131
419ad672 GH	132	static void serial_pci_exit(PCIDevice *dev)
	133	{
	134	PCISerialState *pci = DO_UPCAST(PCISerialState, dev, dev);
	135	SerialState *s = &pci->state;
	136
	137	serial_exit_core(s);
	138	memory_region_destroy(&s->io);
9e64f8a3	139	qemu_free_irq(s->irq);
419ad672 GH	140	}
419ad672 GH	141
d66bbea4 GH	142	static void multi_serial_pci_exit(PCIDevice *dev)
	143	{
	144	PCIMultiSerialState *pci = DO_UPCAST(PCIMultiSerialState, dev, dev);
	145	SerialState *s;
	146	int i;
	147
	148	for (i = 0; i < pci->ports; i++) {
	149	s = pci->state + i;
	150	serial_exit_core(s);
7497bce6	151	memory_region_del_subregion(&pci->iobar, &s->io);
d66bbea4 GH	152	memory_region_destroy(&s->io);
	153	g_free(pci->name[i]);
	154	}
	155	memory_region_destroy(&pci->iobar);
f173d57a	156	qemu_free_irqs(pci->irqs, pci->ports);
d66bbea4 GH	157	}
d66bbea4 GH	158
419ad672 GH	159	static const VMStateDescription vmstate_pci_serial = {
	160	.name = "pci-serial",
	161	.version_id = 1,
	162	.minimum_version_id = 1,
d49805ae	163	.fields = (VMStateField[]) {
419ad672 GH	164	VMSTATE_PCI_DEVICE(dev, PCISerialState),
	165	VMSTATE_STRUCT(state, PCISerialState, 0, vmstate_serial, SerialState),
	166	VMSTATE_END_OF_LIST()
	167	}
	168	};
	169
d66bbea4 GH	170	static const VMStateDescription vmstate_pci_multi_serial = {
	171	.name = "pci-serial-multi",
	172	.version_id = 1,
	173	.minimum_version_id = 1,
d49805ae	174	.fields = (VMStateField[]) {
d66bbea4 GH	175	VMSTATE_PCI_DEVICE(dev, PCIMultiSerialState),
	176	VMSTATE_STRUCT_ARRAY(state, PCIMultiSerialState, PCI_SERIAL_MAX_PORTS,
	177	0, vmstate_serial, SerialState),
	178	VMSTATE_UINT32_ARRAY(level, PCIMultiSerialState, PCI_SERIAL_MAX_PORTS),
	179	VMSTATE_END_OF_LIST()
	180	}
	181	};
	182
419ad672 GH	183	static Property serial_pci_properties[] = {
419ad672 GH	184	DEFINE_PROP_CHR("chardev", PCISerialState, state.chr),
13cc2c3e	185	DEFINE_PROP_UINT8("prog_if", PCISerialState, prog_if, 0x02),
419ad672 GH	186	DEFINE_PROP_END_OF_LIST(),
	187	};
	188
d66bbea4 GH	189	static Property multi_2x_serial_pci_properties[] = {
	190	DEFINE_PROP_CHR("chardev1", PCIMultiSerialState, state[0].chr),
	191	DEFINE_PROP_CHR("chardev2", PCIMultiSerialState, state[1].chr),
13cc2c3e	192	DEFINE_PROP_UINT8("prog_if", PCIMultiSerialState, prog_if, 0x02),
d66bbea4 GH	193	DEFINE_PROP_END_OF_LIST(),
	194	};
	195
	196	static Property multi_4x_serial_pci_properties[] = {
	197	DEFINE_PROP_CHR("chardev1", PCIMultiSerialState, state[0].chr),
	198	DEFINE_PROP_CHR("chardev2", PCIMultiSerialState, state[1].chr),
	199	DEFINE_PROP_CHR("chardev3", PCIMultiSerialState, state[2].chr),
	200	DEFINE_PROP_CHR("chardev4", PCIMultiSerialState, state[3].chr),
13cc2c3e	201	DEFINE_PROP_UINT8("prog_if", PCIMultiSerialState, prog_if, 0x02),
d66bbea4 GH	202	DEFINE_PROP_END_OF_LIST(),
	203	};
	204
419ad672 GH	205	static void serial_pci_class_initfn(ObjectClass klass, void data)
	206	{
	207	DeviceClass *dc = DEVICE_CLASS(klass);
	208	PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass);
	209	pc->init = serial_pci_init;
	210	pc->exit = serial_pci_exit;
5c03a254 PB	211	pc->vendor_id = PCI_VENDOR_ID_REDHAT;
5c03a254 PB	212	pc->device_id = PCI_DEVICE_ID_REDHAT_SERIAL;
419ad672 GH	213	pc->revision = 1;
	214	pc->class_id = PCI_CLASS_COMMUNICATION_SERIAL;
	215	dc->vmsd = &vmstate_pci_serial;
	216	dc->props = serial_pci_properties;
125ee0ed	217	set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
419ad672 GH	218	}
419ad672 GH	219
d66bbea4 GH	220	static void multi_2x_serial_pci_class_initfn(ObjectClass klass, void data)
	221	{
	222	DeviceClass *dc = DEVICE_CLASS(klass);
	223	PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass);
	224	pc->init = multi_serial_pci_init;
	225	pc->exit = multi_serial_pci_exit;
5c03a254 PB	226	pc->vendor_id = PCI_VENDOR_ID_REDHAT;
5c03a254 PB	227	pc->device_id = PCI_DEVICE_ID_REDHAT_SERIAL2;
d66bbea4 GH	228	pc->revision = 1;
	229	pc->class_id = PCI_CLASS_COMMUNICATION_SERIAL;
	230	dc->vmsd = &vmstate_pci_multi_serial;
	231	dc->props = multi_2x_serial_pci_properties;
125ee0ed	232	set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
d66bbea4 GH	233	}
	234
	235	static void multi_4x_serial_pci_class_initfn(ObjectClass klass, void data)
	236	{
	237	DeviceClass *dc = DEVICE_CLASS(klass);
	238	PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass);
	239	pc->init = multi_serial_pci_init;
	240	pc->exit = multi_serial_pci_exit;
5c03a254 PB	241	pc->vendor_id = PCI_VENDOR_ID_REDHAT;
5c03a254 PB	242	pc->device_id = PCI_DEVICE_ID_REDHAT_SERIAL4;
d66bbea4 GH	243	pc->revision = 1;
	244	pc->class_id = PCI_CLASS_COMMUNICATION_SERIAL;
	245	dc->vmsd = &vmstate_pci_multi_serial;
	246	dc->props = multi_4x_serial_pci_properties;
125ee0ed	247	set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
d66bbea4 GH	248	}
d66bbea4 GH	249
8c43a6f0	250	static const TypeInfo serial_pci_info = {
419ad672 GH	251	.name = "pci-serial",
	252	.parent = TYPE_PCI_DEVICE,
	253	.instance_size = sizeof(PCISerialState),
	254	.class_init = serial_pci_class_initfn,
	255	};
	256
8c43a6f0	257	static const TypeInfo multi_2x_serial_pci_info = {
d66bbea4 GH	258	.name = "pci-serial-2x",
	259	.parent = TYPE_PCI_DEVICE,
	260	.instance_size = sizeof(PCIMultiSerialState),
	261	.class_init = multi_2x_serial_pci_class_initfn,
	262	};
	263
8c43a6f0	264	static const TypeInfo multi_4x_serial_pci_info = {
d66bbea4 GH	265	.name = "pci-serial-4x",
	266	.parent = TYPE_PCI_DEVICE,
	267	.instance_size = sizeof(PCIMultiSerialState),
	268	.class_init = multi_4x_serial_pci_class_initfn,
	269	};
	270
419ad672 GH	271	static void serial_pci_register_types(void)
	272	{
	273	type_register_static(&serial_pci_info);
d66bbea4 GH	274	type_register_static(&multi_2x_serial_pci_info);
d66bbea4 GH	275	type_register_static(&multi_4x_serial_pci_info);
419ad672 GH	276	}
	277
	278	type_init(serial_pci_register_types)