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12f42174 DG |
1 | /* |
2 | * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator | |
3 | * | |
4 | * RTAS Real Time Clock | |
5 | * | |
6 | * Copyright (c) 2010-2011 David Gibson, IBM Corporation. | |
7 | * Copyright 2014 David Gibson, Red Hat. | |
8 | * | |
9 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
10 | * of this software and associated documentation files (the "Software"), to deal | |
11 | * in the Software without restriction, including without limitation the rights | |
12 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
13 | * copies of the Software, and to permit persons to whom the Software is | |
14 | * furnished to do so, subject to the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice shall be included in | |
17 | * all copies or substantial portions of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
20 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
21 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
22 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
23 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
24 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
25 | * THE SOFTWARE. | |
12f42174 | 26 | */ |
e688df6b | 27 | |
0d75590d | 28 | #include "qemu/osdep.h" |
12f42174 | 29 | #include "cpu.h" |
e0cf11f3 | 30 | #include "qemu/timer.h" |
f01c5d84 | 31 | #include "sysemu/sysemu.h" |
12f42174 | 32 | #include "hw/ppc/spapr.h" |
e688df6b | 33 | #include "qapi/error.h" |
112ed241 | 34 | #include "qapi/qapi-events-misc.h" |
f348b6d1 | 35 | #include "qemu/cutils.h" |
12f42174 | 36 | |
147ff807 | 37 | void spapr_rtc_read(sPAPRRTCState *rtc, struct tm *tm, uint32_t *ns) |
e5dad1d7 | 38 | { |
f01c5d84 | 39 | int64_t host_ns = qemu_clock_get_ns(rtc_clock); |
880ae7de | 40 | int64_t guest_ns; |
f01c5d84 DG |
41 | time_t guest_s; |
42 | ||
28df36a1 DG |
43 | assert(rtc); |
44 | ||
880ae7de | 45 | guest_ns = host_ns + rtc->ns_offset; |
13566fe3 | 46 | guest_s = guest_ns / NANOSECONDS_PER_SECOND; |
f01c5d84 DG |
47 | |
48 | if (tm) { | |
49 | gmtime_r(&guest_s, tm); | |
50 | } | |
e5dad1d7 | 51 | if (ns) { |
880ae7de | 52 | *ns = guest_ns; |
e5dad1d7 DG |
53 | } |
54 | } | |
55 | ||
147ff807 | 56 | int spapr_rtc_import_offset(sPAPRRTCState *rtc, int64_t legacy_offset) |
880ae7de | 57 | { |
147ff807 | 58 | if (!rtc) { |
880ae7de DG |
59 | return -ENODEV; |
60 | } | |
61 | ||
13566fe3 | 62 | rtc->ns_offset = legacy_offset * NANOSECONDS_PER_SECOND; |
880ae7de DG |
63 | |
64 | return 0; | |
65 | } | |
66 | ||
28e02042 | 67 | static void rtas_get_time_of_day(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
12f42174 DG |
68 | uint32_t token, uint32_t nargs, |
69 | target_ulong args, | |
70 | uint32_t nret, target_ulong rets) | |
71 | { | |
72 | struct tm tm; | |
e5dad1d7 | 73 | uint32_t ns; |
12f42174 | 74 | |
bbade206 | 75 | if ((nargs != 0) || (nret != 8)) { |
12f42174 DG |
76 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
77 | return; | |
78 | } | |
79 | ||
147ff807 | 80 | spapr_rtc_read(&spapr->rtc, &tm, &ns); |
12f42174 DG |
81 | |
82 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); | |
83 | rtas_st(rets, 1, tm.tm_year + 1900); | |
84 | rtas_st(rets, 2, tm.tm_mon + 1); | |
85 | rtas_st(rets, 3, tm.tm_mday); | |
86 | rtas_st(rets, 4, tm.tm_hour); | |
87 | rtas_st(rets, 5, tm.tm_min); | |
88 | rtas_st(rets, 6, tm.tm_sec); | |
e5dad1d7 | 89 | rtas_st(rets, 7, ns); |
12f42174 DG |
90 | } |
91 | ||
28e02042 | 92 | static void rtas_set_time_of_day(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
12f42174 DG |
93 | uint32_t token, uint32_t nargs, |
94 | target_ulong args, | |
95 | uint32_t nret, target_ulong rets) | |
96 | { | |
147ff807 | 97 | sPAPRRTCState *rtc = &spapr->rtc; |
12f42174 | 98 | struct tm tm; |
f01c5d84 DG |
99 | time_t new_s; |
100 | int64_t host_ns; | |
12f42174 | 101 | |
bbade206 DG |
102 | if ((nargs != 7) || (nret != 1)) { |
103 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
104 | return; | |
105 | } | |
106 | ||
12f42174 DG |
107 | tm.tm_year = rtas_ld(args, 0) - 1900; |
108 | tm.tm_mon = rtas_ld(args, 1) - 1; | |
109 | tm.tm_mday = rtas_ld(args, 2); | |
110 | tm.tm_hour = rtas_ld(args, 3); | |
111 | tm.tm_min = rtas_ld(args, 4); | |
112 | tm.tm_sec = rtas_ld(args, 5); | |
113 | ||
f01c5d84 DG |
114 | new_s = mktimegm(&tm); |
115 | if (new_s == -1) { | |
116 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); | |
117 | return; | |
118 | } | |
119 | ||
120 | /* Generate a monitor event for the change */ | |
12f42174 | 121 | qapi_event_send_rtc_change(qemu_timedate_diff(&tm), &error_abort); |
f01c5d84 DG |
122 | |
123 | host_ns = qemu_clock_get_ns(rtc_clock); | |
124 | ||
13566fe3 | 125 | rtc->ns_offset = (new_s * NANOSECONDS_PER_SECOND) - host_ns; |
12f42174 DG |
126 | |
127 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); | |
128 | } | |
129 | ||
74e5ae28 DG |
130 | static void spapr_rtc_qom_date(Object *obj, struct tm *current_tm, Error **errp) |
131 | { | |
147ff807 | 132 | spapr_rtc_read(SPAPR_RTC(obj), current_tm, NULL); |
74e5ae28 DG |
133 | } |
134 | ||
28df36a1 | 135 | static void spapr_rtc_realize(DeviceState *dev, Error **errp) |
12f42174 | 136 | { |
880ae7de | 137 | sPAPRRTCState *rtc = SPAPR_RTC(dev); |
f01c5d84 DG |
138 | struct tm tm; |
139 | time_t host_s; | |
140 | int64_t rtc_ns; | |
141 | ||
142 | /* Initialize the RTAS RTC from host time */ | |
143 | ||
144 | qemu_get_timedate(&tm, 0); | |
145 | host_s = mktimegm(&tm); | |
146 | rtc_ns = qemu_clock_get_ns(rtc_clock); | |
13566fe3 | 147 | rtc->ns_offset = host_s * NANOSECONDS_PER_SECOND - rtc_ns; |
74e5ae28 DG |
148 | |
149 | object_property_add_tm(OBJECT(rtc), "date", spapr_rtc_qom_date, NULL); | |
28df36a1 DG |
150 | } |
151 | ||
880ae7de DG |
152 | static const VMStateDescription vmstate_spapr_rtc = { |
153 | .name = "spapr/rtc", | |
154 | .version_id = 1, | |
155 | .minimum_version_id = 1, | |
156 | .fields = (VMStateField[]) { | |
157 | VMSTATE_INT64(ns_offset, sPAPRRTCState), | |
158 | VMSTATE_END_OF_LIST() | |
159 | }, | |
160 | }; | |
161 | ||
28df36a1 DG |
162 | static void spapr_rtc_class_init(ObjectClass *oc, void *data) |
163 | { | |
164 | DeviceClass *dc = DEVICE_CLASS(oc); | |
165 | ||
166 | dc->realize = spapr_rtc_realize; | |
880ae7de | 167 | dc->vmsd = &vmstate_spapr_rtc; |
8ccccff9 TH |
168 | /* Reason: This is an internal device only for handling the hypercalls */ |
169 | dc->user_creatable = false; | |
f01c5d84 | 170 | |
12f42174 DG |
171 | spapr_rtas_register(RTAS_GET_TIME_OF_DAY, "get-time-of-day", |
172 | rtas_get_time_of_day); | |
173 | spapr_rtas_register(RTAS_SET_TIME_OF_DAY, "set-time-of-day", | |
174 | rtas_set_time_of_day); | |
175 | } | |
28df36a1 DG |
176 | |
177 | static const TypeInfo spapr_rtc_info = { | |
178 | .name = TYPE_SPAPR_RTC, | |
147ff807 | 179 | .parent = TYPE_DEVICE, |
28df36a1 | 180 | .instance_size = sizeof(sPAPRRTCState), |
28df36a1 DG |
181 | .class_init = spapr_rtc_class_init, |
182 | }; | |
183 | ||
184 | static void spapr_rtc_register_types(void) | |
185 | { | |
186 | type_register_static(&spapr_rtc_info); | |
187 | } | |
188 | type_init(spapr_rtc_register_types) |