[qemu.git] / hw / char / stm32f2xx_usart.c

/*
 * STM32F2XX USART
 *
 * Copyright (c) 2014 Alistair Francis <[email protected]>
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "hw/char/stm32f2xx_usart.h"

#ifndef STM_USART_ERR_DEBUG
#define STM_USART_ERR_DEBUG 0
#endif

#define DB_PRINT_L(lvl, fmt, args...) do { \
    if (STM_USART_ERR_DEBUG >= lvl) { \
        qemu_log("%s: " fmt, __func__, ## args); \
    } \
} while (0);

#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)

static int stm32f2xx_usart_can_receive(void *opaque)
{
    STM32F2XXUsartState *s = opaque;

    if (!(s->usart_sr & USART_SR_RXNE)) {
        return 1;
    }

    return 0;
}

static void stm32f2xx_usart_receive(void *opaque, const uint8_t *buf, int size)
{
    STM32F2XXUsartState *s = opaque;

    s->usart_dr = *buf;

    if (!(s->usart_cr1 & USART_CR1_UE && s->usart_cr1 & USART_CR1_RE)) {
        /* USART not enabled - drop the chars */
        DB_PRINT("Dropping the chars\n");
        return;
    }

    s->usart_sr |= USART_SR_RXNE;

    if (s->usart_cr1 & USART_CR1_RXNEIE) {
        qemu_set_irq(s->irq, 1);
    }

    DB_PRINT("Receiving: %c\n", s->usart_dr);
}

static void stm32f2xx_usart_reset(DeviceState *dev)
{
    STM32F2XXUsartState *s = STM32F2XX_USART(dev);

    s->usart_sr = USART_SR_RESET;
    s->usart_dr = 0x00000000;
    s->usart_brr = 0x00000000;
    s->usart_cr1 = 0x00000000;
    s->usart_cr2 = 0x00000000;
    s->usart_cr3 = 0x00000000;
    s->usart_gtpr = 0x00000000;

    qemu_set_irq(s->irq, 0);
}

static uint64_t stm32f2xx_usart_read(void *opaque, hwaddr addr,
                                       unsigned int size)
{
    STM32F2XXUsartState *s = opaque;
    uint64_t retvalue;

    DB_PRINT("Read 0x%"HWADDR_PRIx"\n", addr);

    switch (addr) {
    case USART_SR:
        retvalue = s->usart_sr;
        s->usart_sr &= ~USART_SR_TC;
        if (s->chr) {
            qemu_chr_accept_input(s->chr);
        }
        return retvalue;
    case USART_DR:
        DB_PRINT("Value: 0x%" PRIx32 ", %c\n", s->usart_dr, (char) s->usart_dr);
        s->usart_sr |= USART_SR_TXE;
        s->usart_sr &= ~USART_SR_RXNE;
        if (s->chr) {
            qemu_chr_accept_input(s->chr);
        }
        qemu_set_irq(s->irq, 0);
        return s->usart_dr & 0x3FF;
    case USART_BRR:
        return s->usart_brr;
    case USART_CR1:
        return s->usart_cr1;
    case USART_CR2:
        return s->usart_cr2;
    case USART_CR3:
        return s->usart_cr3;
    case USART_GTPR:
        return s->usart_gtpr;
    default:
        qemu_log_mask(LOG_GUEST_ERROR,
                      "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
        return 0;
    }

    return 0;
}

static void stm32f2xx_usart_write(void *opaque, hwaddr addr,
                                  uint64_t val64, unsigned int size)
{
    STM32F2XXUsartState *s = opaque;
    uint32_t value = val64;
    unsigned char ch;

    DB_PRINT("Write 0x%" PRIx32 ", 0x%"HWADDR_PRIx"\n", value, addr);

    switch (addr) {
    case USART_SR:
        if (value <= 0x3FF) {
            s->usart_sr = value;
        } else {
            s->usart_sr &= value;
        }
        if (!(s->usart_sr & USART_SR_RXNE)) {
            qemu_set_irq(s->irq, 0);
        }
        return;
    case USART_DR:
        if (value < 0xF000) {
            ch = value;
            if (s->chr) {
                qemu_chr_fe_write_all(s->chr, &ch, 1);
            }
            s->usart_sr |= USART_SR_TC;
            s->usart_sr &= ~USART_SR_TXE;
        }
        return;
    case USART_BRR:
        s->usart_brr = value;
        return;
    case USART_CR1:
        s->usart_cr1 = value;
            if (s->usart_cr1 & USART_CR1_RXNEIE &&
                s->usart_sr & USART_SR_RXNE) {
                qemu_set_irq(s->irq, 1);
            }
        return;
    case USART_CR2:
        s->usart_cr2 = value;
        return;
    case USART_CR3:
        s->usart_cr3 = value;
        return;
    case USART_GTPR:
        s->usart_gtpr = value;
        return;
    default:
        qemu_log_mask(LOG_GUEST_ERROR,
                      "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
    }
}

static const MemoryRegionOps stm32f2xx_usart_ops = {
    .read = stm32f2xx_usart_read,
    .write = stm32f2xx_usart_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static void stm32f2xx_usart_init(Object *obj)
{
    STM32F2XXUsartState *s = STM32F2XX_USART(obj);

    sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);

    memory_region_init_io(&s->mmio, obj, &stm32f2xx_usart_ops, s,
                          TYPE_STM32F2XX_USART, 0x2000);
    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);

    /* FIXME use a qdev chardev prop instead of qemu_char_get_next_serial() */
    s->chr = qemu_char_get_next_serial();

    if (s->chr) {
        qemu_chr_add_handlers(s->chr, stm32f2xx_usart_can_receive,
                              stm32f2xx_usart_receive, NULL, s);
    }
}

static void stm32f2xx_usart_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->reset = stm32f2xx_usart_reset;
    /* Reason: instance_init() method uses qemu_char_get_next_serial() */
    dc->cannot_instantiate_with_device_add_yet = true;
}

static const TypeInfo stm32f2xx_usart_info = {
    .name          = TYPE_STM32F2XX_USART,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(STM32F2XXUsartState),
    .instance_init = stm32f2xx_usart_init,
    .class_init    = stm32f2xx_usart_class_init,
};

static void stm32f2xx_usart_register_types(void)
{
    type_register_static(&stm32f2xx_usart_info);
}

type_init(stm32f2xx_usart_register_types)
Commit	Line	Data
73af5d11 AF	1	/*
	2	* STM32F2XX USART
	3	*
	4	* Copyright (c) 2014 Alistair Francis <[email protected]>
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24
	25	#include "hw/char/stm32f2xx_usart.h"
	26
	27	#ifndef STM_USART_ERR_DEBUG
	28	#define STM_USART_ERR_DEBUG 0
	29	#endif
	30
	31	#define DB_PRINT_L(lvl, fmt, args...) do { \
	32	if (STM_USART_ERR_DEBUG >= lvl) { \
	33	qemu_log("%s: " fmt, __func__, ## args); \
	34	} \
	35	} while (0);
	36
	37	#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
	38
	39	static int stm32f2xx_usart_can_receive(void *opaque)
	40	{
	41	STM32F2XXUsartState *s = opaque;
	42
	43	if (!(s->usart_sr & USART_SR_RXNE)) {
	44	return 1;
	45	}
	46
	47	return 0;
	48	}
	49
	50	static void stm32f2xx_usart_receive(void opaque, const uint8_t buf, int size)
	51	{
	52	STM32F2XXUsartState *s = opaque;
	53
	54	s->usart_dr = *buf;
	55
	56	if (!(s->usart_cr1 & USART_CR1_UE && s->usart_cr1 & USART_CR1_RE)) {
	57	/* USART not enabled - drop the chars */
	58	DB_PRINT("Dropping the chars\n");
	59	return;
	60	}
	61
	62	s->usart_sr \|= USART_SR_RXNE;
	63
	64	if (s->usart_cr1 & USART_CR1_RXNEIE) {
65	qemu_set_irq(s->irq, 1);
66	}
67
68	DB_PRINT("Receiving: %c\n", s->usart_dr);
69	}
70
71	static void stm32f2xx_usart_reset(DeviceState *dev)
72	{
73	STM32F2XXUsartState *s = STM32F2XX_USART(dev);
74
75	s->usart_sr = USART_SR_RESET;
76	s->usart_dr = 0x00000000;
77	s->usart_brr = 0x00000000;
78	s->usart_cr1 = 0x00000000;
79	s->usart_cr2 = 0x00000000;
80	s->usart_cr3 = 0x00000000;
81	s->usart_gtpr = 0x00000000;
82
83	qemu_set_irq(s->irq, 0);
84	}
85
86	static uint64_t stm32f2xx_usart_read(void *opaque, hwaddr addr,
87	unsigned int size)
88	{
89	STM32F2XXUsartState *s = opaque;
90	uint64_t retvalue;
91
92	DB_PRINT("Read 0x%"HWADDR_PRIx"\n", addr);
93
94	switch (addr) {
95	case USART_SR:
96	retvalue = s->usart_sr;
97	s->usart_sr &= ~USART_SR_TC;
98	if (s->chr) {
99	qemu_chr_accept_input(s->chr);
100	}
101	return retvalue;
102	case USART_DR:
103	DB_PRINT("Value: 0x%" PRIx32 ", %c\n", s->usart_dr, (char) s->usart_dr);
104	s->usart_sr \|= USART_SR_TXE;
105	s->usart_sr &= ~USART_SR_RXNE;
106	if (s->chr) {
107	qemu_chr_accept_input(s->chr);
108	}
109	qemu_set_irq(s->irq, 0);
110	return s->usart_dr & 0x3FF;
111	case USART_BRR:
112	return s->usart_brr;
113	case USART_CR1:
114	return s->usart_cr1;
115	case USART_CR2:
116	return s->usart_cr2;
117	case USART_CR3:
118	return s->usart_cr3;
119	case USART_GTPR:
120	return s->usart_gtpr;
121	default:
122	qemu_log_mask(LOG_GUEST_ERROR,
123	"%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
124	return 0;
125	}
126
127	return 0;
128	}
129
130	static void stm32f2xx_usart_write(void *opaque, hwaddr addr,
131	uint64_t val64, unsigned int size)
132	{
133	STM32F2XXUsartState *s = opaque;
134	uint32_t value = val64;
135	unsigned char ch;
136
137	DB_PRINT("Write 0x%" PRIx32 ", 0x%"HWADDR_PRIx"\n", value, addr);
138
139	switch (addr) {
140	case USART_SR:
141	if (value <= 0x3FF) {
142	s->usart_sr = value;
143	} else {
144	s->usart_sr &= value;
145	}
146	if (!(s->usart_sr & USART_SR_RXNE)) {
147	qemu_set_irq(s->irq, 0);
148	}
149	return;
150	case USART_DR:
151	if (value < 0xF000) {
152	ch = value;
153	if (s->chr) {
154	qemu_chr_fe_write_all(s->chr, &ch, 1);
155	}
156	s->usart_sr \|= USART_SR_TC;
157	s->usart_sr &= ~USART_SR_TXE;
158	}
159	return;
160	case USART_BRR:
161	s->usart_brr = value;
162	return;
163	case USART_CR1:
164	s->usart_cr1 = value;
165	if (s->usart_cr1 & USART_CR1_RXNEIE &&
166	s->usart_sr & USART_SR_RXNE) {
167	qemu_set_irq(s->irq, 1);
168	}
169	return;
170	case USART_CR2:
171	s->usart_cr2 = value;
172	return;
173	case USART_CR3:
174	s->usart_cr3 = value;
175	return;
176	case USART_GTPR:
177	s->usart_gtpr = value;
178	return;
179	default:
180	qemu_log_mask(LOG_GUEST_ERROR,
181	"%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
182	}
183	}
184
185	static const MemoryRegionOps stm32f2xx_usart_ops = {
186	.read = stm32f2xx_usart_read,
187	.write = stm32f2xx_usart_write,
188	.endianness = DEVICE_NATIVE_ENDIAN,
189	};
190
191	static void stm32f2xx_usart_init(Object *obj)
192	{
193	STM32F2XXUsartState *s = STM32F2XX_USART(obj);
194
195	sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
196
197	memory_region_init_io(&s->mmio, obj, &stm32f2xx_usart_ops, s,
198	TYPE_STM32F2XX_USART, 0x2000);
199	sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
200
d71b22bb	201	/* FIXME use a qdev chardev prop instead of qemu_char_get_next_serial() */
73af5d11 AF	202	s->chr = qemu_char_get_next_serial();
	203
	204	if (s->chr) {
	205	qemu_chr_add_handlers(s->chr, stm32f2xx_usart_can_receive,
	206	stm32f2xx_usart_receive, NULL, s);
	207	}
	208	}
	209
	210	static void stm32f2xx_usart_class_init(ObjectClass klass, void data)
	211	{
	212	DeviceClass *dc = DEVICE_CLASS(klass);
	213
	214	dc->reset = stm32f2xx_usart_reset;
9f9bdf43 MA	215	/* Reason: instance_init() method uses qemu_char_get_next_serial() */
9f9bdf43 MA	216	dc->cannot_instantiate_with_device_add_yet = true;
73af5d11 AF	217	}
	218
	219	static const TypeInfo stm32f2xx_usart_info = {
	220	.name = TYPE_STM32F2XX_USART,
	221	.parent = TYPE_SYS_BUS_DEVICE,
	222	.instance_size = sizeof(STM32F2XXUsartState),
	223	.instance_init = stm32f2xx_usart_init,
	224	.class_init = stm32f2xx_usart_class_init,
	225	};
	226
	227	static void stm32f2xx_usart_register_types(void)
	228	{
	229	type_register_static(&stm32f2xx_usart_info);
	230	}
	231
	232	type_init(stm32f2xx_usart_register_types)