[qemu.git] / hw / char / serial-pci.c

/*
 * QEMU 16550A UART emulation
 *
 * Copyright (c) 2003-2004 Fabrice Bellard
 * Copyright (c) 2008 Citrix Systems, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

/* see docs/specs/pci-serial.txt */

#include "hw/char/serial.h"
#include "hw/pci/pci.h"

#define PCI_SERIAL_MAX_PORTS 4

typedef struct PCISerialState {
    PCIDevice dev;
    SerialState state;
    uint8_t prog_if;
} PCISerialState;

typedef struct PCIMultiSerialState {
    PCIDevice    dev;
    MemoryRegion iobar;
    uint32_t     ports;
    char         *name[PCI_SERIAL_MAX_PORTS];
    SerialState  state[PCI_SERIAL_MAX_PORTS];
    uint32_t     level[PCI_SERIAL_MAX_PORTS];
    qemu_irq     *irqs;
    uint8_t      prog_if;
} PCIMultiSerialState;

static void multi_serial_pci_exit(PCIDevice *dev);

static void serial_pci_realize(PCIDevice *dev, Error **errp)
{
    PCISerialState *pci = DO_UPCAST(PCISerialState, dev, dev);
    SerialState *s = &pci->state;
    Error *err = NULL;

    s->baudbase = 115200;
    serial_realize_core(s, &err);
    if (err != NULL) {
        error_propagate(errp, err);
        return;
    }

    pci->dev.config[PCI_CLASS_PROG] = pci->prog_if;
    pci->dev.config[PCI_INTERRUPT_PIN] = 0x01;
    s->irq = pci_allocate_irq(&pci->dev);

    memory_region_init_io(&s->io, OBJECT(pci), &serial_io_ops, s, "serial", 8);
    pci_register_bar(&pci->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io);
}

static void multi_serial_irq_mux(void *opaque, int n, int level)
{
    PCIMultiSerialState *pci = opaque;
    int i, pending = 0;

    pci->level[n] = level;
    for (i = 0; i < pci->ports; i++) {
        if (pci->level[i]) {
            pending = 1;
        }
    }
    pci_set_irq(&pci->dev, pending);
}

static void multi_serial_pci_realize(PCIDevice *dev, Error **errp)
{
    PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
    PCIMultiSerialState *pci = DO_UPCAST(PCIMultiSerialState, dev, dev);
    SerialState *s;
    Error *err = NULL;
    int i, nr_ports = 0;

    switch (pc->device_id) {
    case 0x0003:
        nr_ports = 2;
        break;
    case 0x0004:
        nr_ports = 4;
        break;
    }
    assert(nr_ports > 0);
    assert(nr_ports <= PCI_SERIAL_MAX_PORTS);

    pci->dev.config[PCI_CLASS_PROG] = pci->prog_if;
    pci->dev.config[PCI_INTERRUPT_PIN] = 0x01;
    memory_region_init(&pci->iobar, OBJECT(pci), "multiserial", 8 * nr_ports);
    pci_register_bar(&pci->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &pci->iobar);
    pci->irqs = qemu_allocate_irqs(multi_serial_irq_mux, pci,
                                   nr_ports);

    for (i = 0; i < nr_ports; i++) {
        s = pci->state + i;
        s->baudbase = 115200;
        serial_realize_core(s, &err);
        if (err != NULL) {
            error_propagate(errp, err);
            multi_serial_pci_exit(dev);
            return;
        }
        s->irq = pci->irqs[i];
        pci->name[i] = g_strdup_printf("uart #%d", i+1);
        memory_region_init_io(&s->io, OBJECT(pci), &serial_io_ops, s,
                              pci->name[i], 8);
        memory_region_add_subregion(&pci->iobar, 8 * i, &s->io);
        pci->ports++;
    }
}

static void serial_pci_exit(PCIDevice *dev)
{
    PCISerialState *pci = DO_UPCAST(PCISerialState, dev, dev);
    SerialState *s = &pci->state;

    serial_exit_core(s);
    qemu_free_irq(s->irq);
}

static void multi_serial_pci_exit(PCIDevice *dev)
{
    PCIMultiSerialState *pci = DO_UPCAST(PCIMultiSerialState, dev, dev);
    SerialState *s;
    int i;

    for (i = 0; i < pci->ports; i++) {
        s = pci->state + i;
        serial_exit_core(s);
        memory_region_del_subregion(&pci->iobar, &s->io);
        g_free(pci->name[i]);
    }
    qemu_free_irqs(pci->irqs, pci->ports);
}

static const VMStateDescription vmstate_pci_serial = {
    .name = "pci-serial",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_PCI_DEVICE(dev, PCISerialState),
        VMSTATE_STRUCT(state, PCISerialState, 0, vmstate_serial, SerialState),
        VMSTATE_END_OF_LIST()
    }
};

static const VMStateDescription vmstate_pci_multi_serial = {
    .name = "pci-serial-multi",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_PCI_DEVICE(dev, PCIMultiSerialState),
        VMSTATE_STRUCT_ARRAY(state, PCIMultiSerialState, PCI_SERIAL_MAX_PORTS,
                             0, vmstate_serial, SerialState),
        VMSTATE_UINT32_ARRAY(level, PCIMultiSerialState, PCI_SERIAL_MAX_PORTS),
        VMSTATE_END_OF_LIST()
    }
};

static Property serial_pci_properties[] = {
    DEFINE_PROP_CHR("chardev",  PCISerialState, state.chr),
    DEFINE_PROP_UINT8("prog_if",  PCISerialState, prog_if, 0x02),
    DEFINE_PROP_END_OF_LIST(),
};

static Property multi_2x_serial_pci_properties[] = {
    DEFINE_PROP_CHR("chardev1",  PCIMultiSerialState, state[0].chr),
    DEFINE_PROP_CHR("chardev2",  PCIMultiSerialState, state[1].chr),
    DEFINE_PROP_UINT8("prog_if",  PCIMultiSerialState, prog_if, 0x02),
    DEFINE_PROP_END_OF_LIST(),
};

static Property multi_4x_serial_pci_properties[] = {
    DEFINE_PROP_CHR("chardev1",  PCIMultiSerialState, state[0].chr),
    DEFINE_PROP_CHR("chardev2",  PCIMultiSerialState, state[1].chr),
    DEFINE_PROP_CHR("chardev3",  PCIMultiSerialState, state[2].chr),
    DEFINE_PROP_CHR("chardev4",  PCIMultiSerialState, state[3].chr),
    DEFINE_PROP_UINT8("prog_if",  PCIMultiSerialState, prog_if, 0x02),
    DEFINE_PROP_END_OF_LIST(),
};

static void serial_pci_class_initfn(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass);
    pc->realize = serial_pci_realize;
    pc->exit = serial_pci_exit;
    pc->vendor_id = PCI_VENDOR_ID_REDHAT;
    pc->device_id = PCI_DEVICE_ID_REDHAT_SERIAL;
    pc->revision = 1;
    pc->class_id = PCI_CLASS_COMMUNICATION_SERIAL;
    dc->vmsd = &vmstate_pci_serial;
    dc->props = serial_pci_properties;
    set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
}

static void multi_2x_serial_pci_class_initfn(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass);
    pc->realize = multi_serial_pci_realize;
    pc->exit = multi_serial_pci_exit;
    pc->vendor_id = PCI_VENDOR_ID_REDHAT;
    pc->device_id = PCI_DEVICE_ID_REDHAT_SERIAL2;
    pc->revision = 1;
    pc->class_id = PCI_CLASS_COMMUNICATION_SERIAL;
    dc->vmsd = &vmstate_pci_multi_serial;
    dc->props = multi_2x_serial_pci_properties;
    set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
}

static void multi_4x_serial_pci_class_initfn(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass);
    pc->realize = multi_serial_pci_realize;
    pc->exit = multi_serial_pci_exit;
    pc->vendor_id = PCI_VENDOR_ID_REDHAT;
    pc->device_id = PCI_DEVICE_ID_REDHAT_SERIAL4;
    pc->revision = 1;
    pc->class_id = PCI_CLASS_COMMUNICATION_SERIAL;
    dc->vmsd = &vmstate_pci_multi_serial;
    dc->props = multi_4x_serial_pci_properties;
    set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
}

static const TypeInfo serial_pci_info = {
    .name          = "pci-serial",
    .parent        = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCISerialState),
    .class_init    = serial_pci_class_initfn,
};

static const TypeInfo multi_2x_serial_pci_info = {
    .name          = "pci-serial-2x",
    .parent        = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCIMultiSerialState),
    .class_init    = multi_2x_serial_pci_class_initfn,
};

static const TypeInfo multi_4x_serial_pci_info = {
    .name          = "pci-serial-4x",
    .parent        = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCIMultiSerialState),
    .class_init    = multi_4x_serial_pci_class_initfn,
};

static void serial_pci_register_types(void)
{
    type_register_static(&serial_pci_info);
    type_register_static(&multi_2x_serial_pci_info);
    type_register_static(&multi_4x_serial_pci_info);
}

type_init(serial_pci_register_types)
Commit	Line	Data
419ad672 GH	1	/*
	2	* QEMU 16550A UART emulation
	3	*
	4	* Copyright (c) 2003-2004 Fabrice Bellard
	5	* Copyright (c) 2008 Citrix Systems, Inc.
	6	*
	7	* Permission is hereby granted, free of charge, to any person obtaining a copy
	8	* of this software and associated documentation files (the "Software"), to deal
	9	* in the Software without restriction, including without limitation the rights
	10	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	11	* copies of the Software, and to permit persons to whom the Software is
	12	* furnished to do so, subject to the following conditions:
	13	*
	14	* The above copyright notice and this permission notice shall be included in
	15	* all copies or substantial portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	22	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	23	* THE SOFTWARE.
	24	*/
	25
90734e02 GH	26	/* see docs/specs/pci-serial.txt */
90734e02 GH	27
0d09e41a	28	#include "hw/char/serial.h"
83c9f4ca	29	#include "hw/pci/pci.h"
419ad672	30
d66bbea4 GH	31	#define PCI_SERIAL_MAX_PORTS 4
d66bbea4 GH	32
419ad672 GH	33	typedef struct PCISerialState {
	34	PCIDevice dev;
	35	SerialState state;
13cc2c3e	36	uint8_t prog_if;
419ad672 GH	37	} PCISerialState;
419ad672 GH	38
d66bbea4 GH	39	typedef struct PCIMultiSerialState {
	40	PCIDevice dev;
	41	MemoryRegion iobar;
	42	uint32_t ports;
	43	char *name[PCI_SERIAL_MAX_PORTS];
	44	SerialState state[PCI_SERIAL_MAX_PORTS];
	45	uint32_t level[PCI_SERIAL_MAX_PORTS];
	46	qemu_irq *irqs;
13cc2c3e	47	uint8_t prog_if;
d66bbea4 GH	48	} PCIMultiSerialState;
d66bbea4 GH	49
a48da7b5 GH	50	static void multi_serial_pci_exit(PCIDevice *dev);
a48da7b5 GH	51
28d85904	52	static void serial_pci_realize(PCIDevice dev, Error *errp)
419ad672 GH	53	{
	54	PCISerialState *pci = DO_UPCAST(PCISerialState, dev, dev);
	55	SerialState *s = &pci->state;
db895a1e	56	Error *err = NULL;
419ad672 GH	57
419ad672 GH	58	s->baudbase = 115200;
db895a1e AF	59	serial_realize_core(s, &err);
db895a1e AF	60	if (err != NULL) {
28d85904 MA	61	error_propagate(errp, err);
28d85904 MA	62	return;
db895a1e	63	}
419ad672	64
13cc2c3e	65	pci->dev.config[PCI_CLASS_PROG] = pci->prog_if;
419ad672	66	pci->dev.config[PCI_INTERRUPT_PIN] = 0x01;
9e64f8a3	67	s->irq = pci_allocate_irq(&pci->dev);
419ad672	68
300b1fc6	69	memory_region_init_io(&s->io, OBJECT(pci), &serial_io_ops, s, "serial", 8);
419ad672	70	pci_register_bar(&pci->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io);
419ad672 GH	71	}
419ad672 GH	72
d66bbea4 GH	73	static void multi_serial_irq_mux(void *opaque, int n, int level)
	74	{
	75	PCIMultiSerialState *pci = opaque;
	76	int i, pending = 0;
	77
	78	pci->level[n] = level;
	79	for (i = 0; i < pci->ports; i++) {
	80	if (pci->level[i]) {
	81	pending = 1;
	82	}
	83	}
9e64f8a3	84	pci_set_irq(&pci->dev, pending);
d66bbea4 GH	85	}
d66bbea4 GH	86
28d85904	87	static void multi_serial_pci_realize(PCIDevice dev, Error *errp)
d66bbea4 GH	88	{
	89	PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
	90	PCIMultiSerialState *pci = DO_UPCAST(PCIMultiSerialState, dev, dev);
	91	SerialState *s;
db895a1e	92	Error *err = NULL;
a48da7b5	93	int i, nr_ports = 0;
d66bbea4 GH	94
	95	switch (pc->device_id) {
	96	case 0x0003:
a48da7b5	97	nr_ports = 2;
d66bbea4 GH	98	break;
d66bbea4 GH	99	case 0x0004:
a48da7b5	100	nr_ports = 4;
d66bbea4 GH	101	break;
d66bbea4 GH	102	}
a48da7b5 GH	103	assert(nr_ports > 0);
a48da7b5 GH	104	assert(nr_ports <= PCI_SERIAL_MAX_PORTS);
d66bbea4	105
13cc2c3e	106	pci->dev.config[PCI_CLASS_PROG] = pci->prog_if;
d66bbea4	107	pci->dev.config[PCI_INTERRUPT_PIN] = 0x01;
a48da7b5	108	memory_region_init(&pci->iobar, OBJECT(pci), "multiserial", 8 * nr_ports);
d66bbea4 GH	109	pci_register_bar(&pci->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &pci->iobar);
d66bbea4 GH	110	pci->irqs = qemu_allocate_irqs(multi_serial_irq_mux, pci,
a48da7b5	111	nr_ports);
d66bbea4	112
a48da7b5	113	for (i = 0; i < nr_ports; i++) {
d66bbea4 GH	114	s = pci->state + i;
d66bbea4 GH	115	s->baudbase = 115200;
db895a1e AF	116	serial_realize_core(s, &err);
db895a1e AF	117	if (err != NULL) {
28d85904	118	error_propagate(errp, err);
a48da7b5	119	multi_serial_pci_exit(dev);
28d85904	120	return;
db895a1e	121	}
d66bbea4 GH	122	s->irq = pci->irqs[i];
d66bbea4 GH	123	pci->name[i] = g_strdup_printf("uart #%d", i+1);
300b1fc6 PB	124	memory_region_init_io(&s->io, OBJECT(pci), &serial_io_ops, s,
300b1fc6 PB	125	pci->name[i], 8);
d66bbea4	126	memory_region_add_subregion(&pci->iobar, 8 * i, &s->io);
a48da7b5	127	pci->ports++;
d66bbea4	128	}
d66bbea4 GH	129	}
d66bbea4 GH	130
419ad672 GH	131	static void serial_pci_exit(PCIDevice *dev)
	132	{
	133	PCISerialState *pci = DO_UPCAST(PCISerialState, dev, dev);
	134	SerialState *s = &pci->state;
	135
	136	serial_exit_core(s);
9e64f8a3	137	qemu_free_irq(s->irq);
419ad672 GH	138	}
419ad672 GH	139
d66bbea4 GH	140	static void multi_serial_pci_exit(PCIDevice *dev)
	141	{
	142	PCIMultiSerialState *pci = DO_UPCAST(PCIMultiSerialState, dev, dev);
	143	SerialState *s;
	144	int i;
	145
	146	for (i = 0; i < pci->ports; i++) {
	147	s = pci->state + i;
	148	serial_exit_core(s);
7497bce6	149	memory_region_del_subregion(&pci->iobar, &s->io);
d66bbea4 GH	150	g_free(pci->name[i]);
d66bbea4 GH	151	}
f173d57a	152	qemu_free_irqs(pci->irqs, pci->ports);
d66bbea4 GH	153	}
d66bbea4 GH	154
419ad672 GH	155	static const VMStateDescription vmstate_pci_serial = {
	156	.name = "pci-serial",
	157	.version_id = 1,
	158	.minimum_version_id = 1,
d49805ae	159	.fields = (VMStateField[]) {
419ad672 GH	160	VMSTATE_PCI_DEVICE(dev, PCISerialState),
	161	VMSTATE_STRUCT(state, PCISerialState, 0, vmstate_serial, SerialState),
	162	VMSTATE_END_OF_LIST()
	163	}
	164	};
	165
d66bbea4 GH	166	static const VMStateDescription vmstate_pci_multi_serial = {
	167	.name = "pci-serial-multi",
	168	.version_id = 1,
	169	.minimum_version_id = 1,
d49805ae	170	.fields = (VMStateField[]) {
d66bbea4 GH	171	VMSTATE_PCI_DEVICE(dev, PCIMultiSerialState),
	172	VMSTATE_STRUCT_ARRAY(state, PCIMultiSerialState, PCI_SERIAL_MAX_PORTS,
	173	0, vmstate_serial, SerialState),
	174	VMSTATE_UINT32_ARRAY(level, PCIMultiSerialState, PCI_SERIAL_MAX_PORTS),
	175	VMSTATE_END_OF_LIST()
	176	}
	177	};
	178
419ad672 GH	179	static Property serial_pci_properties[] = {
419ad672 GH	180	DEFINE_PROP_CHR("chardev", PCISerialState, state.chr),
13cc2c3e	181	DEFINE_PROP_UINT8("prog_if", PCISerialState, prog_if, 0x02),
419ad672 GH	182	DEFINE_PROP_END_OF_LIST(),
	183	};
	184
d66bbea4 GH	185	static Property multi_2x_serial_pci_properties[] = {
	186	DEFINE_PROP_CHR("chardev1", PCIMultiSerialState, state[0].chr),
	187	DEFINE_PROP_CHR("chardev2", PCIMultiSerialState, state[1].chr),
13cc2c3e	188	DEFINE_PROP_UINT8("prog_if", PCIMultiSerialState, prog_if, 0x02),
d66bbea4 GH	189	DEFINE_PROP_END_OF_LIST(),
	190	};
	191
	192	static Property multi_4x_serial_pci_properties[] = {
	193	DEFINE_PROP_CHR("chardev1", PCIMultiSerialState, state[0].chr),
	194	DEFINE_PROP_CHR("chardev2", PCIMultiSerialState, state[1].chr),
	195	DEFINE_PROP_CHR("chardev3", PCIMultiSerialState, state[2].chr),
	196	DEFINE_PROP_CHR("chardev4", PCIMultiSerialState, state[3].chr),
13cc2c3e	197	DEFINE_PROP_UINT8("prog_if", PCIMultiSerialState, prog_if, 0x02),
d66bbea4 GH	198	DEFINE_PROP_END_OF_LIST(),
	199	};
	200
419ad672 GH	201	static void serial_pci_class_initfn(ObjectClass klass, void data)
	202	{
	203	DeviceClass *dc = DEVICE_CLASS(klass);
	204	PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass);
28d85904	205	pc->realize = serial_pci_realize;
419ad672	206	pc->exit = serial_pci_exit;
5c03a254 PB	207	pc->vendor_id = PCI_VENDOR_ID_REDHAT;
5c03a254 PB	208	pc->device_id = PCI_DEVICE_ID_REDHAT_SERIAL;
419ad672 GH	209	pc->revision = 1;
	210	pc->class_id = PCI_CLASS_COMMUNICATION_SERIAL;
	211	dc->vmsd = &vmstate_pci_serial;
	212	dc->props = serial_pci_properties;
125ee0ed	213	set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
419ad672 GH	214	}
419ad672 GH	215
d66bbea4 GH	216	static void multi_2x_serial_pci_class_initfn(ObjectClass klass, void data)
	217	{
	218	DeviceClass *dc = DEVICE_CLASS(klass);
	219	PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass);
28d85904	220	pc->realize = multi_serial_pci_realize;
d66bbea4	221	pc->exit = multi_serial_pci_exit;
5c03a254 PB	222	pc->vendor_id = PCI_VENDOR_ID_REDHAT;
5c03a254 PB	223	pc->device_id = PCI_DEVICE_ID_REDHAT_SERIAL2;
d66bbea4 GH	224	pc->revision = 1;
	225	pc->class_id = PCI_CLASS_COMMUNICATION_SERIAL;
	226	dc->vmsd = &vmstate_pci_multi_serial;
	227	dc->props = multi_2x_serial_pci_properties;
125ee0ed	228	set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
d66bbea4 GH	229	}
	230
	231	static void multi_4x_serial_pci_class_initfn(ObjectClass klass, void data)
	232	{
	233	DeviceClass *dc = DEVICE_CLASS(klass);
	234	PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass);
28d85904	235	pc->realize = multi_serial_pci_realize;
d66bbea4	236	pc->exit = multi_serial_pci_exit;
5c03a254 PB	237	pc->vendor_id = PCI_VENDOR_ID_REDHAT;
5c03a254 PB	238	pc->device_id = PCI_DEVICE_ID_REDHAT_SERIAL4;
d66bbea4 GH	239	pc->revision = 1;
	240	pc->class_id = PCI_CLASS_COMMUNICATION_SERIAL;
	241	dc->vmsd = &vmstate_pci_multi_serial;
	242	dc->props = multi_4x_serial_pci_properties;
125ee0ed	243	set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
d66bbea4 GH	244	}
d66bbea4 GH	245
8c43a6f0	246	static const TypeInfo serial_pci_info = {
419ad672 GH	247	.name = "pci-serial",
	248	.parent = TYPE_PCI_DEVICE,
	249	.instance_size = sizeof(PCISerialState),
	250	.class_init = serial_pci_class_initfn,
	251	};
	252
8c43a6f0	253	static const TypeInfo multi_2x_serial_pci_info = {
d66bbea4 GH	254	.name = "pci-serial-2x",
	255	.parent = TYPE_PCI_DEVICE,
	256	.instance_size = sizeof(PCIMultiSerialState),
	257	.class_init = multi_2x_serial_pci_class_initfn,
	258	};
	259
8c43a6f0	260	static const TypeInfo multi_4x_serial_pci_info = {
d66bbea4 GH	261	.name = "pci-serial-4x",
	262	.parent = TYPE_PCI_DEVICE,
	263	.instance_size = sizeof(PCIMultiSerialState),
	264	.class_init = multi_4x_serial_pci_class_initfn,
	265	};
	266
419ad672 GH	267	static void serial_pci_register_types(void)
	268	{
	269	type_register_static(&serial_pci_info);
d66bbea4 GH	270	type_register_static(&multi_2x_serial_pci_info);
d66bbea4 GH	271	type_register_static(&multi_4x_serial_pci_info);
419ad672 GH	272	}
	273
	274	type_init(serial_pci_register_types)