[qemu.git] / hw / pxa2xx_timer.c

/*
 * Intel XScale PXA255/270 OS Timers.
 *
 * Copyright (c) 2006 Openedhand Ltd.
 * Copyright (c) 2006 Thorsten Zitterell
 *
 * This code is licensed under the GPL.
 */

#include "hw.h"
#include "qemu-timer.h"
#include "sysemu.h"
#include "pxa.h"
#include "sysbus.h"

#define OSMR0	0x00
#define OSMR1	0x04
#define OSMR2	0x08
#define OSMR3	0x0c
#define OSMR4	0x80
#define OSMR5	0x84
#define OSMR6	0x88
#define OSMR7	0x8c
#define OSMR8	0x90
#define OSMR9	0x94
#define OSMR10	0x98
#define OSMR11	0x9c
#define OSCR	0x10	/* OS Timer Count */
#define OSCR4	0x40
#define OSCR5	0x44
#define OSCR6	0x48
#define OSCR7	0x4c
#define OSCR8	0x50
#define OSCR9	0x54
#define OSCR10	0x58
#define OSCR11	0x5c
#define OSSR	0x14	/* Timer status register */
#define OWER	0x18
#define OIER	0x1c	/* Interrupt enable register  3-0 to E3-E0 */
#define OMCR4	0xc0	/* OS Match Control registers */
#define OMCR5	0xc4
#define OMCR6	0xc8
#define OMCR7	0xcc
#define OMCR8	0xd0
#define OMCR9	0xd4
#define OMCR10	0xd8
#define OMCR11	0xdc
#define OSNR	0x20

#define PXA25X_FREQ	3686400	/* 3.6864 MHz */
#define PXA27X_FREQ	3250000	/* 3.25 MHz */

static int pxa2xx_timer4_freq[8] = {
    [0] = 0,
    [1] = 32768,
    [2] = 1000,
    [3] = 1,
    [4] = 1000000,
    /* [5] is the "Externally supplied clock".  Assign if necessary.  */
    [5 ... 7] = 0,
};

typedef struct PXA2xxTimerInfo PXA2xxTimerInfo;

typedef struct {
    uint32_t value;
    qemu_irq irq;
    QEMUTimer *qtimer;
    int num;
    PXA2xxTimerInfo *info;
} PXA2xxTimer0;

typedef struct {
    PXA2xxTimer0 tm;
    int32_t oldclock;
    int32_t clock;
    uint64_t lastload;
    uint32_t freq;
    uint32_t control;
} PXA2xxTimer4;

struct PXA2xxTimerInfo {
    SysBusDevice busdev;
    MemoryRegion iomem;
    uint32_t flags;

    int32_t clock;
    int32_t oldclock;
    uint64_t lastload;
    uint32_t freq;
    PXA2xxTimer0 timer[4];
    uint32_t events;
    uint32_t irq_enabled;
    uint32_t reset3;
    uint32_t snapshot;

    qemu_irq irq4;
    PXA2xxTimer4 tm4[8];
};

#define PXA2XX_TIMER_HAVE_TM4	0

static inline int pxa2xx_timer_has_tm4(PXA2xxTimerInfo *s)
{
    return s->flags & (1 << PXA2XX_TIMER_HAVE_TM4);
}

static void pxa2xx_timer_update(void *opaque, uint64_t now_qemu)
{
    PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
    int i;
    uint32_t now_vm;
    uint64_t new_qemu;

    now_vm = s->clock +
            muldiv64(now_qemu - s->lastload, s->freq, get_ticks_per_sec());

    for (i = 0; i < 4; i ++) {
        new_qemu = now_qemu + muldiv64((uint32_t) (s->timer[i].value - now_vm),
                        get_ticks_per_sec(), s->freq);
        qemu_mod_timer(s->timer[i].qtimer, new_qemu);
    }
}

static void pxa2xx_timer_update4(void *opaque, uint64_t now_qemu, int n)
{
    PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
    uint32_t now_vm;
    uint64_t new_qemu;
    static const int counters[8] = { 0, 0, 0, 0, 4, 4, 6, 6 };
    int counter;

    if (s->tm4[n].control & (1 << 7))
        counter = n;
    else
        counter = counters[n];

    if (!s->tm4[counter].freq) {
        qemu_del_timer(s->tm4[n].tm.qtimer);
        return;
    }

    now_vm = s->tm4[counter].clock + muldiv64(now_qemu -
                    s->tm4[counter].lastload,
                    s->tm4[counter].freq, get_ticks_per_sec());

    new_qemu = now_qemu + muldiv64((uint32_t) (s->tm4[n].tm.value - now_vm),
                    get_ticks_per_sec(), s->tm4[counter].freq);
    qemu_mod_timer(s->tm4[n].tm.qtimer, new_qemu);
}

static uint64_t pxa2xx_timer_read(void *opaque, hwaddr offset,
                                  unsigned size)
{
    PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
    int tm = 0;

    switch (offset) {
    case OSMR3:  tm ++;
    case OSMR2:  tm ++;
    case OSMR1:  tm ++;
    case OSMR0:
        return s->timer[tm].value;
    case OSMR11: tm ++;
    case OSMR10: tm ++;
    case OSMR9:  tm ++;
    case OSMR8:  tm ++;
    case OSMR7:  tm ++;
    case OSMR6:  tm ++;
    case OSMR5:  tm ++;
    case OSMR4:
        if (!pxa2xx_timer_has_tm4(s))
            goto badreg;
        return s->tm4[tm].tm.value;
    case OSCR:
        return s->clock + muldiv64(qemu_get_clock_ns(vm_clock) -
                        s->lastload, s->freq, get_ticks_per_sec());
    case OSCR11: tm ++;
    case OSCR10: tm ++;
    case OSCR9:  tm ++;
    case OSCR8:  tm ++;
    case OSCR7:  tm ++;
    case OSCR6:  tm ++;
    case OSCR5:  tm ++;
    case OSCR4:
        if (!pxa2xx_timer_has_tm4(s))
            goto badreg;

        if ((tm == 9 - 4 || tm == 11 - 4) && (s->tm4[tm].control & (1 << 9))) {
            if (s->tm4[tm - 1].freq)
                s->snapshot = s->tm4[tm - 1].clock + muldiv64(
                                qemu_get_clock_ns(vm_clock) -
                                s->tm4[tm - 1].lastload,
                                s->tm4[tm - 1].freq, get_ticks_per_sec());
            else
                s->snapshot = s->tm4[tm - 1].clock;
        }

        if (!s->tm4[tm].freq)
            return s->tm4[tm].clock;
        return s->tm4[tm].clock + muldiv64(qemu_get_clock_ns(vm_clock) -
                        s->tm4[tm].lastload, s->tm4[tm].freq, get_ticks_per_sec());
    case OIER:
        return s->irq_enabled;
    case OSSR:	/* Status register */
        return s->events;
    case OWER:
        return s->reset3;
    case OMCR11: tm ++;
    case OMCR10: tm ++;
    case OMCR9:  tm ++;
    case OMCR8:  tm ++;
    case OMCR7:  tm ++;
    case OMCR6:  tm ++;
    case OMCR5:  tm ++;
    case OMCR4:
        if (!pxa2xx_timer_has_tm4(s))
            goto badreg;
        return s->tm4[tm].control;
    case OSNR:
        return s->snapshot;
    default:
    badreg:
        hw_error("pxa2xx_timer_read: Bad offset " REG_FMT "\n", offset);
    }

    return 0;
}

static void pxa2xx_timer_write(void *opaque, hwaddr offset,
                               uint64_t value, unsigned size)
{
    int i, tm = 0;
    PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;

    switch (offset) {
    case OSMR3:  tm ++;
    case OSMR2:  tm ++;
    case OSMR1:  tm ++;
    case OSMR0:
        s->timer[tm].value = value;
        pxa2xx_timer_update(s, qemu_get_clock_ns(vm_clock));
        break;
    case OSMR11: tm ++;
    case OSMR10: tm ++;
    case OSMR9:  tm ++;
    case OSMR8:  tm ++;
    case OSMR7:  tm ++;
    case OSMR6:  tm ++;
    case OSMR5:  tm ++;
    case OSMR4:
        if (!pxa2xx_timer_has_tm4(s))
            goto badreg;
        s->tm4[tm].tm.value = value;
        pxa2xx_timer_update4(s, qemu_get_clock_ns(vm_clock), tm);
        break;
    case OSCR:
        s->oldclock = s->clock;
        s->lastload = qemu_get_clock_ns(vm_clock);
        s->clock = value;
        pxa2xx_timer_update(s, s->lastload);
        break;
    case OSCR11: tm ++;
    case OSCR10: tm ++;
    case OSCR9:  tm ++;
    case OSCR8:  tm ++;
    case OSCR7:  tm ++;
    case OSCR6:  tm ++;
    case OSCR5:  tm ++;
    case OSCR4:
        if (!pxa2xx_timer_has_tm4(s))
            goto badreg;
        s->tm4[tm].oldclock = s->tm4[tm].clock;
        s->tm4[tm].lastload = qemu_get_clock_ns(vm_clock);
        s->tm4[tm].clock = value;
        pxa2xx_timer_update4(s, s->tm4[tm].lastload, tm);
        break;
    case OIER:
        s->irq_enabled = value & 0xfff;
        break;
    case OSSR:	/* Status register */
        value &= s->events;
        s->events &= ~value;
        for (i = 0; i < 4; i ++, value >>= 1)
            if (value & 1)
                qemu_irq_lower(s->timer[i].irq);
        if (pxa2xx_timer_has_tm4(s) && !(s->events & 0xff0) && value)
            qemu_irq_lower(s->irq4);
        break;
    case OWER:	/* XXX: Reset on OSMR3 match? */
        s->reset3 = value;
        break;
    case OMCR7:  tm ++;
    case OMCR6:  tm ++;
    case OMCR5:  tm ++;
    case OMCR4:
        if (!pxa2xx_timer_has_tm4(s))
            goto badreg;
        s->tm4[tm].control = value & 0x0ff;
        /* XXX Stop if running (shouldn't happen) */
        if ((value & (1 << 7)) || tm == 0)
            s->tm4[tm].freq = pxa2xx_timer4_freq[value & 7];
        else {
            s->tm4[tm].freq = 0;
            pxa2xx_timer_update4(s, qemu_get_clock_ns(vm_clock), tm);
        }
        break;
    case OMCR11: tm ++;
    case OMCR10: tm ++;
    case OMCR9:  tm ++;
    case OMCR8:  tm += 4;
        if (!pxa2xx_timer_has_tm4(s))
            goto badreg;
        s->tm4[tm].control = value & 0x3ff;
        /* XXX Stop if running (shouldn't happen) */
        if ((value & (1 << 7)) || !(tm & 1))
            s->tm4[tm].freq =
                    pxa2xx_timer4_freq[(value & (1 << 8)) ?  0 : (value & 7)];
        else {
            s->tm4[tm].freq = 0;
            pxa2xx_timer_update4(s, qemu_get_clock_ns(vm_clock), tm);
        }
        break;
    default:
    badreg:
        hw_error("pxa2xx_timer_write: Bad offset " REG_FMT "\n", offset);
    }
}

static const MemoryRegionOps pxa2xx_timer_ops = {
    .read = pxa2xx_timer_read,
    .write = pxa2xx_timer_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static void pxa2xx_timer_tick(void *opaque)
{
    PXA2xxTimer0 *t = (PXA2xxTimer0 *) opaque;
    PXA2xxTimerInfo *i = t->info;

    if (i->irq_enabled & (1 << t->num)) {
        i->events |= 1 << t->num;
        qemu_irq_raise(t->irq);
    }

    if (t->num == 3)
        if (i->reset3 & 1) {
            i->reset3 = 0;
            qemu_system_reset_request();
        }
}

static void pxa2xx_timer_tick4(void *opaque)
{
    PXA2xxTimer4 *t = (PXA2xxTimer4 *) opaque;
    PXA2xxTimerInfo *i = (PXA2xxTimerInfo *) t->tm.info;

    pxa2xx_timer_tick(&t->tm);
    if (t->control & (1 << 3))
        t->clock = 0;
    if (t->control & (1 << 6))
        pxa2xx_timer_update4(i, qemu_get_clock_ns(vm_clock), t->tm.num - 4);
    if (i->events & 0xff0)
        qemu_irq_raise(i->irq4);
}

static int pxa25x_timer_post_load(void *opaque, int version_id)
{
    PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
    int64_t now;
    int i;

    now = qemu_get_clock_ns(vm_clock);
    pxa2xx_timer_update(s, now);

    if (pxa2xx_timer_has_tm4(s))
        for (i = 0; i < 8; i ++)
            pxa2xx_timer_update4(s, now, i);

    return 0;
}

static int pxa2xx_timer_init(SysBusDevice *dev)
{
    int i;
    PXA2xxTimerInfo *s;

    s = FROM_SYSBUS(PXA2xxTimerInfo, dev);
    s->irq_enabled = 0;
    s->oldclock = 0;
    s->clock = 0;
    s->lastload = qemu_get_clock_ns(vm_clock);
    s->reset3 = 0;

    for (i = 0; i < 4; i ++) {
        s->timer[i].value = 0;
        sysbus_init_irq(dev, &s->timer[i].irq);
        s->timer[i].info = s;
        s->timer[i].num = i;
        s->timer[i].qtimer = qemu_new_timer_ns(vm_clock,
                        pxa2xx_timer_tick, &s->timer[i]);
    }
    if (s->flags & (1 << PXA2XX_TIMER_HAVE_TM4)) {
        sysbus_init_irq(dev, &s->irq4);

        for (i = 0; i < 8; i ++) {
            s->tm4[i].tm.value = 0;
            s->tm4[i].tm.info = s;
            s->tm4[i].tm.num = i + 4;
            s->tm4[i].freq = 0;
            s->tm4[i].control = 0x0;
            s->tm4[i].tm.qtimer = qemu_new_timer_ns(vm_clock,
                        pxa2xx_timer_tick4, &s->tm4[i]);
        }
    }

    memory_region_init_io(&s->iomem, &pxa2xx_timer_ops, s,
                          "pxa2xx-timer", 0x00001000);
    sysbus_init_mmio(dev, &s->iomem);

    return 0;
}

static const VMStateDescription vmstate_pxa2xx_timer0_regs = {
    .name = "pxa2xx_timer0",
    .version_id = 2,
    .minimum_version_id = 2,
    .minimum_version_id_old = 2,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(value, PXA2xxTimer0),
        VMSTATE_END_OF_LIST(),
    },
};

static const VMStateDescription vmstate_pxa2xx_timer4_regs = {
    .name = "pxa2xx_timer4",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields = (VMStateField[]) {
        VMSTATE_STRUCT(tm, PXA2xxTimer4, 1,
                        vmstate_pxa2xx_timer0_regs, PXA2xxTimer0),
        VMSTATE_INT32(oldclock, PXA2xxTimer4),
        VMSTATE_INT32(clock, PXA2xxTimer4),
        VMSTATE_UINT64(lastload, PXA2xxTimer4),
        VMSTATE_UINT32(freq, PXA2xxTimer4),
        VMSTATE_UINT32(control, PXA2xxTimer4),
        VMSTATE_END_OF_LIST(),
    },
};

static bool pxa2xx_timer_has_tm4_test(void *opaque, int version_id)
{
    return pxa2xx_timer_has_tm4(opaque);
}

static const VMStateDescription vmstate_pxa2xx_timer_regs = {
    .name = "pxa2xx_timer",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .post_load = pxa25x_timer_post_load,
    .fields = (VMStateField[]) {
        VMSTATE_INT32(clock, PXA2xxTimerInfo),
        VMSTATE_INT32(oldclock, PXA2xxTimerInfo),
        VMSTATE_UINT64(lastload, PXA2xxTimerInfo),
        VMSTATE_STRUCT_ARRAY(timer, PXA2xxTimerInfo, 4, 1,
                        vmstate_pxa2xx_timer0_regs, PXA2xxTimer0),
        VMSTATE_UINT32(events, PXA2xxTimerInfo),
        VMSTATE_UINT32(irq_enabled, PXA2xxTimerInfo),
        VMSTATE_UINT32(reset3, PXA2xxTimerInfo),
        VMSTATE_UINT32(snapshot, PXA2xxTimerInfo),
        VMSTATE_STRUCT_ARRAY_TEST(tm4, PXA2xxTimerInfo, 8,
                        pxa2xx_timer_has_tm4_test, 0,
                        vmstate_pxa2xx_timer4_regs, PXA2xxTimer4),
        VMSTATE_END_OF_LIST(),
    }
};

static Property pxa25x_timer_dev_properties[] = {
    DEFINE_PROP_UINT32("freq", PXA2xxTimerInfo, freq, PXA25X_FREQ),
    DEFINE_PROP_BIT("tm4", PXA2xxTimerInfo, flags,
    PXA2XX_TIMER_HAVE_TM4, false),
    DEFINE_PROP_END_OF_LIST(),
};

static void pxa25x_timer_dev_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);

    k->init = pxa2xx_timer_init;
    dc->desc = "PXA25x timer";
    dc->vmsd = &vmstate_pxa2xx_timer_regs;
    dc->props = pxa25x_timer_dev_properties;
}

static TypeInfo pxa25x_timer_dev_info = {
    .name          = "pxa25x-timer",
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(PXA2xxTimerInfo),
    .class_init    = pxa25x_timer_dev_class_init,
};

static Property pxa27x_timer_dev_properties[] = {
    DEFINE_PROP_UINT32("freq", PXA2xxTimerInfo, freq, PXA27X_FREQ),
    DEFINE_PROP_BIT("tm4", PXA2xxTimerInfo, flags,
    PXA2XX_TIMER_HAVE_TM4, true),
    DEFINE_PROP_END_OF_LIST(),
};

static void pxa27x_timer_dev_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);

    k->init = pxa2xx_timer_init;
    dc->desc = "PXA27x timer";
    dc->vmsd = &vmstate_pxa2xx_timer_regs;
    dc->props = pxa27x_timer_dev_properties;
}

static TypeInfo pxa27x_timer_dev_info = {
    .name          = "pxa27x-timer",
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(PXA2xxTimerInfo),
    .class_init    = pxa27x_timer_dev_class_init,
};

static void pxa2xx_timer_register_types(void)
{
    type_register_static(&pxa25x_timer_dev_info);
    type_register_static(&pxa27x_timer_dev_info);
}

type_init(pxa2xx_timer_register_types)
Commit	Line	Data
a171fe39 AZ	1	/*
	2	* Intel XScale PXA255/270 OS Timers.
	3	*
	4	* Copyright (c) 2006 Openedhand Ltd.
	5	* Copyright (c) 2006 Thorsten Zitterell
	6	*
8e31bf38	7	* This code is licensed under the GPL.
a171fe39 AZ	8	*/
a171fe39 AZ	9
87ecb68b PB	10	#include "hw.h"
	11	#include "qemu-timer.h"
	12	#include "sysemu.h"
	13	#include "pxa.h"
797e9542	14	#include "sysbus.h"
a171fe39 AZ	15
	16	#define OSMR0 0x00
	17	#define OSMR1 0x04
	18	#define OSMR2 0x08
	19	#define OSMR3 0x0c
	20	#define OSMR4 0x80
	21	#define OSMR5 0x84
	22	#define OSMR6 0x88
	23	#define OSMR7 0x8c
	24	#define OSMR8 0x90
	25	#define OSMR9 0x94
	26	#define OSMR10 0x98
	27	#define OSMR11 0x9c
	28	#define OSCR 0x10 /* OS Timer Count */
	29	#define OSCR4 0x40
	30	#define OSCR5 0x44
	31	#define OSCR6 0x48
	32	#define OSCR7 0x4c
	33	#define OSCR8 0x50
	34	#define OSCR9 0x54
	35	#define OSCR10 0x58
	36	#define OSCR11 0x5c
	37	#define OSSR 0x14 /* Timer status register */
	38	#define OWER 0x18
	39	#define OIER 0x1c /* Interrupt enable register 3-0 to E3-E0 */
	40	#define OMCR4 0xc0 /* OS Match Control registers */
	41	#define OMCR5 0xc4
	42	#define OMCR6 0xc8
	43	#define OMCR7 0xcc
	44	#define OMCR8 0xd0
	45	#define OMCR9 0xd4
	46	#define OMCR10 0xd8
	47	#define OMCR11 0xdc
	48	#define OSNR 0x20
	49
	50	#define PXA25X_FREQ 3686400 /* 3.6864 MHz */
	51	#define PXA27X_FREQ 3250000 /* 3.25 MHz */
	52
	53	static int pxa2xx_timer4_freq[8] = {
	54	[0] = 0,
	55	[1] = 32768,
	56	[2] = 1000,
	57	[3] = 1,
	58	[4] = 1000000,
	59	/* [5] is the "Externally supplied clock". Assign if necessary. */
	60	[5 ... 7] = 0,
	61	};
	62
797e9542 DES	63	typedef struct PXA2xxTimerInfo PXA2xxTimerInfo;
797e9542 DES	64
bc24a225	65	typedef struct {
a171fe39	66	uint32_t value;
5251d196	67	qemu_irq irq;
a171fe39 AZ	68	QEMUTimer *qtimer;
a171fe39 AZ	69	int num;
797e9542	70	PXA2xxTimerInfo *info;
bc24a225	71	} PXA2xxTimer0;
a171fe39	72
bc24a225 PB	73	typedef struct {
bc24a225 PB	74	PXA2xxTimer0 tm;
a171fe39 AZ	75	int32_t oldclock;
	76	int32_t clock;
	77	uint64_t lastload;
	78	uint32_t freq;
	79	uint32_t control;
bc24a225	80	} PXA2xxTimer4;
a171fe39	81
797e9542 DES	82	struct PXA2xxTimerInfo {
797e9542 DES	83	SysBusDevice busdev;
b755bde3	84	MemoryRegion iomem;
797e9542 DES	85	uint32_t flags;
797e9542 DES	86
a171fe39 AZ	87	int32_t clock;
	88	int32_t oldclock;
	89	uint64_t lastload;
	90	uint32_t freq;
bc24a225	91	PXA2xxTimer0 timer[4];
a171fe39 AZ	92	uint32_t events;
	93	uint32_t irq_enabled;
	94	uint32_t reset3;
a171fe39	95	uint32_t snapshot;
797e9542	96
4ff927cc	97	qemu_irq irq4;
797e9542	98	PXA2xxTimer4 tm4[8];
797e9542 DES	99	};
	100
	101	#define PXA2XX_TIMER_HAVE_TM4 0
	102
	103	static inline int pxa2xx_timer_has_tm4(PXA2xxTimerInfo *s)
	104	{
	105	return s->flags & (1 << PXA2XX_TIMER_HAVE_TM4);
	106	}
a171fe39 AZ	107
	108	static void pxa2xx_timer_update(void *opaque, uint64_t now_qemu)
	109	{
d353eb43	110	PXA2xxTimerInfo s = (PXA2xxTimerInfo ) opaque;
a171fe39 AZ	111	int i;
	112	uint32_t now_vm;
	113	uint64_t new_qemu;
	114
	115	now_vm = s->clock +
6ee093c9	116	muldiv64(now_qemu - s->lastload, s->freq, get_ticks_per_sec());
a171fe39 AZ	117
	118	for (i = 0; i < 4; i ++) {
	119	new_qemu = now_qemu + muldiv64((uint32_t) (s->timer[i].value - now_vm),
6ee093c9	120	get_ticks_per_sec(), s->freq);
a171fe39 AZ	121	qemu_mod_timer(s->timer[i].qtimer, new_qemu);
	122	}
	123	}
	124
	125	static void pxa2xx_timer_update4(void *opaque, uint64_t now_qemu, int n)
	126	{
d353eb43	127	PXA2xxTimerInfo s = (PXA2xxTimerInfo ) opaque;
a171fe39 AZ	128	uint32_t now_vm;
	129	uint64_t new_qemu;
	130	static const int counters[8] = { 0, 0, 0, 0, 4, 4, 6, 6 };
	131	int counter;
	132
	133	if (s->tm4[n].control & (1 << 7))
	134	counter = n;
	135	else
	136	counter = counters[n];
	137
	138	if (!s->tm4[counter].freq) {
3f582262	139	qemu_del_timer(s->tm4[n].tm.qtimer);
a171fe39 AZ	140	return;
	141	}
	142
	143	now_vm = s->tm4[counter].clock + muldiv64(now_qemu -
	144	s->tm4[counter].lastload,
6ee093c9	145	s->tm4[counter].freq, get_ticks_per_sec());
a171fe39	146
3bdd58a4	147	new_qemu = now_qemu + muldiv64((uint32_t) (s->tm4[n].tm.value - now_vm),
6ee093c9	148	get_ticks_per_sec(), s->tm4[counter].freq);
3f582262	149	qemu_mod_timer(s->tm4[n].tm.qtimer, new_qemu);
a171fe39 AZ	150	}
a171fe39 AZ	151
a8170e5e	152	static uint64_t pxa2xx_timer_read(void *opaque, hwaddr offset,
b755bde3	153	unsigned size)
a171fe39	154	{
d353eb43	155	PXA2xxTimerInfo s = (PXA2xxTimerInfo ) opaque;
a171fe39 AZ	156	int tm = 0;
a171fe39 AZ	157
a171fe39 AZ	158	switch (offset) {
	159	case OSMR3: tm ++;
	160	case OSMR2: tm ++;
	161	case OSMR1: tm ++;
	162	case OSMR0:
	163	return s->timer[tm].value;
	164	case OSMR11: tm ++;
	165	case OSMR10: tm ++;
	166	case OSMR9: tm ++;
	167	case OSMR8: tm ++;
	168	case OSMR7: tm ++;
	169	case OSMR6: tm ++;
	170	case OSMR5: tm ++;
	171	case OSMR4:
797e9542	172	if (!pxa2xx_timer_has_tm4(s))
a171fe39	173	goto badreg;
3bdd58a4	174	return s->tm4[tm].tm.value;
a171fe39	175	case OSCR:
74475455	176	return s->clock + muldiv64(qemu_get_clock_ns(vm_clock) -
6ee093c9	177	s->lastload, s->freq, get_ticks_per_sec());
a171fe39 AZ	178	case OSCR11: tm ++;
	179	case OSCR10: tm ++;
	180	case OSCR9: tm ++;
	181	case OSCR8: tm ++;
	182	case OSCR7: tm ++;
	183	case OSCR6: tm ++;
	184	case OSCR5: tm ++;
	185	case OSCR4:
797e9542	186	if (!pxa2xx_timer_has_tm4(s))
a171fe39 AZ	187	goto badreg;
	188
	189	if ((tm == 9 - 4 \|\| tm == 11 - 4) && (s->tm4[tm].control & (1 << 9))) {
	190	if (s->tm4[tm - 1].freq)
	191	s->snapshot = s->tm4[tm - 1].clock + muldiv64(
74475455	192	qemu_get_clock_ns(vm_clock) -
a171fe39	193	s->tm4[tm - 1].lastload,
6ee093c9	194	s->tm4[tm - 1].freq, get_ticks_per_sec());
a171fe39 AZ	195	else
	196	s->snapshot = s->tm4[tm - 1].clock;
	197	}
	198
	199	if (!s->tm4[tm].freq)
	200	return s->tm4[tm].clock;
74475455	201	return s->tm4[tm].clock + muldiv64(qemu_get_clock_ns(vm_clock) -
6ee093c9	202	s->tm4[tm].lastload, s->tm4[tm].freq, get_ticks_per_sec());
a171fe39 AZ	203	case OIER:
	204	return s->irq_enabled;
	205	case OSSR: /* Status register */
	206	return s->events;
	207	case OWER:
	208	return s->reset3;
	209	case OMCR11: tm ++;
	210	case OMCR10: tm ++;
	211	case OMCR9: tm ++;
	212	case OMCR8: tm ++;
	213	case OMCR7: tm ++;
	214	case OMCR6: tm ++;
	215	case OMCR5: tm ++;
	216	case OMCR4:
797e9542	217	if (!pxa2xx_timer_has_tm4(s))
a171fe39 AZ	218	goto badreg;
	219	return s->tm4[tm].control;
	220	case OSNR:
	221	return s->snapshot;
	222	default:
	223	badreg:
2ac71179	224	hw_error("pxa2xx_timer_read: Bad offset " REG_FMT "\n", offset);
a171fe39 AZ	225	}
	226
	227	return 0;
	228	}
	229
a8170e5e	230	static void pxa2xx_timer_write(void *opaque, hwaddr offset,
b755bde3	231	uint64_t value, unsigned size)
a171fe39 AZ	232	{
a171fe39 AZ	233	int i, tm = 0;
d353eb43	234	PXA2xxTimerInfo s = (PXA2xxTimerInfo ) opaque;
a171fe39	235
a171fe39 AZ	236	switch (offset) {
	237	case OSMR3: tm ++;
	238	case OSMR2: tm ++;
	239	case OSMR1: tm ++;
	240	case OSMR0:
	241	s->timer[tm].value = value;
74475455	242	pxa2xx_timer_update(s, qemu_get_clock_ns(vm_clock));
a171fe39 AZ	243	break;
	244	case OSMR11: tm ++;
	245	case OSMR10: tm ++;
	246	case OSMR9: tm ++;
	247	case OSMR8: tm ++;
	248	case OSMR7: tm ++;
	249	case OSMR6: tm ++;
	250	case OSMR5: tm ++;
	251	case OSMR4:
797e9542	252	if (!pxa2xx_timer_has_tm4(s))
a171fe39	253	goto badreg;
3bdd58a4	254	s->tm4[tm].tm.value = value;
74475455	255	pxa2xx_timer_update4(s, qemu_get_clock_ns(vm_clock), tm);
a171fe39 AZ	256	break;
	257	case OSCR:
	258	s->oldclock = s->clock;
74475455	259	s->lastload = qemu_get_clock_ns(vm_clock);
a171fe39 AZ	260	s->clock = value;
	261	pxa2xx_timer_update(s, s->lastload);
	262	break;
	263	case OSCR11: tm ++;
	264	case OSCR10: tm ++;
	265	case OSCR9: tm ++;
	266	case OSCR8: tm ++;
	267	case OSCR7: tm ++;
	268	case OSCR6: tm ++;
	269	case OSCR5: tm ++;
	270	case OSCR4:
797e9542	271	if (!pxa2xx_timer_has_tm4(s))
a171fe39 AZ	272	goto badreg;
a171fe39 AZ	273	s->tm4[tm].oldclock = s->tm4[tm].clock;
74475455	274	s->tm4[tm].lastload = qemu_get_clock_ns(vm_clock);
a171fe39 AZ	275	s->tm4[tm].clock = value;
	276	pxa2xx_timer_update4(s, s->tm4[tm].lastload, tm);
	277	break;
	278	case OIER:
	279	s->irq_enabled = value & 0xfff;
	280	break;
	281	case OSSR: /* Status register */
8034ce7d	282	value &= s->events;
a171fe39	283	s->events &= ~value;
8034ce7d AZ	284	for (i = 0; i < 4; i ++, value >>= 1)
8034ce7d AZ	285	if (value & 1)
5251d196	286	qemu_irq_lower(s->timer[i].irq);
8034ce7d AZ	287	if (pxa2xx_timer_has_tm4(s) && !(s->events & 0xff0) && value)
8034ce7d AZ	288	qemu_irq_lower(s->irq4);
a171fe39 AZ	289	break;
	290	case OWER: /* XXX: Reset on OSMR3 match? */
	291	s->reset3 = value;
	292	break;
	293	case OMCR7: tm ++;
	294	case OMCR6: tm ++;
	295	case OMCR5: tm ++;
	296	case OMCR4:
797e9542	297	if (!pxa2xx_timer_has_tm4(s))
a171fe39 AZ	298	goto badreg;
	299	s->tm4[tm].control = value & 0x0ff;
	300	/* XXX Stop if running (shouldn't happen) */
	301	if ((value & (1 << 7)) \|\| tm == 0)
	302	s->tm4[tm].freq = pxa2xx_timer4_freq[value & 7];
	303	else {
	304	s->tm4[tm].freq = 0;
74475455	305	pxa2xx_timer_update4(s, qemu_get_clock_ns(vm_clock), tm);
a171fe39 AZ	306	}
	307	break;
	308	case OMCR11: tm ++;
	309	case OMCR10: tm ++;
	310	case OMCR9: tm ++;
	311	case OMCR8: tm += 4;
797e9542	312	if (!pxa2xx_timer_has_tm4(s))
a171fe39 AZ	313	goto badreg;
	314	s->tm4[tm].control = value & 0x3ff;
	315	/* XXX Stop if running (shouldn't happen) */
	316	if ((value & (1 << 7)) \|\| !(tm & 1))
	317	s->tm4[tm].freq =
	318	pxa2xx_timer4_freq[(value & (1 << 8)) ? 0 : (value & 7)];
	319	else {
	320	s->tm4[tm].freq = 0;
74475455	321	pxa2xx_timer_update4(s, qemu_get_clock_ns(vm_clock), tm);
a171fe39 AZ	322	}
	323	break;
	324	default:
	325	badreg:
2ac71179	326	hw_error("pxa2xx_timer_write: Bad offset " REG_FMT "\n", offset);
a171fe39 AZ	327	}
	328	}
	329
b755bde3 BC	330	static const MemoryRegionOps pxa2xx_timer_ops = {
	331	.read = pxa2xx_timer_read,
	332	.write = pxa2xx_timer_write,
	333	.endianness = DEVICE_NATIVE_ENDIAN,
a171fe39 AZ	334	};
	335
	336	static void pxa2xx_timer_tick(void *opaque)
	337	{
bc24a225	338	PXA2xxTimer0 t = (PXA2xxTimer0 ) opaque;
797e9542	339	PXA2xxTimerInfo *i = t->info;
a171fe39 AZ	340
a171fe39 AZ	341	if (i->irq_enabled & (1 << t->num)) {
a171fe39	342	i->events \|= 1 << t->num;
5251d196	343	qemu_irq_raise(t->irq);
a171fe39 AZ	344	}
	345
	346	if (t->num == 3)
	347	if (i->reset3 & 1) {
	348	i->reset3 = 0;
3f582262	349	qemu_system_reset_request();
a171fe39 AZ	350	}
	351	}
	352
	353	static void pxa2xx_timer_tick4(void *opaque)
	354	{
bc24a225	355	PXA2xxTimer4 t = (PXA2xxTimer4 ) opaque;
d353eb43	356	PXA2xxTimerInfo i = (PXA2xxTimerInfo ) t->tm.info;
a171fe39	357
3bdd58a4	358	pxa2xx_timer_tick(&t->tm);
a171fe39 AZ	359	if (t->control & (1 << 3))
	360	t->clock = 0;
	361	if (t->control & (1 << 6))
74475455	362	pxa2xx_timer_update4(i, qemu_get_clock_ns(vm_clock), t->tm.num - 4);
4ff927cc DES	363	if (i->events & 0xff0)
4ff927cc DES	364	qemu_irq_raise(i->irq4);
a171fe39 AZ	365	}
a171fe39 AZ	366
797e9542	367	static int pxa25x_timer_post_load(void *opaque, int version_id)
aa941b94	368	{
d353eb43	369	PXA2xxTimerInfo s = (PXA2xxTimerInfo ) opaque;
aa941b94 AZ	370	int64_t now;
	371	int i;
	372
74475455	373	now = qemu_get_clock_ns(vm_clock);
aa941b94 AZ	374	pxa2xx_timer_update(s, now);
aa941b94 AZ	375
797e9542 DES	376	if (pxa2xx_timer_has_tm4(s))
797e9542 DES	377	for (i = 0; i < 8; i ++)
aa941b94	378	pxa2xx_timer_update4(s, now, i);
aa941b94 AZ	379
	380	return 0;
	381	}
	382
797e9542	383	static int pxa2xx_timer_init(SysBusDevice *dev)
a171fe39 AZ	384	{
a171fe39 AZ	385	int i;
d353eb43	386	PXA2xxTimerInfo *s;
a171fe39	387
797e9542	388	s = FROM_SYSBUS(PXA2xxTimerInfo, dev);
a171fe39 AZ	389	s->irq_enabled = 0;
	390	s->oldclock = 0;
	391	s->clock = 0;
74475455	392	s->lastload = qemu_get_clock_ns(vm_clock);
a171fe39	393	s->reset3 = 0;
a171fe39 AZ	394
	395	for (i = 0; i < 4; i ++) {
	396	s->timer[i].value = 0;
5251d196	397	sysbus_init_irq(dev, &s->timer[i].irq);
a171fe39 AZ	398	s->timer[i].info = s;
a171fe39 AZ	399	s->timer[i].num = i;
74475455	400	s->timer[i].qtimer = qemu_new_timer_ns(vm_clock,
a171fe39 AZ	401	pxa2xx_timer_tick, &s->timer[i]);
a171fe39 AZ	402	}
797e9542	403	if (s->flags & (1 << PXA2XX_TIMER_HAVE_TM4)) {
4ff927cc	404	sysbus_init_irq(dev, &s->irq4);
797e9542 DES	405
	406	for (i = 0; i < 8; i ++) {
	407	s->tm4[i].tm.value = 0;
	408	s->tm4[i].tm.info = s;
	409	s->tm4[i].tm.num = i + 4;
797e9542 DES	410	s->tm4[i].freq = 0;
797e9542 DES	411	s->tm4[i].control = 0x0;
74475455	412	s->tm4[i].tm.qtimer = qemu_new_timer_ns(vm_clock,
797e9542 DES	413	pxa2xx_timer_tick4, &s->tm4[i]);
	414	}
	415	}
a171fe39	416
b755bde3 BC	417	memory_region_init_io(&s->iomem, &pxa2xx_timer_ops, s,
b755bde3 BC	418	"pxa2xx-timer", 0x00001000);
750ecd44	419	sysbus_init_mmio(dev, &s->iomem);
aa941b94	420
797e9542	421	return 0;
a171fe39 AZ	422	}
a171fe39 AZ	423
797e9542 DES	424	static const VMStateDescription vmstate_pxa2xx_timer0_regs = {
797e9542 DES	425	.name = "pxa2xx_timer0",
8034ce7d AZ	426	.version_id = 2,
	427	.minimum_version_id = 2,
	428	.minimum_version_id_old = 2,
797e9542 DES	429	.fields = (VMStateField[]) {
797e9542 DES	430	VMSTATE_UINT32(value, PXA2xxTimer0),
797e9542 DES	431	VMSTATE_END_OF_LIST(),
	432	},
	433	};
	434
	435	static const VMStateDescription vmstate_pxa2xx_timer4_regs = {
	436	.name = "pxa2xx_timer4",
	437	.version_id = 1,
	438	.minimum_version_id = 1,
	439	.minimum_version_id_old = 1,
	440	.fields = (VMStateField[]) {
	441	VMSTATE_STRUCT(tm, PXA2xxTimer4, 1,
	442	vmstate_pxa2xx_timer0_regs, PXA2xxTimer0),
	443	VMSTATE_INT32(oldclock, PXA2xxTimer4),
	444	VMSTATE_INT32(clock, PXA2xxTimer4),
	445	VMSTATE_UINT64(lastload, PXA2xxTimer4),
	446	VMSTATE_UINT32(freq, PXA2xxTimer4),
	447	VMSTATE_UINT32(control, PXA2xxTimer4),
	448	VMSTATE_END_OF_LIST(),
	449	},
	450	};
	451
	452	static bool pxa2xx_timer_has_tm4_test(void *opaque, int version_id)
a171fe39	453	{
797e9542	454	return pxa2xx_timer_has_tm4(opaque);
a171fe39 AZ	455	}
a171fe39 AZ	456
797e9542 DES	457	static const VMStateDescription vmstate_pxa2xx_timer_regs = {
	458	.name = "pxa2xx_timer",
	459	.version_id = 1,
	460	.minimum_version_id = 1,
	461	.minimum_version_id_old = 1,
	462	.post_load = pxa25x_timer_post_load,
	463	.fields = (VMStateField[]) {
	464	VMSTATE_INT32(clock, PXA2xxTimerInfo),
	465	VMSTATE_INT32(oldclock, PXA2xxTimerInfo),
	466	VMSTATE_UINT64(lastload, PXA2xxTimerInfo),
	467	VMSTATE_STRUCT_ARRAY(timer, PXA2xxTimerInfo, 4, 1,
	468	vmstate_pxa2xx_timer0_regs, PXA2xxTimer0),
	469	VMSTATE_UINT32(events, PXA2xxTimerInfo),
	470	VMSTATE_UINT32(irq_enabled, PXA2xxTimerInfo),
	471	VMSTATE_UINT32(reset3, PXA2xxTimerInfo),
	472	VMSTATE_UINT32(snapshot, PXA2xxTimerInfo),
	473	VMSTATE_STRUCT_ARRAY_TEST(tm4, PXA2xxTimerInfo, 8,
	474	pxa2xx_timer_has_tm4_test, 0,
	475	vmstate_pxa2xx_timer4_regs, PXA2xxTimer4),
	476	VMSTATE_END_OF_LIST(),
a171fe39	477	}
797e9542 DES	478	};
797e9542 DES	479
999e12bb AL	480	static Property pxa25x_timer_dev_properties[] = {
	481	DEFINE_PROP_UINT32("freq", PXA2xxTimerInfo, freq, PXA25X_FREQ),
	482	DEFINE_PROP_BIT("tm4", PXA2xxTimerInfo, flags,
	483	PXA2XX_TIMER_HAVE_TM4, false),
	484	DEFINE_PROP_END_OF_LIST(),
797e9542 DES	485	};
797e9542 DES	486
999e12bb AL	487	static void pxa25x_timer_dev_class_init(ObjectClass klass, void data)
999e12bb AL	488	{
39bffca2	489	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb AL	490	SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
	491
	492	k->init = pxa2xx_timer_init;
39bffca2 AL	493	dc->desc = "PXA25x timer";
	494	dc->vmsd = &vmstate_pxa2xx_timer_regs;
	495	dc->props = pxa25x_timer_dev_properties;
999e12bb AL	496	}
999e12bb AL	497
39bffca2 AL	498	static TypeInfo pxa25x_timer_dev_info = {
	499	.name = "pxa25x-timer",
	500	.parent = TYPE_SYS_BUS_DEVICE,
	501	.instance_size = sizeof(PXA2xxTimerInfo),
	502	.class_init = pxa25x_timer_dev_class_init,
999e12bb AL	503	};
	504
	505	static Property pxa27x_timer_dev_properties[] = {
	506	DEFINE_PROP_UINT32("freq", PXA2xxTimerInfo, freq, PXA27X_FREQ),
	507	DEFINE_PROP_BIT("tm4", PXA2xxTimerInfo, flags,
	508	PXA2XX_TIMER_HAVE_TM4, true),
	509	DEFINE_PROP_END_OF_LIST(),
	510	};
	511
	512	static void pxa27x_timer_dev_class_init(ObjectClass klass, void data)
	513	{
39bffca2	514	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb AL	515	SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
	516
	517	k->init = pxa2xx_timer_init;
39bffca2 AL	518	dc->desc = "PXA27x timer";
	519	dc->vmsd = &vmstate_pxa2xx_timer_regs;
	520	dc->props = pxa27x_timer_dev_properties;
999e12bb AL	521	}
999e12bb AL	522
39bffca2 AL	523	static TypeInfo pxa27x_timer_dev_info = {
	524	.name = "pxa27x-timer",
	525	.parent = TYPE_SYS_BUS_DEVICE,
	526	.instance_size = sizeof(PXA2xxTimerInfo),
	527	.class_init = pxa27x_timer_dev_class_init,
797e9542 DES	528	};
797e9542 DES	529
83f7d43a	530	static void pxa2xx_timer_register_types(void)
797e9542	531	{
39bffca2 AL	532	type_register_static(&pxa25x_timer_dev_info);
39bffca2 AL	533	type_register_static(&pxa27x_timer_dev_info);
83f7d43a AF	534	}
	535
	536	type_init(pxa2xx_timer_register_types)