[qemu.git] / hw / ppc / ppc405_boards.c

/*
 * QEMU PowerPC 405 evaluation boards emulation
 *
 * Copyright (c) 2007 Jocelyn Mayer
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "qemu/osdep.h"
#include "qemu/units.h"
#include "qapi/error.h"
#include "qemu-common.h"
#include "cpu.h"
#include "hw/hw.h"
#include "hw/ppc/ppc.h"
#include "ppc405.h"
#include "hw/timer/m48t59.h"
#include "hw/block/flash.h"
#include "sysemu/sysemu.h"
#include "sysemu/qtest.h"
#include "sysemu/block-backend.h"
#include "hw/boards.h"
#include "qemu/log.h"
#include "qemu/error-report.h"
#include "hw/loader.h"
#include "exec/address-spaces.h"

#define BIOS_FILENAME "ppc405_rom.bin"
#define BIOS_SIZE (2 * MiB)

#define KERNEL_LOAD_ADDR 0x00000000
#define INITRD_LOAD_ADDR 0x01800000

#define USE_FLASH_BIOS

/*****************************************************************************/
/* PPC405EP reference board (IBM) */
/* Standalone board with:
 * - PowerPC 405EP CPU
 * - SDRAM (0x00000000)
 * - Flash (0xFFF80000)
 * - SRAM  (0xFFF00000)
 * - NVRAM (0xF0000000)
 * - FPGA  (0xF0300000)
 */
typedef struct ref405ep_fpga_t ref405ep_fpga_t;
struct ref405ep_fpga_t {
    uint8_t reg0;
    uint8_t reg1;
};

static uint64_t ref405ep_fpga_readb(void *opaque, hwaddr addr, unsigned size)
{
    ref405ep_fpga_t *fpga;
    uint32_t ret;

    fpga = opaque;
    switch (addr) {
    case 0x0:
        ret = fpga->reg0;
        break;
    case 0x1:
        ret = fpga->reg1;
        break;
    default:
        ret = 0;
        break;
    }

    return ret;
}

static void ref405ep_fpga_writeb(void *opaque, hwaddr addr, uint64_t value,
                                 unsigned size)
{
    ref405ep_fpga_t *fpga;

    fpga = opaque;
    switch (addr) {
    case 0x0:
        /* Read only */
        break;
    case 0x1:
        fpga->reg1 = value;
        break;
    default:
        break;
    }
}

static const MemoryRegionOps ref405ep_fpga_ops = {
    .read = ref405ep_fpga_readb,
    .write = ref405ep_fpga_writeb,
    .impl.min_access_size = 1,
    .impl.max_access_size = 1,
    .valid.min_access_size = 1,
    .valid.max_access_size = 4,
    .endianness = DEVICE_BIG_ENDIAN,
};

static void ref405ep_fpga_reset (void *opaque)
{
    ref405ep_fpga_t *fpga;

    fpga = opaque;
    fpga->reg0 = 0x00;
    fpga->reg1 = 0x0F;
}

static void ref405ep_fpga_init(MemoryRegion *sysmem, uint32_t base)
{
    ref405ep_fpga_t *fpga;
    MemoryRegion *fpga_memory = g_new(MemoryRegion, 1);

    fpga = g_malloc0(sizeof(ref405ep_fpga_t));
    memory_region_init_io(fpga_memory, NULL, &ref405ep_fpga_ops, fpga,
                          "fpga", 0x00000100);
    memory_region_add_subregion(sysmem, base, fpga_memory);
    qemu_register_reset(&ref405ep_fpga_reset, fpga);
}

static void ref405ep_init(MachineState *machine)
{
    ram_addr_t ram_size = machine->ram_size;
    const char *kernel_filename = machine->kernel_filename;
    const char *kernel_cmdline = machine->kernel_cmdline;
    const char *initrd_filename = machine->initrd_filename;
    char *filename;
    ppc4xx_bd_info_t bd;
    CPUPPCState *env;
    qemu_irq *pic;
    MemoryRegion *bios;
    MemoryRegion *sram = g_new(MemoryRegion, 1);
    ram_addr_t bdloc;
    MemoryRegion *ram_memories = g_new(MemoryRegion, 2);
    hwaddr ram_bases[2], ram_sizes[2];
    target_ulong sram_size;
    long bios_size;
    //int phy_addr = 0;
    //static int phy_addr = 1;
    target_ulong kernel_base, initrd_base;
    long kernel_size, initrd_size;
    int linux_boot;
    int len;
    DriveInfo *dinfo;
    MemoryRegion *sysmem = get_system_memory();

    /* XXX: fix this */
    memory_region_allocate_system_memory(&ram_memories[0], NULL, "ef405ep.ram",
                                         0x08000000);
    ram_bases[0] = 0;
    ram_sizes[0] = 0x08000000;
    memory_region_init(&ram_memories[1], NULL, "ef405ep.ram1", 0);
    ram_bases[1] = 0x00000000;
    ram_sizes[1] = 0x00000000;
    ram_size = 128 * MiB;
    env = ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes,
                        33333333, &pic, kernel_filename == NULL ? 0 : 1);
    /* allocate SRAM */
    sram_size = 512 * KiB;
    memory_region_init_ram(sram, NULL, "ef405ep.sram", sram_size,
                           &error_fatal);
    memory_region_add_subregion(sysmem, 0xFFF00000, sram);
    /* allocate and load BIOS */
#ifdef USE_FLASH_BIOS
    dinfo = drive_get(IF_PFLASH, 0, 0);
    if (dinfo) {
        bios_size = 8 * MiB;
        pflash_cfi02_register((uint32_t)(-bios_size),
                              "ef405ep.bios", bios_size,
                              dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
                              64 * KiB, 1,
                              2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
                              1);
    } else
#endif
    {
        bios = g_new(MemoryRegion, 1);
        memory_region_init_ram(bios, NULL, "ef405ep.bios", BIOS_SIZE,
                               &error_fatal);

        if (bios_name == NULL)
            bios_name = BIOS_FILENAME;
        filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
        if (filename) {
            bios_size = load_image_size(filename,
                                        memory_region_get_ram_ptr(bios),
                                        BIOS_SIZE);
            g_free(filename);
            if (bios_size < 0) {
                error_report("Could not load PowerPC BIOS '%s'", bios_name);
                exit(1);
            }
            bios_size = (bios_size + 0xfff) & ~0xfff;
            memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios);
        } else if (!qtest_enabled() || kernel_filename != NULL) {
            error_report("Could not load PowerPC BIOS '%s'", bios_name);
            exit(1);
        } else {
            /* Avoid an uninitialized variable warning */
            bios_size = -1;
        }
        memory_region_set_readonly(bios, true);
    }
    /* Register FPGA */
    ref405ep_fpga_init(sysmem, 0xF0300000);
    /* Register NVRAM */
    m48t59_init(NULL, 0xF0000000, 0, 8192, 1968, 8);
    /* Load kernel */
    linux_boot = (kernel_filename != NULL);
    if (linux_boot) {
        memset(&bd, 0, sizeof(bd));
        bd.bi_memstart = 0x00000000;
        bd.bi_memsize = ram_size;
        bd.bi_flashstart = -bios_size;
        bd.bi_flashsize = -bios_size;
        bd.bi_flashoffset = 0;
        bd.bi_sramstart = 0xFFF00000;
        bd.bi_sramsize = sram_size;
        bd.bi_bootflags = 0;
        bd.bi_intfreq = 133333333;
        bd.bi_busfreq = 33333333;
        bd.bi_baudrate = 115200;
        bd.bi_s_version[0] = 'Q';
        bd.bi_s_version[1] = 'M';
        bd.bi_s_version[2] = 'U';
        bd.bi_s_version[3] = '\0';
        bd.bi_r_version[0] = 'Q';
        bd.bi_r_version[1] = 'E';
        bd.bi_r_version[2] = 'M';
        bd.bi_r_version[3] = 'U';
        bd.bi_r_version[4] = '\0';
        bd.bi_procfreq = 133333333;
        bd.bi_plb_busfreq = 33333333;
        bd.bi_pci_busfreq = 33333333;
        bd.bi_opbfreq = 33333333;
        bdloc = ppc405_set_bootinfo(env, &bd, 0x00000001);
        env->gpr[3] = bdloc;
        kernel_base = KERNEL_LOAD_ADDR;
        /* now we can load the kernel */
        kernel_size = load_image_targphys(kernel_filename, kernel_base,
                                          ram_size - kernel_base);
        if (kernel_size < 0) {
            error_report("could not load kernel '%s'", kernel_filename);
            exit(1);
        }
        printf("Load kernel size %ld at " TARGET_FMT_lx,
               kernel_size, kernel_base);
        /* load initrd */
        if (initrd_filename) {
            initrd_base = INITRD_LOAD_ADDR;
            initrd_size = load_image_targphys(initrd_filename, initrd_base,
                                              ram_size - initrd_base);
            if (initrd_size < 0) {
                error_report("could not load initial ram disk '%s'",
                             initrd_filename);
                exit(1);
            }
        } else {
            initrd_base = 0;
            initrd_size = 0;
        }
        env->gpr[4] = initrd_base;
        env->gpr[5] = initrd_size;
        if (kernel_cmdline != NULL) {
            len = strlen(kernel_cmdline);
            bdloc -= ((len + 255) & ~255);
            cpu_physical_memory_write(bdloc, kernel_cmdline, len + 1);
            env->gpr[6] = bdloc;
            env->gpr[7] = bdloc + len;
        } else {
            env->gpr[6] = 0;
            env->gpr[7] = 0;
        }
        env->nip = KERNEL_LOAD_ADDR;
    } else {
        kernel_base = 0;
        kernel_size = 0;
        initrd_base = 0;
        initrd_size = 0;
        bdloc = 0;
    }
}

static void ref405ep_class_init(ObjectClass *oc, void *data)
{
    MachineClass *mc = MACHINE_CLASS(oc);

    mc->desc = "ref405ep";
    mc->init = ref405ep_init;
}

static const TypeInfo ref405ep_type = {
    .name = MACHINE_TYPE_NAME("ref405ep"),
    .parent = TYPE_MACHINE,
    .class_init = ref405ep_class_init,
};

/*****************************************************************************/
/* AMCC Taihu evaluation board */
/* - PowerPC 405EP processor
 * - SDRAM               128 MB at 0x00000000
 * - Boot flash          2 MB   at 0xFFE00000
 * - Application flash   32 MB  at 0xFC000000
 * - 2 serial ports
 * - 2 ethernet PHY
 * - 1 USB 1.1 device    0x50000000
 * - 1 LCD display       0x50100000
 * - 1 CPLD              0x50100000
 * - 1 I2C EEPROM
 * - 1 I2C thermal sensor
 * - a set of LEDs
 * - bit-bang SPI port using GPIOs
 * - 1 EBC interface connector 0 0x50200000
 * - 1 cardbus controller + expansion slot.
 * - 1 PCI expansion slot.
 */
typedef struct taihu_cpld_t taihu_cpld_t;
struct taihu_cpld_t {
    uint8_t reg0;
    uint8_t reg1;
};

static uint64_t taihu_cpld_read(void *opaque, hwaddr addr, unsigned size)
{
    taihu_cpld_t *cpld;
    uint32_t ret;

    cpld = opaque;
    switch (addr) {
    case 0x0:
        ret = cpld->reg0;
        break;
    case 0x1:
        ret = cpld->reg1;
        break;
    default:
        ret = 0;
        break;
    }

    return ret;
}

static void taihu_cpld_write(void *opaque, hwaddr addr,
                             uint64_t value, unsigned size)
{
    taihu_cpld_t *cpld;

    cpld = opaque;
    switch (addr) {
    case 0x0:
        /* Read only */
        break;
    case 0x1:
        cpld->reg1 = value;
        break;
    default:
        break;
    }
}

static const MemoryRegionOps taihu_cpld_ops = {
    .read = taihu_cpld_read,
    .write = taihu_cpld_write,
    .impl = {
        .min_access_size = 1,
        .max_access_size = 1,
    },
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static void taihu_cpld_reset (void *opaque)
{
    taihu_cpld_t *cpld;

    cpld = opaque;
    cpld->reg0 = 0x01;
    cpld->reg1 = 0x80;
}

static void taihu_cpld_init(MemoryRegion *sysmem, uint32_t base)
{
    taihu_cpld_t *cpld;
    MemoryRegion *cpld_memory = g_new(MemoryRegion, 1);

    cpld = g_malloc0(sizeof(taihu_cpld_t));
    memory_region_init_io(cpld_memory, NULL, &taihu_cpld_ops, cpld, "cpld", 0x100);
    memory_region_add_subregion(sysmem, base, cpld_memory);
    qemu_register_reset(&taihu_cpld_reset, cpld);
}

static void taihu_405ep_init(MachineState *machine)
{
    ram_addr_t ram_size = machine->ram_size;
    const char *kernel_filename = machine->kernel_filename;
    const char *initrd_filename = machine->initrd_filename;
    char *filename;
    qemu_irq *pic;
    MemoryRegion *sysmem = get_system_memory();
    MemoryRegion *bios;
    MemoryRegion *ram_memories = g_new(MemoryRegion, 2);
    MemoryRegion *ram = g_malloc0(sizeof(*ram));
    hwaddr ram_bases[2], ram_sizes[2];
    long bios_size;
    target_ulong kernel_base, initrd_base;
    long kernel_size, initrd_size;
    int linux_boot;
    int fl_idx;
    DriveInfo *dinfo;

    /* RAM is soldered to the board so the size cannot be changed */
    ram_size = 0x08000000;
    memory_region_allocate_system_memory(ram, NULL, "taihu_405ep.ram",
                                         ram_size);

    ram_bases[0] = 0;
    ram_sizes[0] = 0x04000000;
    memory_region_init_alias(&ram_memories[0], NULL,
                             "taihu_405ep.ram-0", ram, ram_bases[0],
                             ram_sizes[0]);
    ram_bases[1] = 0x04000000;
    ram_sizes[1] = 0x04000000;
    memory_region_init_alias(&ram_memories[1], NULL,
                             "taihu_405ep.ram-1", ram, ram_bases[1],
                             ram_sizes[1]);
    ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes,
                  33333333, &pic, kernel_filename == NULL ? 0 : 1);
    /* allocate and load BIOS */
    fl_idx = 0;
#if defined(USE_FLASH_BIOS)
    dinfo = drive_get(IF_PFLASH, 0, fl_idx);
    if (dinfo) {
        bios_size = 2 * MiB;
        pflash_cfi02_register(0xFFE00000,
                              "taihu_405ep.bios", bios_size,
                              dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
                              64 * KiB, 1,
                              4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
                              1);
        fl_idx++;
    } else
#endif
    {
        if (bios_name == NULL)
            bios_name = BIOS_FILENAME;
        bios = g_new(MemoryRegion, 1);
        memory_region_init_ram(bios, NULL, "taihu_405ep.bios", BIOS_SIZE,
                               &error_fatal);
        filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
        if (filename) {
            bios_size = load_image_size(filename,
                                        memory_region_get_ram_ptr(bios),
                                        BIOS_SIZE);
            g_free(filename);
            if (bios_size < 0) {
                error_report("Could not load PowerPC BIOS '%s'", bios_name);
                exit(1);
            }
            bios_size = (bios_size + 0xfff) & ~0xfff;
            memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios);
        } else if (!qtest_enabled()) {
            error_report("Could not load PowerPC BIOS '%s'", bios_name);
            exit(1);
        }
        memory_region_set_readonly(bios, true);
    }
    /* Register Linux flash */
    dinfo = drive_get(IF_PFLASH, 0, fl_idx);
    if (dinfo) {
        bios_size = 32 * MiB;
        pflash_cfi02_register(0xfc000000, "taihu_405ep.flash", bios_size,
                              dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
                              64 * KiB, 1,
                              4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
                              1);
        fl_idx++;
    }
    /* Register CLPD & LCD display */
    taihu_cpld_init(sysmem, 0x50100000);
    /* Load kernel */
    linux_boot = (kernel_filename != NULL);
    if (linux_boot) {
        kernel_base = KERNEL_LOAD_ADDR;
        /* now we can load the kernel */
        kernel_size = load_image_targphys(kernel_filename, kernel_base,
                                          ram_size - kernel_base);
        if (kernel_size < 0) {
            error_report("could not load kernel '%s'", kernel_filename);
            exit(1);
        }
        /* load initrd */
        if (initrd_filename) {
            initrd_base = INITRD_LOAD_ADDR;
            initrd_size = load_image_targphys(initrd_filename, initrd_base,
                                              ram_size - initrd_base);
            if (initrd_size < 0) {
                error_report("could not load initial ram disk '%s'",
                             initrd_filename);
                exit(1);
            }
        } else {
            initrd_base = 0;
            initrd_size = 0;
        }
    } else {
        kernel_base = 0;
        kernel_size = 0;
        initrd_base = 0;
        initrd_size = 0;
    }
}

static void taihu_class_init(ObjectClass *oc, void *data)
{
    MachineClass *mc = MACHINE_CLASS(oc);

    mc->desc = "taihu";
    mc->init = taihu_405ep_init;
}

static const TypeInfo taihu_type = {
    .name = MACHINE_TYPE_NAME("taihu"),
    .parent = TYPE_MACHINE,
    .class_init = taihu_class_init,
};

static void ppc405_machine_init(void)
{
    type_register_static(&ref405ep_type);
    type_register_static(&taihu_type);
}

type_init(ppc405_machine_init)
Commit	Line	Data
1a6c0886 JM	1	/*
1a6c0886 JM	2	* QEMU PowerPC 405 evaluation boards emulation
5fafdf24	3	*
1a6c0886	4	* Copyright (c) 2007 Jocelyn Mayer
5fafdf24	5	*
1a6c0886 JM	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
0d75590d	24	#include "qemu/osdep.h"
ab3dd749	25	#include "qemu/units.h"
da34e65c	26	#include "qapi/error.h"
4771d756 PB	27	#include "qemu-common.h"
4771d756 PB	28	#include "cpu.h"
83c9f4ca	29	#include "hw/hw.h"
0d09e41a	30	#include "hw/ppc/ppc.h"
47b43a1f	31	#include "ppc405.h"
0d09e41a PB	32	#include "hw/timer/m48t59.h"
0d09e41a PB	33	#include "hw/block/flash.h"
9c17d615	34	#include "sysemu/sysemu.h"
ad9990ac	35	#include "sysemu/qtest.h"
4be74634	36	#include "sysemu/block-backend.h"
83c9f4ca	37	#include "hw/boards.h"
1de7afc9	38	#include "qemu/log.h"
ad9990ac	39	#include "qemu/error-report.h"
83c9f4ca	40	#include "hw/loader.h"
022c62cb	41	#include "exec/address-spaces.h"
1a6c0886 JM	42
1a6c0886 JM	43	#define BIOS_FILENAME "ppc405_rom.bin"
ab3dd749	44	#define BIOS_SIZE (2 * MiB)
1a6c0886 JM	45
	46	#define KERNEL_LOAD_ADDR 0x00000000
	47	#define INITRD_LOAD_ADDR 0x01800000
	48
	49	#define USE_FLASH_BIOS
	50
1a6c0886 JM	51	/*****************************************************************************/
	52	/* PPC405EP reference board (IBM) */
	53	/* Standalone board with:
	54	* - PowerPC 405EP CPU
	55	* - SDRAM (0x00000000)
	56	* - Flash (0xFFF80000)
	57	* - SRAM (0xFFF00000)
	58	* - NVRAM (0xF0000000)
	59	* - FPGA (0xF0300000)
	60	*/
c227f099 AL	61	typedef struct ref405ep_fpga_t ref405ep_fpga_t;
c227f099 AL	62	struct ref405ep_fpga_t {
1a6c0886 JM	63	uint8_t reg0;
	64	uint8_t reg1;
	65	};
	66
878a4607	67	static uint64_t ref405ep_fpga_readb(void *opaque, hwaddr addr, unsigned size)
1a6c0886	68	{
c227f099	69	ref405ep_fpga_t *fpga;
1a6c0886 JM	70	uint32_t ret;
	71
	72	fpga = opaque;
1a6c0886 JM	73	switch (addr) {
	74	case 0x0:
	75	ret = fpga->reg0;
	76	break;
	77	case 0x1:
	78	ret = fpga->reg1;
	79	break;
	80	default:
	81	ret = 0;
	82	break;
	83	}
	84
	85	return ret;
	86	}
	87
878a4607 PM	88	static void ref405ep_fpga_writeb(void *opaque, hwaddr addr, uint64_t value,
878a4607 PM	89	unsigned size)
1a6c0886	90	{
c227f099	91	ref405ep_fpga_t *fpga;
1a6c0886 JM	92
1a6c0886 JM	93	fpga = opaque;
1a6c0886 JM	94	switch (addr) {
	95	case 0x0:
	96	/* Read only */
	97	break;
	98	case 0x1:
	99	fpga->reg1 = value;
	100	break;
	101	default:
	102	break;
	103	}
	104	}
	105
a682fd5c	106	static const MemoryRegionOps ref405ep_fpga_ops = {
878a4607 PM	107	.read = ref405ep_fpga_readb,
	108	.write = ref405ep_fpga_writeb,
	109	.impl.min_access_size = 1,
	110	.impl.max_access_size = 1,
	111	.valid.min_access_size = 1,
	112	.valid.max_access_size = 4,
	113	.endianness = DEVICE_BIG_ENDIAN,
1a6c0886 JM	114	};
	115
	116	static void ref405ep_fpga_reset (void *opaque)
	117	{
c227f099	118	ref405ep_fpga_t *fpga;
1a6c0886 JM	119
	120	fpga = opaque;
	121	fpga->reg0 = 0x00;
	122	fpga->reg1 = 0x0F;
	123	}
	124
5f072e1f	125	static void ref405ep_fpga_init(MemoryRegion *sysmem, uint32_t base)
1a6c0886	126	{
c227f099	127	ref405ep_fpga_t *fpga;
a682fd5c	128	MemoryRegion *fpga_memory = g_new(MemoryRegion, 1);
1a6c0886	129
7267c094	130	fpga = g_malloc0(sizeof(ref405ep_fpga_t));
2c9b15ca	131	memory_region_init_io(fpga_memory, NULL, &ref405ep_fpga_ops, fpga,
a682fd5c AK	132	"fpga", 0x00000100);
a682fd5c AK	133	memory_region_add_subregion(sysmem, base, fpga_memory);
a08d4367	134	qemu_register_reset(&ref405ep_fpga_reset, fpga);
1a6c0886 JM	135	}
1a6c0886 JM	136
3ef96221	137	static void ref405ep_init(MachineState *machine)
1a6c0886	138	{
3ef96221 MA	139	ram_addr_t ram_size = machine->ram_size;
	140	const char *kernel_filename = machine->kernel_filename;
	141	const char *kernel_cmdline = machine->kernel_cmdline;
	142	const char *initrd_filename = machine->initrd_filename;
5cea8590	143	char *filename;
c227f099	144	ppc4xx_bd_info_t bd;
1a6c0886 JM	145	CPUPPCState *env;
1a6c0886 JM	146	qemu_irq *pic;
cfe5f011	147	MemoryRegion *bios;
a682fd5c AK	148	MemoryRegion *sram = g_new(MemoryRegion, 1);
a682fd5c AK	149	ram_addr_t bdloc;
779db4c7	150	MemoryRegion *ram_memories = g_new(MemoryRegion, 2);
a8170e5e	151	hwaddr ram_bases[2], ram_sizes[2];
093209cd BS	152	target_ulong sram_size;
093209cd BS	153	long bios_size;
1a6c0886 JM	154	//int phy_addr = 0;
1a6c0886 JM	155	//static int phy_addr = 1;
093209cd BS	156	target_ulong kernel_base, initrd_base;
093209cd BS	157	long kernel_size, initrd_size;
1a6c0886	158	int linux_boot;
dd59bcae	159	int len;
751c6a17	160	DriveInfo *dinfo;
a682fd5c	161	MemoryRegion *sysmem = get_system_memory();
1a6c0886 JM	162
1a6c0886 JM	163	/* XXX: fix this */
e938ba0c SP	164	memory_region_allocate_system_memory(&ram_memories[0], NULL, "ef405ep.ram",
e938ba0c SP	165	0x08000000);
b6dcbe08	166	ram_bases[0] = 0;
1a6c0886	167	ram_sizes[0] = 0x08000000;
2c9b15ca	168	memory_region_init(&ram_memories[1], NULL, "ef405ep.ram1", 0);
1a6c0886 JM	169	ram_bases[1] = 0x00000000;
1a6c0886 JM	170	ram_sizes[1] = 0x00000000;
ab3dd749	171	ram_size = 128 * MiB;
a682fd5c	172	env = ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes,
52ce55a1	173	33333333, &pic, kernel_filename == NULL ? 0 : 1);
1a6c0886	174	/* allocate SRAM */
ab3dd749	175	sram_size = 512 * KiB;
98a99ce0	176	memory_region_init_ram(sram, NULL, "ef405ep.sram", sram_size,
f8ed85ac	177	&error_fatal);
a682fd5c	178	memory_region_add_subregion(sysmem, 0xFFF00000, sram);
1a6c0886	179	/* allocate and load BIOS */
1a6c0886	180	#ifdef USE_FLASH_BIOS
dd59bcae	181	dinfo = drive_get(IF_PFLASH, 0, 0);
751c6a17	182	if (dinfo) {
dd59bcae	183	bios_size = 8 * MiB;
cfe5f011	184	pflash_cfi02_register((uint32_t)(-bios_size),
940d5b13	185	"ef405ep.bios", bios_size,
dd59bcae	186	dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
ce14710f	187	64 * KiB, 1,
01e0451a AL	188	2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
01e0451a AL	189	1);
1a6c0886 JM	190	} else
	191	#endif
	192	{
cfe5f011	193	bios = g_new(MemoryRegion, 1);
98a99ce0	194	memory_region_init_ram(bios, NULL, "ef405ep.bios", BIOS_SIZE,
f8ed85ac	195	&error_fatal);
e206ad48	196
1192dad8 JM	197	if (bios_name == NULL)
1192dad8 JM	198	bios_name = BIOS_FILENAME;
5cea8590 PB	199	filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
5cea8590 PB	200	if (filename) {
214b63cd PM	201	bios_size = load_image_size(filename,
	202	memory_region_get_ram_ptr(bios),
	203	BIOS_SIZE);
7267c094	204	g_free(filename);
214b63cd	205	if (bios_size < 0) {
ad9990ac AF	206	error_report("Could not load PowerPC BIOS '%s'", bios_name);
	207	exit(1);
	208	}
	209	bios_size = (bios_size + 0xfff) & ~0xfff;
	210	memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios);
	211	} else if (!qtest_enabled() \|\| kernel_filename != NULL) {
	212	error_report("Could not load PowerPC BIOS '%s'", bios_name);
	213	exit(1);
5cea8590	214	} else {
ad9990ac	215	/* Avoid an uninitialized variable warning */
5cea8590 PB	216	bios_size = -1;
5cea8590 PB	217	}
cfe5f011	218	memory_region_set_readonly(bios, true);
1a6c0886	219	}
1a6c0886	220	/* Register FPGA */
a682fd5c	221	ref405ep_fpga_init(sysmem, 0xF0300000);
1a6c0886	222	/* Register NVRAM */
6de04973	223	m48t59_init(NULL, 0xF0000000, 0, 8192, 1968, 8);
1a6c0886 JM	224	/* Load kernel */
	225	linux_boot = (kernel_filename != NULL);
	226	if (linux_boot) {
1a6c0886 JM	227	memset(&bd, 0, sizeof(bd));
	228	bd.bi_memstart = 0x00000000;
	229	bd.bi_memsize = ram_size;
217fae2d	230	bd.bi_flashstart = -bios_size;
1a6c0886 JM	231	bd.bi_flashsize = -bios_size;
	232	bd.bi_flashoffset = 0;
	233	bd.bi_sramstart = 0xFFF00000;
	234	bd.bi_sramsize = sram_size;
	235	bd.bi_bootflags = 0;
	236	bd.bi_intfreq = 133333333;
	237	bd.bi_busfreq = 33333333;
	238	bd.bi_baudrate = 115200;
	239	bd.bi_s_version[0] = 'Q';
	240	bd.bi_s_version[1] = 'M';
	241	bd.bi_s_version[2] = 'U';
	242	bd.bi_s_version[3] = '\0';
	243	bd.bi_r_version[0] = 'Q';
	244	bd.bi_r_version[1] = 'E';
	245	bd.bi_r_version[2] = 'M';
	246	bd.bi_r_version[3] = 'U';
	247	bd.bi_r_version[4] = '\0';
	248	bd.bi_procfreq = 133333333;
	249	bd.bi_plb_busfreq = 33333333;
	250	bd.bi_pci_busfreq = 33333333;
	251	bd.bi_opbfreq = 33333333;
b8d3f5d1	252	bdloc = ppc405_set_bootinfo(env, &bd, 0x00000001);
1a6c0886 JM	253	env->gpr[3] = bdloc;
	254	kernel_base = KERNEL_LOAD_ADDR;
	255	/* now we can load the kernel */
5c130f65 PB	256	kernel_size = load_image_targphys(kernel_filename, kernel_base,
5c130f65 PB	257	ram_size - kernel_base);
1a6c0886	258	if (kernel_size < 0) {
6f76b817	259	error_report("could not load kernel '%s'", kernel_filename);
1a6c0886 JM	260	exit(1);
1a6c0886 JM	261	}
093209cd	262	printf("Load kernel size %ld at " TARGET_FMT_lx,
5c130f65	263	kernel_size, kernel_base);
1a6c0886 JM	264	/* load initrd */
	265	if (initrd_filename) {
	266	initrd_base = INITRD_LOAD_ADDR;
5c130f65 PB	267	initrd_size = load_image_targphys(initrd_filename, initrd_base,
5c130f65 PB	268	ram_size - initrd_base);
1a6c0886	269	if (initrd_size < 0) {
6f76b817 AF	270	error_report("could not load initial ram disk '%s'",
6f76b817 AF	271	initrd_filename);
1a6c0886 JM	272	exit(1);
	273	}
	274	} else {
	275	initrd_base = 0;
	276	initrd_size = 0;
	277	}
	278	env->gpr[4] = initrd_base;
	279	env->gpr[5] = initrd_size;
1a6c0886 JM	280	if (kernel_cmdline != NULL) {
	281	len = strlen(kernel_cmdline);
	282	bdloc -= ((len + 255) & ~255);
e1fe50dc	283	cpu_physical_memory_write(bdloc, kernel_cmdline, len + 1);
1a6c0886 JM	284	env->gpr[6] = bdloc;
	285	env->gpr[7] = bdloc + len;
	286	} else {
	287	env->gpr[6] = 0;
	288	env->gpr[7] = 0;
	289	}
	290	env->nip = KERNEL_LOAD_ADDR;
	291	} else {
	292	kernel_base = 0;
	293	kernel_size = 0;
	294	initrd_base = 0;
	295	initrd_size = 0;
	296	bdloc = 0;
	297	}
1a6c0886 JM	298	}
1a6c0886 JM	299
8a661aea	300	static void ref405ep_class_init(ObjectClass oc, void data)
e264d29d	301	{
8a661aea AF	302	MachineClass *mc = MACHINE_CLASS(oc);
8a661aea AF	303
e264d29d EH	304	mc->desc = "ref405ep";
	305	mc->init = ref405ep_init;
	306	}
	307
8a661aea AF	308	static const TypeInfo ref405ep_type = {
	309	.name = MACHINE_TYPE_NAME("ref405ep"),
	310	.parent = TYPE_MACHINE,
	311	.class_init = ref405ep_class_init,
	312	};
1a6c0886 JM	313
	314	/*****************************************************************************/
	315	/* AMCC Taihu evaluation board */
	316	/* - PowerPC 405EP processor
	317	* - SDRAM 128 MB at 0x00000000
	318	* - Boot flash 2 MB at 0xFFE00000
	319	* - Application flash 32 MB at 0xFC000000
	320	* - 2 serial ports
	321	* - 2 ethernet PHY
	322	* - 1 USB 1.1 device 0x50000000
	323	* - 1 LCD display 0x50100000
	324	* - 1 CPLD 0x50100000
	325	* - 1 I2C EEPROM
	326	* - 1 I2C thermal sensor
	327	* - a set of LEDs
	328	* - bit-bang SPI port using GPIOs
	329	* - 1 EBC interface connector 0 0x50200000
	330	* - 1 cardbus controller + expansion slot.
	331	* - 1 PCI expansion slot.
	332	*/
	333	typedef struct taihu_cpld_t taihu_cpld_t;
	334	struct taihu_cpld_t {
1a6c0886 JM	335	uint8_t reg0;
	336	uint8_t reg1;
	337	};
	338
e2a176df	339	static uint64_t taihu_cpld_read(void *opaque, hwaddr addr, unsigned size)
1a6c0886 JM	340	{
	341	taihu_cpld_t *cpld;
	342	uint32_t ret;
	343
	344	cpld = opaque;
1a6c0886 JM	345	switch (addr) {
	346	case 0x0:
	347	ret = cpld->reg0;
	348	break;
	349	case 0x1:
	350	ret = cpld->reg1;
	351	break;
	352	default:
	353	ret = 0;
	354	break;
	355	}
	356
	357	return ret;
	358	}
	359
e2a176df PM	360	static void taihu_cpld_write(void *opaque, hwaddr addr,
e2a176df PM	361	uint64_t value, unsigned size)
1a6c0886 JM	362	{
	363	taihu_cpld_t *cpld;
	364
	365	cpld = opaque;
1a6c0886 JM	366	switch (addr) {
	367	case 0x0:
	368	/* Read only */
	369	break;
	370	case 0x1:
	371	cpld->reg1 = value;
	372	break;
	373	default:
	374	break;
	375	}
	376	}
	377
a682fd5c	378	static const MemoryRegionOps taihu_cpld_ops = {
e2a176df PM	379	.read = taihu_cpld_read,
	380	.write = taihu_cpld_write,
	381	.impl = {
	382	.min_access_size = 1,
	383	.max_access_size = 1,
a682fd5c AK	384	},
a682fd5c AK	385	.endianness = DEVICE_NATIVE_ENDIAN,
1a6c0886 JM	386	};
	387
	388	static void taihu_cpld_reset (void *opaque)
	389	{
	390	taihu_cpld_t *cpld;
	391
	392	cpld = opaque;
	393	cpld->reg0 = 0x01;
	394	cpld->reg1 = 0x80;
	395	}
	396
5f072e1f	397	static void taihu_cpld_init(MemoryRegion *sysmem, uint32_t base)
1a6c0886 JM	398	{
1a6c0886 JM	399	taihu_cpld_t *cpld;
a682fd5c	400	MemoryRegion *cpld_memory = g_new(MemoryRegion, 1);
1a6c0886	401
7267c094	402	cpld = g_malloc0(sizeof(taihu_cpld_t));
2c9b15ca	403	memory_region_init_io(cpld_memory, NULL, &taihu_cpld_ops, cpld, "cpld", 0x100);
a682fd5c	404	memory_region_add_subregion(sysmem, base, cpld_memory);
a08d4367	405	qemu_register_reset(&taihu_cpld_reset, cpld);
1a6c0886 JM	406	}
1a6c0886 JM	407
3ef96221	408	static void taihu_405ep_init(MachineState *machine)
1a6c0886	409	{
3ef96221 MA	410	ram_addr_t ram_size = machine->ram_size;
	411	const char *kernel_filename = machine->kernel_filename;
	412	const char *initrd_filename = machine->initrd_filename;
5cea8590	413	char *filename;
1a6c0886	414	qemu_irq *pic;
a682fd5c	415	MemoryRegion *sysmem = get_system_memory();
cfe5f011	416	MemoryRegion *bios;
779db4c7	417	MemoryRegion *ram_memories = g_new(MemoryRegion, 2);
e206ad48	418	MemoryRegion ram = g_malloc0(sizeof(ram));
a8170e5e	419	hwaddr ram_bases[2], ram_sizes[2];
093209cd BS	420	long bios_size;
	421	target_ulong kernel_base, initrd_base;
	422	long kernel_size, initrd_size;
1a6c0886	423	int linux_boot;
dd59bcae	424	int fl_idx;
751c6a17	425	DriveInfo *dinfo;
3b46e624	426
1a6c0886	427	/* RAM is soldered to the board so the size cannot be changed */
e206ad48 HT	428	ram_size = 0x08000000;
	429	memory_region_allocate_system_memory(ram, NULL, "taihu_405ep.ram",
	430	ram_size);
	431
b6dcbe08	432	ram_bases[0] = 0;
1a6c0886	433	ram_sizes[0] = 0x04000000;
e206ad48 HT	434	memory_region_init_alias(&ram_memories[0], NULL,
	435	"taihu_405ep.ram-0", ram, ram_bases[0],
	436	ram_sizes[0]);
b6dcbe08	437	ram_bases[1] = 0x04000000;
1a6c0886	438	ram_sizes[1] = 0x04000000;
e206ad48 HT	439	memory_region_init_alias(&ram_memories[1], NULL,
	440	"taihu_405ep.ram-1", ram, ram_bases[1],
	441	ram_sizes[1]);
a682fd5c	442	ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes,
52ce55a1	443	33333333, &pic, kernel_filename == NULL ? 0 : 1);
1a6c0886	444	/* allocate and load BIOS */
1a6c0886 JM	445	fl_idx = 0;
1a6c0886 JM	446	#if defined(USE_FLASH_BIOS)
751c6a17 GH	447	dinfo = drive_get(IF_PFLASH, 0, fl_idx);
751c6a17 GH	448	if (dinfo) {
dd59bcae MA	449	bios_size = 2 * MiB;
dd59bcae MA	450	pflash_cfi02_register(0xFFE00000,
940d5b13	451	"taihu_405ep.bios", bios_size,
dd59bcae	452	dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
ce14710f	453	64 * KiB, 1,
01e0451a AL	454	4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
01e0451a AL	455	1);
1a6c0886 JM	456	fl_idx++;
	457	} else
	458	#endif
	459	{
1192dad8 JM	460	if (bios_name == NULL)
1192dad8 JM	461	bios_name = BIOS_FILENAME;
cfe5f011	462	bios = g_new(MemoryRegion, 1);
98a99ce0	463	memory_region_init_ram(bios, NULL, "taihu_405ep.bios", BIOS_SIZE,
f8ed85ac	464	&error_fatal);
5cea8590 PB	465	filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
5cea8590 PB	466	if (filename) {
214b63cd PM	467	bios_size = load_image_size(filename,
	468	memory_region_get_ram_ptr(bios),
	469	BIOS_SIZE);
7267c094	470	g_free(filename);
214b63cd	471	if (bios_size < 0) {
ad9990ac AF	472	error_report("Could not load PowerPC BIOS '%s'", bios_name);
	473	exit(1);
	474	}
	475	bios_size = (bios_size + 0xfff) & ~0xfff;
	476	memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios);
	477	} else if (!qtest_enabled()) {
	478	error_report("Could not load PowerPC BIOS '%s'", bios_name);
1a6c0886 JM	479	exit(1);
1a6c0886 JM	480	}
cfe5f011	481	memory_region_set_readonly(bios, true);
1a6c0886	482	}
1a6c0886	483	/* Register Linux flash */
751c6a17 GH	484	dinfo = drive_get(IF_PFLASH, 0, fl_idx);
751c6a17 GH	485	if (dinfo) {
ab3dd749	486	bios_size = 32 * MiB;
940d5b13	487	pflash_cfi02_register(0xfc000000, "taihu_405ep.flash", bios_size,
dd59bcae	488	dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
ce14710f	489	64 * KiB, 1,
01e0451a AL	490	4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
01e0451a AL	491	1);
1a6c0886 JM	492	fl_idx++;
	493	}
	494	/* Register CLPD & LCD display */
a682fd5c	495	taihu_cpld_init(sysmem, 0x50100000);
1a6c0886 JM	496	/* Load kernel */
	497	linux_boot = (kernel_filename != NULL);
	498	if (linux_boot) {
1a6c0886 JM	499	kernel_base = KERNEL_LOAD_ADDR;
1a6c0886 JM	500	/* now we can load the kernel */
5c130f65 PB	501	kernel_size = load_image_targphys(kernel_filename, kernel_base,
5c130f65 PB	502	ram_size - kernel_base);
1a6c0886	503	if (kernel_size < 0) {
6f76b817	504	error_report("could not load kernel '%s'", kernel_filename);
1a6c0886 JM	505	exit(1);
	506	}
	507	/* load initrd */
	508	if (initrd_filename) {
	509	initrd_base = INITRD_LOAD_ADDR;
5c130f65 PB	510	initrd_size = load_image_targphys(initrd_filename, initrd_base,
5c130f65 PB	511	ram_size - initrd_base);
1a6c0886	512	if (initrd_size < 0) {
6f76b817 AF	513	error_report("could not load initial ram disk '%s'",
6f76b817 AF	514	initrd_filename);
1a6c0886 JM	515	exit(1);
	516	}
	517	} else {
	518	initrd_base = 0;
	519	initrd_size = 0;
	520	}
1a6c0886 JM	521	} else {
	522	kernel_base = 0;
	523	kernel_size = 0;
	524	initrd_base = 0;
	525	initrd_size = 0;
	526	}
1a6c0886 JM	527	}
1a6c0886 JM	528
8a661aea	529	static void taihu_class_init(ObjectClass oc, void data)
f80f9ec9	530	{
8a661aea AF	531	MachineClass *mc = MACHINE_CLASS(oc);
8a661aea AF	532
e264d29d EH	533	mc->desc = "taihu";
e264d29d EH	534	mc->init = taihu_405ep_init;
f80f9ec9 AL	535	}
f80f9ec9 AL	536
8a661aea AF	537	static const TypeInfo taihu_type = {
	538	.name = MACHINE_TYPE_NAME("taihu"),
	539	.parent = TYPE_MACHINE,
	540	.class_init = taihu_class_init,
	541	};
	542
	543	static void ppc405_machine_init(void)
	544	{
	545	type_register_static(&ref405ep_type);
	546	type_register_static(&taihu_type);
	547	}
	548
0e6aac87	549	type_init(ppc405_machine_init)