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ppc/pnv: add a LPC Controller model for POWER10
[qemu.git] / hw / ppc / pnv.c
CommitLineData
9e933f4a
BH		 1/*
2 * QEMU PowerPC PowerNV machine model
3 *
4 * Copyright (c) 2016, IBM Corporation.
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include "qemu/osdep.h"
a8d25326 21#include "qemu-common.h"
fc6b3cf9 22#include "qemu/units.h"
9e933f4a
BH		 23#include "qapi/error.h"
24#include "sysemu/sysemu.h"
25#include "sysemu/numa.h"
71e8a915 26#include "sysemu/reset.h"
54d31236 27#include "sysemu/runstate.h"
d2528bdc 28#include "sysemu/cpus.h"
8d409261 29#include "sysemu/device_tree.h"
fcf5ef2a 30#include "target/ppc/cpu.h"
9e933f4a
BH		 31#include "qemu/log.h"
32#include "hw/ppc/fdt.h"
33#include "hw/ppc/ppc.h"
34#include "hw/ppc/pnv.h"
d2fd9612 35#include "hw/ppc/pnv_core.h"
9e933f4a
BH		 36#include "hw/loader.h"
37#include "exec/address-spaces.h"
e997040e 38#include "qapi/visitor.h"
47fea43a
CLG		 39#include "monitor/monitor.h"
40#include "hw/intc/intc.h"
aeaef83d 41#include "hw/ipmi/ipmi.h"
58969eee 42#include "target/ppc/mmu-hash64.h"
9e933f4a 43
36fc6f08 44#include "hw/ppc/xics.h"
a27bd6c7 45#include "hw/qdev-properties.h"
967b7523 46#include "hw/ppc/pnv_xscom.h"
35dde576 47#include "hw/ppc/pnv_pnor.h"
967b7523 48
3495b6b6 49#include "hw/isa/isa.h"
12e9493d 50#include "hw/boards.h"
3495b6b6 51#include "hw/char/serial.h"
bcdb9064 52#include "hw/rtc/mc146818rtc.h"
3495b6b6 53
9e933f4a
BH		 54#include <libfdt.h>
55
b268a616 56#define FDT_MAX_SIZE (1 * MiB)
9e933f4a
BH		 57
58#define FW_FILE_NAME "skiboot.lid"
59#define FW_LOAD_ADDR 0x0
b268a616 60#define FW_MAX_SIZE (4 * MiB)
9e933f4a
BH		 61
62#define KERNEL_LOAD_ADDR 0x20000000
b45b56ba 63#define KERNEL_MAX_SIZE (256 * MiB)
fef592f9 64#define INITRD_LOAD_ADDR 0x60000000
584ea7e7 65#define INITRD_MAX_SIZE (256 * MiB)
9e933f4a 66
40abf43f
IM		 67static const char *pnv_chip_core_typename(const PnvChip *o)
68{
69 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o)));
70 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX);
71 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type);
72 const char *core_type = object_class_get_name(object_class_by_name(s));
73 g_free(s);
74 return core_type;
75}
76
9e933f4a
BH		 77/*
78 * On Power Systems E880 (POWER8), the max cpus (threads) should be :
79 * 4 * 4 sockets * 12 cores * 8 threads = 1536
80 * Let's make it 2^11
81 */
82#define MAX_CPUS 2048
83
84/*
85 * Memory nodes are created by hostboot, one for each range of memory
86 * that has a different "affinity". In practice, it means one range
87 * per chip.
88 */
b168a138 89static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size)
9e933f4a
BH		 90{
91 char *mem_name;
92 uint64_t mem_reg_property[2];
93 int off;
94
95 mem_reg_property[0] = cpu_to_be64(start);
96 mem_reg_property[1] = cpu_to_be64(size);
97
98 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start);
99 off = fdt_add_subnode(fdt, 0, mem_name);
100 g_free(mem_name);
101
102 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
103 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
104 sizeof(mem_reg_property))));
105 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id)));
106}
107
d2fd9612
CLG		 108static int get_cpus_node(void *fdt)
109{
110 int cpus_offset = fdt_path_offset(fdt, "/cpus");
111
112 if (cpus_offset < 0) {
a4f3885c 113 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
d2fd9612
CLG		 114 if (cpus_offset) {
115 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
116 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
117 }
118 }
119 _FDT(cpus_offset);
120 return cpus_offset;
121}
122
123/*
124 * The PowerNV cores (and threads) need to use real HW ids and not an
125 * incremental index like it has been done on other platforms. This HW
126 * id is stored in the CPU PIR, it is used to create cpu nodes in the
127 * device tree, used in XSCOM to address cores and in interrupt
128 * servers.
129 */
b168a138 130static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
d2fd9612 131{
08304a86
DG		 132 PowerPCCPU *cpu = pc->threads[0];
133 CPUState *cs = CPU(cpu);
d2fd9612 134 DeviceClass *dc = DEVICE_GET_CLASS(cs);
8bd9530e 135 int smt_threads = CPU_CORE(pc)->nr_threads;
d2fd9612
CLG		 136 CPUPPCState *env = &cpu->env;
137 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
138 uint32_t servers_prop[smt_threads];
139 int i;
140 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
141 0xffffffff, 0xffffffff};
142 uint32_t tbfreq = PNV_TIMEBASE_FREQ;
143 uint32_t cpufreq = 1000000000;
144 uint32_t page_sizes_prop[64];
145 size_t page_sizes_prop_size;
146 const uint8_t pa_features[] = { 24, 0,
147 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0,
148 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
149 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
150 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
151 int offset;
152 char *nodename;
153 int cpus_offset = get_cpus_node(fdt);
154
155 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir);
156 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
157 _FDT(offset);
158 g_free(nodename);
159
160 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id)));
161
162 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir)));
163 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir)));
164 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
165
166 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
167 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
168 env->dcache_line_size)));
169 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
170 env->dcache_line_size)));
171 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
172 env->icache_line_size)));
173 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
174 env->icache_line_size)));
175
176 if (pcc->l1_dcache_size) {
177 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
178 pcc->l1_dcache_size)));
179 } else {
3dc6f869 180 warn_report("Unknown L1 dcache size for cpu");
d2fd9612
CLG		 181 }
182 if (pcc->l1_icache_size) {
183 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
184 pcc->l1_icache_size)));
185 } else {
3dc6f869 186 warn_report("Unknown L1 icache size for cpu");
d2fd9612
CLG		 187 }
188
189 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
190 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
59b7c1c2
B		 191 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size",
192 cpu->hash64_opts->slb_size)));
d2fd9612
CLG		 193 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
194 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
195
196 if (env->spr_cb[SPR_PURR].oea_read) {
197 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
198 }
199
58969eee 200 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) {
d2fd9612
CLG		 201 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
202 segs, sizeof(segs))));
203 }
204
59b7c1c2
B		 205 /*
206 * Advertise VMX/VSX (vector extensions) if available
d2fd9612
CLG		 207 * 0 / no property == no vector extensions
208 * 1 == VMX / Altivec available
59b7c1c2
B		 209 * 2 == VSX available
210 */
d2fd9612
CLG		 211 if (env->insns_flags & PPC_ALTIVEC) {
212 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
213
214 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx)));
215 }
216
59b7c1c2
B		 217 /*
218 * Advertise DFP (Decimal Floating Point) if available
d2fd9612 219 * 0 / no property == no DFP
59b7c1c2
B		 220 * 1 == DFP available
221 */
d2fd9612
CLG		 222 if (env->insns_flags2 & PPC2_DFP) {
223 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
224 }
225
644a2c99
DG		 226 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop,
227 sizeof(page_sizes_prop));
d2fd9612
CLG		 228 if (page_sizes_prop_size) {
229 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
230 page_sizes_prop, page_sizes_prop_size)));
231 }
232
233 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
234 pa_features, sizeof(pa_features))));
235
d2fd9612
CLG		 236 /* Build interrupt servers properties */
237 for (i = 0; i < smt_threads; i++) {
238 servers_prop[i] = cpu_to_be32(pc->pir + i);
239 }
240 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
241 servers_prop, sizeof(servers_prop))));
242}
243
b168a138
CLG		 244static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir,
245 uint32_t nr_threads)
bf5615e7
CLG		 246{
247 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12);
248 char *name;
249 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp";
250 uint32_t irange[2], i, rsize;
251 uint64_t *reg;
252 int offset;
253
254 irange[0] = cpu_to_be32(pir);
255 irange[1] = cpu_to_be32(nr_threads);
256
257 rsize = sizeof(uint64_t) * 2 * nr_threads;
258 reg = g_malloc(rsize);
259 for (i = 0; i < nr_threads; i++) {
260 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000));
261 reg[i * 2 + 1] = cpu_to_be64(0x1000);
262 }
263
264 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr);
265 offset = fdt_add_subnode(fdt, 0, name);
266 _FDT(offset);
267 g_free(name);
268
269 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat))));
270 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize)));
271 _FDT((fdt_setprop_string(fdt, offset, "device_type",
272 "PowerPC-External-Interrupt-Presentation")));
273 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0)));
274 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges",
275 irange, sizeof(irange))));
276 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1)));
277 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0)));
278 g_free(reg);
279}
280
eb859a27 281static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt)
e997040e 282{
d2fd9612
CLG		 283 int i;
284
b168a138 285 pnv_dt_xscom(chip, fdt, 0);
967b7523 286
d2fd9612 287 for (i = 0; i < chip->nr_cores; i++) {
4fa28f23 288 PnvCore *pnv_core = chip->cores[i];
d2fd9612 289
b168a138 290 pnv_dt_core(chip, pnv_core, fdt);
bf5615e7
CLG		 291
292 /* Interrupt Control Presenters (ICP). One per core. */
b168a138 293 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads);
d2fd9612
CLG		 294 }
295
e997040e 296 if (chip->ram_size) {
b168a138 297 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
e997040e
CLG		 298 }
299}
300
eb859a27
CLG		 301static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt)
302{
eb859a27
CLG		 303 int i;
304
305 pnv_dt_xscom(chip, fdt, 0);
306
307 for (i = 0; i < chip->nr_cores; i++) {
4fa28f23 308 PnvCore *pnv_core = chip->cores[i];
eb859a27
CLG		 309
310 pnv_dt_core(chip, pnv_core, fdt);
311 }
312
313 if (chip->ram_size) {
314 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
315 }
15376c66 316
2661f6ab 317 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE);
eb859a27
CLG		 318}
319
2b548a42
CLG		 320static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt)
321{
322 int i;
323
324 pnv_dt_xscom(chip, fdt, 0);
325
326 for (i = 0; i < chip->nr_cores; i++) {
327 PnvCore *pnv_core = chip->cores[i];
328
329 pnv_dt_core(chip, pnv_core, fdt);
330 }
331
332 if (chip->ram_size) {
333 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
334 }
2661f6ab
CLG		 335
336 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE);
2b548a42
CLG		 337}
338
b168a138 339static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off)
c5ffdcae
CLG		 340{
341 uint32_t io_base = d->ioport_id;
342 uint32_t io_regs[] = {
343 cpu_to_be32(1),
344 cpu_to_be32(io_base),
345 cpu_to_be32(2)
346 };
347 char *name;
348 int node;
349
350 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
351 node = fdt_add_subnode(fdt, lpc_off, name);
352 _FDT(node);
353 g_free(name);
354
355 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
356 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00")));
357}
358
b168a138 359static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off)
cb228f5a
CLG		 360{
361 const char compatible[] = "ns16550\0pnpPNP,501";
362 uint32_t io_base = d->ioport_id;
363 uint32_t io_regs[] = {
364 cpu_to_be32(1),
365 cpu_to_be32(io_base),
366 cpu_to_be32(8)
367 };
368 char *name;
369 int node;
370
371 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
372 node = fdt_add_subnode(fdt, lpc_off, name);
373 _FDT(node);
374 g_free(name);
375
376 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
377 _FDT((fdt_setprop(fdt, node, "compatible", compatible,
378 sizeof(compatible))));
379
380 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200)));
381 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200)));
382 _FDT((fdt_setprop_cell(fdt, node, "interrupts", d->isairq[0])));
383 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent",
384 fdt_get_phandle(fdt, lpc_off))));
385
386 /* This is needed by Linux */
387 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial")));
388}
389
b168a138 390static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off)
04f6c8b2
CLG		 391{
392 const char compatible[] = "bt\0ipmi-bt";
393 uint32_t io_base;
394 uint32_t io_regs[] = {
395 cpu_to_be32(1),
396 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */
397 cpu_to_be32(3)
398 };
399 uint32_t irq;
400 char *name;
401 int node;
402
403 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal);
404 io_regs[1] = cpu_to_be32(io_base);
405
406 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal);
407
408 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
409 node = fdt_add_subnode(fdt, lpc_off, name);
410 _FDT(node);
411 g_free(name);
412
7032d92a
CLG		 413 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
414 _FDT((fdt_setprop(fdt, node, "compatible", compatible,
415 sizeof(compatible))));
04f6c8b2
CLG		 416
417 /* Mark it as reserved to avoid Linux trying to claim it */
418 _FDT((fdt_setprop_string(fdt, node, "status", "reserved")));
419 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq)));
420 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent",
421 fdt_get_phandle(fdt, lpc_off))));
422}
423
e7a3fee3
CLG		 424typedef struct ForeachPopulateArgs {
425 void *fdt;
426 int offset;
427} ForeachPopulateArgs;
428
b168a138 429static int pnv_dt_isa_device(DeviceState *dev, void *opaque)
e7a3fee3 430{
c5ffdcae
CLG		 431 ForeachPopulateArgs *args = opaque;
432 ISADevice *d = ISA_DEVICE(dev);
433
434 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) {
b168a138 435 pnv_dt_rtc(d, args->fdt, args->offset);
cb228f5a 436 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) {
b168a138 437 pnv_dt_serial(d, args->fdt, args->offset);
04f6c8b2 438 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) {
b168a138 439 pnv_dt_ipmi_bt(d, args->fdt, args->offset);
c5ffdcae
CLG		 440 } else {
441 error_report("unknown isa device %s@i%x", qdev_fw_name(dev),
442 d->ioport_id);
443 }
444
e7a3fee3
CLG		 445 return 0;
446}
447
59b7c1c2
B		 448/*
449 * The default LPC bus of a multichip system is on chip 0. It's
bb7ab95c
CLG		 450 * recognized by the firmware (skiboot) using a "primary" property.
451 */
452static void pnv_dt_isa(PnvMachineState *pnv, void *fdt)
453{
64d011d5 454 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename);
e7a3fee3
CLG		 455 ForeachPopulateArgs args = {
456 .fdt = fdt,
bb7ab95c 457 .offset = isa_offset,
e7a3fee3 458 };
f47a08d1 459 uint32_t phandle;
e7a3fee3 460
bb7ab95c
CLG		 461 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0)));
462
f47a08d1
CLG		 463 phandle = qemu_fdt_alloc_phandle(fdt);
464 assert(phandle > 0);
465 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle)));
466
59b7c1c2
B		 467 /*
468 * ISA devices are not necessarily parented to the ISA bus so we
469 * can not use object_child_foreach()
470 */
bb7ab95c
CLG		 471 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL,
472 &args);
e7a3fee3
CLG		 473}
474
e5694793
CLG		 475static void pnv_dt_power_mgt(void *fdt)
476{
477 int off;
478
479 off = fdt_add_subnode(fdt, 0, "ibm,opal");
480 off = fdt_add_subnode(fdt, off, "power-mgt");
481
482 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000));
483}
484
b168a138 485static void *pnv_dt_create(MachineState *machine)
9e933f4a 486{
83b90bf0
CLG		 487 const char plat_compat8[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv";
488 const char plat_compat9[] = "qemu,powernv9\0ibm,powernv";
2b548a42 489 const char plat_compat10[] = "qemu,powernv10\0ibm,powernv";
b168a138 490 PnvMachineState *pnv = PNV_MACHINE(machine);
9e933f4a
BH		 491 void *fdt;
492 char *buf;
493 int off;
e997040e 494 int i;
9e933f4a
BH		 495
496 fdt = g_malloc0(FDT_MAX_SIZE);
497 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE)));
498
ccb099b3
CLG		 499 /* /qemu node */
500 _FDT((fdt_add_subnode(fdt, 0, "qemu")));
501
9e933f4a
BH		 502 /* Root node */
503 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2)));
504 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2)));
505 _FDT((fdt_setprop_string(fdt, 0, "model",
506 "IBM PowerNV (emulated by qemu)")));
2b548a42
CLG		 507 if (pnv_is_power10(pnv)) {
508 _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat10,
509 sizeof(plat_compat10))));
510 } else if (pnv_is_power9(pnv)) {
83b90bf0
CLG		 511 _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat9,
512 sizeof(plat_compat9))));
513 } else {
514 _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat8,
515 sizeof(plat_compat8))));
516 }
517
9e933f4a
BH		 518
519 buf = qemu_uuid_unparse_strdup(&qemu_uuid);
520 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf)));
521 if (qemu_uuid_set) {
522 _FDT((fdt_property_string(fdt, "system-id", buf)));
523 }
524 g_free(buf);
525
526 off = fdt_add_subnode(fdt, 0, "chosen");
527 if (machine->kernel_cmdline) {
528 _FDT((fdt_setprop_string(fdt, off, "bootargs",
529 machine->kernel_cmdline)));
530 }
531
532 if (pnv->initrd_size) {
533 uint32_t start_prop = cpu_to_be32(pnv->initrd_base);
534 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size);
535
536 _FDT((fdt_setprop(fdt, off, "linux,initrd-start",
537 &start_prop, sizeof(start_prop))));
538 _FDT((fdt_setprop(fdt, off, "linux,initrd-end",
539 &end_prop, sizeof(end_prop))));
540 }
541
e997040e
CLG		 542 /* Populate device tree for each chip */
543 for (i = 0; i < pnv->num_chips; i++) {
eb859a27 544 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt);
e997040e 545 }
e7a3fee3
CLG		 546
547 /* Populate ISA devices on chip 0 */
bb7ab95c 548 pnv_dt_isa(pnv, fdt);
aeaef83d
CLG		 549
550 if (pnv->bmc) {
b168a138 551 pnv_dt_bmc_sensors(pnv->bmc, fdt);
aeaef83d
CLG		 552 }
553
2b548a42
CLG		 554 /* Create an extra node for power management on Power9 and Power10 */
555 if (pnv_is_power9(pnv) || pnv_is_power10(pnv)) {
e5694793
CLG		 556 pnv_dt_power_mgt(fdt);
557 }
558
9e933f4a
BH		 559 return fdt;
560}
561
bce0b691
CLG		 562static void pnv_powerdown_notify(Notifier *n, void *opaque)
563{
b168a138 564 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
bce0b691
CLG		 565
566 if (pnv->bmc) {
567 pnv_bmc_powerdown(pnv->bmc);
568 }
569}
570
a0628599 571static void pnv_reset(MachineState *machine)
9e933f4a 572{
9e933f4a
BH		 573 void *fdt;
574
575 qemu_devices_reset();
576
b168a138 577 fdt = pnv_dt_create(machine);
9e933f4a
BH		 578
579 /* Pack resulting tree */
580 _FDT((fdt_pack(fdt)));
581
8d409261 582 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
9e933f4a
BH		 583 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt));
584}
585
04026890 586static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp)
3495b6b6 587{
77864267
CLG		 588 Pnv8Chip *chip8 = PNV8_CHIP(chip);
589 return pnv_lpc_isa_create(&chip8->lpc, true, errp);
04026890 590}
3495b6b6 591
04026890
CLG		 592static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp)
593{
77864267
CLG		 594 Pnv8Chip *chip8 = PNV8_CHIP(chip);
595 return pnv_lpc_isa_create(&chip8->lpc, false, errp);
04026890 596}
3495b6b6 597
04026890
CLG		 598static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp)
599{
15376c66
CLG		 600 Pnv9Chip *chip9 = PNV9_CHIP(chip);
601 return pnv_lpc_isa_create(&chip9->lpc, false, errp);
04026890 602}
3495b6b6 603
2b548a42
CLG		 604static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp)
605{
2661f6ab
CLG		 606 Pnv10Chip *chip10 = PNV10_CHIP(chip);
607 return pnv_lpc_isa_create(&chip10->lpc, false, errp);
2b548a42
CLG		 608}
609
04026890
CLG		 610static ISABus *pnv_isa_create(PnvChip *chip, Error **errp)
611{
612 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp);
3495b6b6
CLG		 613}
614
d8e4aad5
CLG		 615static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon)
616{
617 Pnv8Chip *chip8 = PNV8_CHIP(chip);
618
619 ics_pic_print_info(&chip8->psi.ics, mon);
620}
621
622static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon)
623{
624 Pnv9Chip *chip9 = PNV9_CHIP(chip);
625
626 pnv_xive_pic_print_info(&chip9->xive, mon);
c38536bc 627 pnv_psi_pic_print_info(&chip9->psi, mon);
d8e4aad5
CLG		 628}
629
f30c843c
CLG		 630static bool pnv_match_cpu(const char *default_type, const char *cpu_type)
631{
632 PowerPCCPUClass *ppc_default =
633 POWERPC_CPU_CLASS(object_class_by_name(default_type));
634 PowerPCCPUClass *ppc =
635 POWERPC_CPU_CLASS(object_class_by_name(cpu_type));
636
637 return ppc_default->pvr_match(ppc_default, ppc->pvr);
638}
639
e2392d43
CLG		 640static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq)
641{
642 Object *obj;
643
644 obj = OBJECT(isa_create(bus, "isa-ipmi-bt"));
645 object_property_set_link(obj, OBJECT(bmc), "bmc", &error_fatal);
646 object_property_set_int(obj, irq, "irq", &error_fatal);
647 object_property_set_bool(obj, true, "realized", &error_fatal);
648}
649
2b548a42
CLG		 650static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon)
651{
8b50ce85
CLG		 652 Pnv10Chip *chip10 = PNV10_CHIP(chip);
653
654 pnv_psi_pic_print_info(&chip10->psi, mon);
2b548a42
CLG		 655}
656
b168a138 657static void pnv_init(MachineState *machine)
9e933f4a 658{
b168a138 659 PnvMachineState *pnv = PNV_MACHINE(machine);
f30c843c 660 MachineClass *mc = MACHINE_GET_CLASS(machine);
9e933f4a
BH		 661 MemoryRegion *ram;
662 char *fw_filename;
663 long fw_size;
e997040e
CLG		 664 int i;
665 char *chip_typename;
35dde576
CLG		 666 DriveInfo *pnor = drive_get(IF_MTD, 0, 0);
667 DeviceState *dev;
9e933f4a
BH		 668
669 /* allocate RAM */
d23b6caa 670 if (machine->ram_size < (1 * GiB)) {
3dc6f869 671 warn_report("skiboot may not work with < 1GB of RAM");
9e933f4a
BH		 672 }
673
674 ram = g_new(MemoryRegion, 1);
b168a138 675 memory_region_allocate_system_memory(ram, NULL, "pnv.ram",
9e933f4a
BH		 676 machine->ram_size);
677 memory_region_add_subregion(get_system_memory(), 0, ram);
678
35dde576
CLG		 679 /*
680 * Create our simple PNOR device
681 */
682 dev = qdev_create(NULL, TYPE_PNV_PNOR);
683 if (pnor) {
684 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor),
685 &error_abort);
686 }
687 qdev_init_nofail(dev);
688 pnv->pnor = PNV_PNOR(dev);
689
9e933f4a
BH		 690 /* load skiboot firmware */
691 if (bios_name == NULL) {
692 bios_name = FW_FILE_NAME;
693 }
694
695 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
15fcedb2
CLG		 696 if (!fw_filename) {
697 error_report("Could not find OPAL firmware '%s'", bios_name);
698 exit(1);
699 }
9e933f4a
BH		 700
701 fw_size = load_image_targphys(fw_filename, FW_LOAD_ADDR, FW_MAX_SIZE);
702 if (fw_size < 0) {
15fcedb2 703 error_report("Could not load OPAL firmware '%s'", fw_filename);
9e933f4a
BH		 704 exit(1);
705 }
706 g_free(fw_filename);
707
708 /* load kernel */
709 if (machine->kernel_filename) {
710 long kernel_size;
711
712 kernel_size = load_image_targphys(machine->kernel_filename,
b45b56ba 713 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE);
9e933f4a 714 if (kernel_size < 0) {
802fc7ab 715 error_report("Could not load kernel '%s'",
7c6e8797 716 machine->kernel_filename);
9e933f4a
BH		 717 exit(1);
718 }
719 }
720
721 /* load initrd */
722 if (machine->initrd_filename) {
723 pnv->initrd_base = INITRD_LOAD_ADDR;
724 pnv->initrd_size = load_image_targphys(machine->initrd_filename,
584ea7e7 725 pnv->initrd_base, INITRD_MAX_SIZE);
9e933f4a 726 if (pnv->initrd_size < 0) {
802fc7ab 727 error_report("Could not load initial ram disk '%s'",
9e933f4a
BH		 728 machine->initrd_filename);
729 exit(1);
730 }
731 }
e997040e 732
f30c843c
CLG		 733 /*
734 * Check compatibility of the specified CPU with the machine
735 * default.
736 */
737 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) {
738 error_report("invalid CPU model '%s' for %s machine",
739 machine->cpu_type, mc->name);
740 exit(1);
741 }
742
e997040e 743 /* Create the processor chips */
4a12c699 744 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX);
7fd544d8 745 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"),
4a12c699 746 i, machine->cpu_type);
e997040e 747 if (!object_class_by_name(chip_typename)) {
f30c843c
CLG		 748 error_report("invalid chip model '%.*s' for %s machine",
749 i, machine->cpu_type, mc->name);
e997040e
CLG		 750 exit(1);
751 }
752
753 pnv->chips = g_new0(PnvChip *, pnv->num_chips);
754 for (i = 0; i < pnv->num_chips; i++) {
755 char chip_name[32];
756 Object *chip = object_new(chip_typename);
757
758 pnv->chips[i] = PNV_CHIP(chip);
759
59b7c1c2
B		 760 /*
761 * TODO: put all the memory in one node on chip 0 until we find a
e997040e
CLG		 762 * way to specify different ranges for each chip
763 */
764 if (i == 0) {
765 object_property_set_int(chip, machine->ram_size, "ram-size",
766 &error_fatal);
767 }
768
769 snprintf(chip_name, sizeof(chip_name), "chip[%d]", PNV_CHIP_HWID(i));
770 object_property_add_child(OBJECT(pnv), chip_name, chip, &error_fatal);
771 object_property_set_int(chip, PNV_CHIP_HWID(i), "chip-id",
772 &error_fatal);
fe6b6346
LX		 773 object_property_set_int(chip, machine->smp.cores,
774 "nr-cores", &error_fatal);
e997040e
CLG		 775 object_property_set_bool(chip, true, "realized", &error_fatal);
776 }
777 g_free(chip_typename);
3495b6b6 778
e2392d43
CLG		 779 /* Create the machine BMC simulator */
780 pnv->bmc = pnv_bmc_create();
781
3495b6b6 782 /* Instantiate ISA bus on chip 0 */
04026890 783 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal);
3495b6b6
CLG		 784
785 /* Create serial port */
def337ff 786 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS);
3495b6b6
CLG		 787
788 /* Create an RTC ISA device too */
6c646a11 789 mc146818_rtc_init(pnv->isa_bus, 2000, NULL);
bce0b691 790
e2392d43
CLG		 791 /* Create the IPMI BT device for communication with the BMC */
792 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10);
793
59b7c1c2
B		 794 /*
795 * OpenPOWER systems use a IPMI SEL Event message to notify the
796 * host to powerdown
797 */
bce0b691
CLG		 798 pnv->powerdown_notifier.notify = pnv_powerdown_notify;
799 qemu_register_powerdown_notifier(&pnv->powerdown_notifier);
e997040e
CLG		 800}
801
631adaff
CLG		 802/*
803 * 0:21 Reserved - Read as zeros
804 * 22:24 Chip ID
805 * 25:28 Core number
806 * 29:31 Thread ID
807 */
808static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id)
809{
810 return (chip->chip_id << 7) | (core_id << 3);
811}
812
8fa1f4ef
CLG		 813static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu,
814 Error **errp)
d35aefa9 815{
8fa1f4ef
CLG		 816 Error *local_err = NULL;
817 Object *obj;
8907fc25 818 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
8fa1f4ef
CLG		 819
820 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, XICS_FABRIC(qdev_get_machine()),
821 &local_err);
822 if (local_err) {
823 error_propagate(errp, local_err);
824 return;
825 }
826
956b8f46 827 pnv_cpu->intc = obj;
d35aefa9
CLG		 828}
829
0990ce6a 830
d49e8a9b
CLG		 831static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
832{
833 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
834
835 icp_reset(ICP(pnv_cpu->intc));
836}
837
0990ce6a
GK		 838static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
839{
840 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
841
842 icp_destroy(ICP(pnv_cpu->intc));
843 pnv_cpu->intc = NULL;
844}
845
631adaff
CLG		 846/*
847 * 0:48 Reserved - Read as zeroes
848 * 49:52 Node ID
849 * 53:55 Chip ID
850 * 56 Reserved - Read as zero
851 * 57:61 Core number
852 * 62:63 Thread ID
853 *
854 * We only care about the lower bits. uint32_t is fine for the moment.
855 */
856static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id)
857{
858 return (chip->chip_id << 8) | (core_id << 2);
859}
860
2b548a42
CLG		 861static uint32_t pnv_chip_core_pir_p10(PnvChip *chip, uint32_t core_id)
862{
863 return (chip->chip_id << 8) | (core_id << 2);
864}
865
8fa1f4ef
CLG		 866static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu,
867 Error **errp)
d35aefa9 868{
2dfa91a2
CLG		 869 Pnv9Chip *chip9 = PNV9_CHIP(chip);
870 Error *local_err = NULL;
871 Object *obj;
872 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
873
874 /*
875 * The core creates its interrupt presenter but the XIVE interrupt
876 * controller object is initialized afterwards. Hopefully, it's
877 * only used at runtime.
878 */
26aa5b1e 879 obj = xive_tctx_create(OBJECT(cpu), XIVE_ROUTER(&chip9->xive), &local_err);
2dfa91a2
CLG		 880 if (local_err) {
881 error_propagate(errp, local_err);
882 return;
883 }
884
885 pnv_cpu->intc = obj;
d35aefa9
CLG		 886}
887
d49e8a9b
CLG		 888static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
889{
890 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
891
892 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc));
893}
894
0990ce6a
GK		 895static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
896{
897 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
898
899 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc));
900 pnv_cpu->intc = NULL;
901}
902
2b548a42
CLG		 903static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu,
904 Error **errp)
905{
906 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
907
908 /* Will be defined when the interrupt controller is */
909 pnv_cpu->intc = NULL;
910}
911
912static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
913{
914 ;
915}
916
917static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
918{
919 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
920
921 pnv_cpu->intc = NULL;
922}
923
59b7c1c2
B		 924/*
925 * Allowed core identifiers on a POWER8 Processor Chip :
397a79e7
CLG		 926 *
927 * <EX0 reserved>
928 * EX1 - Venice only
929 * EX2 - Venice only
930 * EX3 - Venice only
931 * EX4
932 * EX5
933 * EX6
934 * <EX7,8 reserved> <reserved>
935 * EX9 - Venice only
936 * EX10 - Venice only
937 * EX11 - Venice only
938 * EX12
939 * EX13
940 * EX14
941 * <EX15 reserved>
942 */
943#define POWER8E_CORE_MASK (0x7070ull)
944#define POWER8_CORE_MASK (0x7e7eull)
945
946/*
09279d7e 947 * POWER9 has 24 cores, ids starting at 0x0
397a79e7 948 */
09279d7e 949#define POWER9_CORE_MASK (0xffffffffffffffull)
397a79e7 950
2b548a42
CLG		 951
952#define POWER10_CORE_MASK (0xffffffffffffffull)
953
77864267
CLG		 954static void pnv_chip_power8_instance_init(Object *obj)
955{
956 Pnv8Chip *chip8 = PNV8_CHIP(obj);
957
f6d4dca8 958 object_initialize_child(obj, "psi", &chip8->psi, sizeof(chip8->psi),
ae856055 959 TYPE_PNV8_PSI, &error_abort, NULL);
77864267
CLG		 960 object_property_add_const_link(OBJECT(&chip8->psi), "xics",
961 OBJECT(qdev_get_machine()), &error_abort);
962
f6d4dca8 963 object_initialize_child(obj, "lpc", &chip8->lpc, sizeof(chip8->lpc),
82514be2 964 TYPE_PNV8_LPC, &error_abort, NULL);
77864267 965
f6d4dca8 966 object_initialize_child(obj, "occ", &chip8->occ, sizeof(chip8->occ),
3233838c 967 TYPE_PNV8_OCC, &error_abort, NULL);
3887d241
B		 968
969 object_initialize_child(obj, "homer", &chip8->homer, sizeof(chip8->homer),
970 TYPE_PNV8_HOMER, &error_abort, NULL);
77864267
CLG		 971}
972
973static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp)
974 {
975 PnvChip *chip = PNV_CHIP(chip8);
976 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
77864267
CLG		 977 int i, j;
978 char *name;
979 XICSFabric *xi = XICS_FABRIC(qdev_get_machine());
980
981 name = g_strdup_printf("icp-%x", chip->chip_id);
982 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE);
983 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio);
984 g_free(name);
985
986 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip));
987
988 /* Map the ICP registers for each thread */
989 for (i = 0; i < chip->nr_cores; i++) {
4fa28f23 990 PnvCore *pnv_core = chip->cores[i];
77864267
CLG		 991 int core_hwid = CPU_CORE(pnv_core)->core_id;
992
993 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) {
994 uint32_t pir = pcc->core_pir(chip, core_hwid) + j;
995 PnvICPState *icp = PNV_ICP(xics_icp_get(xi, pir));
996
997 memory_region_add_subregion(&chip8->icp_mmio, pir << 12,
998 &icp->mmio);
999 }
1000 }
1001}
1002
1003static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
1004{
1005 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
1006 PnvChip *chip = PNV_CHIP(dev);
1007 Pnv8Chip *chip8 = PNV8_CHIP(dev);
ae856055 1008 Pnv8Psi *psi8 = &chip8->psi;
77864267
CLG		 1009 Error *local_err = NULL;
1010
709044fd
CLG		 1011 /* XSCOM bridge is first */
1012 pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err);
1013 if (local_err) {
1014 error_propagate(errp, local_err);
1015 return;
1016 }
1017 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip));
1018
77864267
CLG		 1019 pcc->parent_realize(dev, &local_err);
1020 if (local_err) {
1021 error_propagate(errp, local_err);
1022 return;
1023 }
1024
1025 /* Processor Service Interface (PSI) Host Bridge */
1026 object_property_set_int(OBJECT(&chip8->psi), PNV_PSIHB_BASE(chip),
1027 "bar", &error_fatal);
1028 object_property_set_bool(OBJECT(&chip8->psi), true, "realized", &local_err);
1029 if (local_err) {
1030 error_propagate(errp, local_err);
1031 return;
1032 }
ae856055
CLG		 1033 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE,
1034 &PNV_PSI(psi8)->xscom_regs);
77864267
CLG		 1035
1036 /* Create LPC controller */
b63f3893
GK		 1037 object_property_set_link(OBJECT(&chip8->lpc), OBJECT(&chip8->psi), "psi",
1038 &error_abort);
77864267
CLG		 1039 object_property_set_bool(OBJECT(&chip8->lpc), true, "realized",
1040 &error_fatal);
1041 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs);
1042
64d011d5
CLG		 1043 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x",
1044 (uint64_t) PNV_XSCOM_BASE(chip),
1045 PNV_XSCOM_LPC_BASE);
1046
59b7c1c2
B		 1047 /*
1048 * Interrupt Management Area. This is the memory region holding
1049 * all the Interrupt Control Presenter (ICP) registers
1050 */
77864267
CLG		 1051 pnv_chip_icp_realize(chip8, &local_err);
1052 if (local_err) {
1053 error_propagate(errp, local_err);
1054 return;
1055 }
1056
1057 /* Create the simplified OCC model */
ee3d2713
GK		 1058 object_property_set_link(OBJECT(&chip8->occ), OBJECT(&chip8->psi), "psi",
1059 &error_abort);
77864267
CLG		 1060 object_property_set_bool(OBJECT(&chip8->occ), true, "realized", &local_err);
1061 if (local_err) {
1062 error_propagate(errp, local_err);
1063 return;
1064 }
1065 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs);
f3db8266
B		 1066
1067 /* OCC SRAM model */
1068 memory_region_add_subregion(get_system_memory(), PNV_OCC_COMMON_AREA(chip),
1069 &chip8->occ.sram_regs);
3887d241
B		 1070
1071 /* HOMER */
f2582acf
GK		 1072 object_property_set_link(OBJECT(&chip8->homer), OBJECT(chip), "chip",
1073 &error_abort);
3887d241
B		 1074 object_property_set_bool(OBJECT(&chip8->homer), true, "realized",
1075 &local_err);
1076 if (local_err) {
1077 error_propagate(errp, local_err);
1078 return;
1079 }
1080 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip),
1081 &chip8->homer.regs);
77864267
CLG		 1082}
1083
e997040e
CLG		 1084static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
1085{
1086 DeviceClass *dc = DEVICE_CLASS(klass);
1087 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1088
e997040e
CLG		 1089 k->chip_type = PNV_CHIP_POWER8E;
1090 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */
397a79e7 1091 k->cores_mask = POWER8E_CORE_MASK;
631adaff 1092 k->core_pir = pnv_chip_core_pir_p8;
d35aefa9 1093 k->intc_create = pnv_chip_power8_intc_create;
d49e8a9b 1094 k->intc_reset = pnv_chip_power8_intc_reset;
0990ce6a 1095 k->intc_destroy = pnv_chip_power8_intc_destroy;
04026890 1096 k->isa_create = pnv_chip_power8_isa_create;
eb859a27 1097 k->dt_populate = pnv_chip_power8_dt_populate;
d8e4aad5 1098 k->pic_print_info = pnv_chip_power8_pic_print_info;
e997040e 1099 dc->desc = "PowerNV Chip POWER8E";
77864267
CLG		 1100
1101 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
1102 &k->parent_realize);
e997040e
CLG		 1103}
1104
e997040e
CLG		 1105static void pnv_chip_power8_class_init(ObjectClass *klass, void *data)
1106{
1107 DeviceClass *dc = DEVICE_CLASS(klass);
1108 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1109
e997040e
CLG		 1110 k->chip_type = PNV_CHIP_POWER8;
1111 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */
397a79e7 1112 k->cores_mask = POWER8_CORE_MASK;
631adaff 1113 k->core_pir = pnv_chip_core_pir_p8;
d35aefa9 1114 k->intc_create = pnv_chip_power8_intc_create;
d49e8a9b 1115 k->intc_reset = pnv_chip_power8_intc_reset;
0990ce6a 1116 k->intc_destroy = pnv_chip_power8_intc_destroy;
04026890 1117 k->isa_create = pnv_chip_power8_isa_create;
eb859a27 1118 k->dt_populate = pnv_chip_power8_dt_populate;
d8e4aad5 1119 k->pic_print_info = pnv_chip_power8_pic_print_info;
e997040e 1120 dc->desc = "PowerNV Chip POWER8";
77864267
CLG		 1121
1122 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
1123 &k->parent_realize);
e997040e
CLG		 1124}
1125
e997040e
CLG		 1126static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data)
1127{
1128 DeviceClass *dc = DEVICE_CLASS(klass);
1129 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1130
e997040e
CLG		 1131 k->chip_type = PNV_CHIP_POWER8NVL;
1132 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */
397a79e7 1133 k->cores_mask = POWER8_CORE_MASK;
631adaff 1134 k->core_pir = pnv_chip_core_pir_p8;
d35aefa9 1135 k->intc_create = pnv_chip_power8_intc_create;
d49e8a9b 1136 k->intc_reset = pnv_chip_power8_intc_reset;
0990ce6a 1137 k->intc_destroy = pnv_chip_power8_intc_destroy;
04026890 1138 k->isa_create = pnv_chip_power8nvl_isa_create;
eb859a27 1139 k->dt_populate = pnv_chip_power8_dt_populate;
d8e4aad5 1140 k->pic_print_info = pnv_chip_power8_pic_print_info;
e997040e 1141 dc->desc = "PowerNV Chip POWER8NVL";
77864267
CLG		 1142
1143 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
1144 &k->parent_realize);
1145}
1146
1147static void pnv_chip_power9_instance_init(Object *obj)
1148{
2dfa91a2
CLG		 1149 Pnv9Chip *chip9 = PNV9_CHIP(obj);
1150
1151 object_initialize_child(obj, "xive", &chip9->xive, sizeof(chip9->xive),
1152 TYPE_PNV_XIVE, &error_abort, NULL);
c38536bc
CLG		 1153
1154 object_initialize_child(obj, "psi", &chip9->psi, sizeof(chip9->psi),
1155 TYPE_PNV9_PSI, &error_abort, NULL);
15376c66
CLG		 1156
1157 object_initialize_child(obj, "lpc", &chip9->lpc, sizeof(chip9->lpc),
1158 TYPE_PNV9_LPC, &error_abort, NULL);
6598a70d
CLG		 1159
1160 object_initialize_child(obj, "occ", &chip9->occ, sizeof(chip9->occ),
1161 TYPE_PNV9_OCC, &error_abort, NULL);
3887d241
B		 1162
1163 object_initialize_child(obj, "homer", &chip9->homer, sizeof(chip9->homer),
1164 TYPE_PNV9_HOMER, &error_abort, NULL);
77864267
CLG		 1165}
1166
5dad902c
CLG		 1167static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp)
1168{
1169 PnvChip *chip = PNV_CHIP(chip9);
5dad902c
CLG		 1170 int i;
1171
1172 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4);
1173 chip9->quads = g_new0(PnvQuad, chip9->nr_quads);
1174
1175 for (i = 0; i < chip9->nr_quads; i++) {
1176 char eq_name[32];
1177 PnvQuad *eq = &chip9->quads[i];
4fa28f23 1178 PnvCore *pnv_core = chip->cores[i * 4];
5dad902c
CLG		 1179 int core_id = CPU_CORE(pnv_core)->core_id;
1180
5dad902c 1181 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id);
bc4c406c
PMD		 1182 object_initialize_child(OBJECT(chip), eq_name, eq, sizeof(*eq),
1183 TYPE_PNV_QUAD, &error_fatal, NULL);
5dad902c 1184
5dad902c
CLG		 1185 object_property_set_int(OBJECT(eq), core_id, "id", &error_fatal);
1186 object_property_set_bool(OBJECT(eq), true, "realized", &error_fatal);
5dad902c
CLG		 1187
1188 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->id),
1189 &eq->xscom_regs);
1190 }
1191}
1192
77864267
CLG		 1193static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
1194{
1195 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
2dfa91a2
CLG		 1196 Pnv9Chip *chip9 = PNV9_CHIP(dev);
1197 PnvChip *chip = PNV_CHIP(dev);
c38536bc 1198 Pnv9Psi *psi9 = &chip9->psi;
77864267
CLG		 1199 Error *local_err = NULL;
1200
709044fd
CLG		 1201 /* XSCOM bridge is first */
1202 pnv_xscom_realize(chip, PNV9_XSCOM_SIZE, &local_err);
1203 if (local_err) {
1204 error_propagate(errp, local_err);
1205 return;
1206 }
1207 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV9_XSCOM_BASE(chip));
1208
77864267
CLG		 1209 pcc->parent_realize(dev, &local_err);
1210 if (local_err) {
1211 error_propagate(errp, local_err);
1212 return;
1213 }
2dfa91a2 1214
5dad902c
CLG		 1215 pnv_chip_quad_realize(chip9, &local_err);
1216 if (local_err) {
1217 error_propagate(errp, local_err);
1218 return;
1219 }
1220
2dfa91a2
CLG		 1221 /* XIVE interrupt controller (POWER9) */
1222 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_IC_BASE(chip),
1223 "ic-bar", &error_fatal);
1224 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_VC_BASE(chip),
1225 "vc-bar", &error_fatal);
1226 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_PC_BASE(chip),
1227 "pc-bar", &error_fatal);
1228 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_TM_BASE(chip),
1229 "tm-bar", &error_fatal);
7ae54cc3
GK		 1230 object_property_set_link(OBJECT(&chip9->xive), OBJECT(chip), "chip",
1231 &error_abort);
2dfa91a2
CLG		 1232 object_property_set_bool(OBJECT(&chip9->xive), true, "realized",
1233 &local_err);
1234 if (local_err) {
1235 error_propagate(errp, local_err);
1236 return;
1237 }
1238 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE,
1239 &chip9->xive.xscom_regs);
c38536bc
CLG		 1240
1241 /* Processor Service Interface (PSI) Host Bridge */
1242 object_property_set_int(OBJECT(&chip9->psi), PNV9_PSIHB_BASE(chip),
1243 "bar", &error_fatal);
1244 object_property_set_bool(OBJECT(&chip9->psi), true, "realized", &local_err);
1245 if (local_err) {
1246 error_propagate(errp, local_err);
1247 return;
1248 }
1249 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE,
1250 &PNV_PSI(psi9)->xscom_regs);
15376c66
CLG		 1251
1252 /* LPC */
b63f3893
GK		 1253 object_property_set_link(OBJECT(&chip9->lpc), OBJECT(&chip9->psi), "psi",
1254 &error_abort);
15376c66
CLG		 1255 object_property_set_bool(OBJECT(&chip9->lpc), true, "realized", &local_err);
1256 if (local_err) {
1257 error_propagate(errp, local_err);
1258 return;
1259 }
1260 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip),
1261 &chip9->lpc.xscom_regs);
1262
1263 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0",
1264 (uint64_t) PNV9_LPCM_BASE(chip));
6598a70d
CLG		 1265
1266 /* Create the simplified OCC model */
ee3d2713
GK		 1267 object_property_set_link(OBJECT(&chip9->occ), OBJECT(&chip9->psi), "psi",
1268 &error_abort);
6598a70d
CLG		 1269 object_property_set_bool(OBJECT(&chip9->occ), true, "realized", &local_err);
1270 if (local_err) {
1271 error_propagate(errp, local_err);
1272 return;
1273 }
1274 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs);
f3db8266
B		 1275
1276 /* OCC SRAM model */
1277 memory_region_add_subregion(get_system_memory(), PNV9_OCC_COMMON_AREA(chip),
1278 &chip9->occ.sram_regs);
3887d241
B		 1279
1280 /* HOMER */
f2582acf
GK		 1281 object_property_set_link(OBJECT(&chip9->homer), OBJECT(chip), "chip",
1282 &error_abort);
3887d241
B		 1283 object_property_set_bool(OBJECT(&chip9->homer), true, "realized",
1284 &local_err);
1285 if (local_err) {
1286 error_propagate(errp, local_err);
1287 return;
1288 }
1289 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip),
1290 &chip9->homer.regs);
e997040e
CLG		 1291}
1292
e997040e
CLG		 1293static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
1294{
1295 DeviceClass *dc = DEVICE_CLASS(klass);
1296 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1297
e997040e 1298 k->chip_type = PNV_CHIP_POWER9;
83028a2b 1299 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */
397a79e7 1300 k->cores_mask = POWER9_CORE_MASK;
631adaff 1301 k->core_pir = pnv_chip_core_pir_p9;
d35aefa9 1302 k->intc_create = pnv_chip_power9_intc_create;
d49e8a9b 1303 k->intc_reset = pnv_chip_power9_intc_reset;
0990ce6a 1304 k->intc_destroy = pnv_chip_power9_intc_destroy;
04026890 1305 k->isa_create = pnv_chip_power9_isa_create;
eb859a27 1306 k->dt_populate = pnv_chip_power9_dt_populate;
d8e4aad5 1307 k->pic_print_info = pnv_chip_power9_pic_print_info;
e997040e 1308 dc->desc = "PowerNV Chip POWER9";
77864267
CLG		 1309
1310 device_class_set_parent_realize(dc, pnv_chip_power9_realize,
1311 &k->parent_realize);
e997040e
CLG		 1312}
1313
2b548a42
CLG		 1314static void pnv_chip_power10_instance_init(Object *obj)
1315{
8b50ce85
CLG		 1316 Pnv10Chip *chip10 = PNV10_CHIP(obj);
1317
1318 object_initialize_child(obj, "psi", &chip10->psi, sizeof(chip10->psi),
1319 TYPE_PNV10_PSI, &error_abort, NULL);
2661f6ab
CLG		 1320 object_initialize_child(obj, "lpc", &chip10->lpc, sizeof(chip10->lpc),
1321 TYPE_PNV10_LPC, &error_abort, NULL);
2b548a42
CLG		 1322}
1323
1324static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
1325{
1326 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
1327 PnvChip *chip = PNV_CHIP(dev);
8b50ce85 1328 Pnv10Chip *chip10 = PNV10_CHIP(dev);
2b548a42
CLG		 1329 Error *local_err = NULL;
1330
1331 /* XSCOM bridge is first */
1332 pnv_xscom_realize(chip, PNV10_XSCOM_SIZE, &local_err);
1333 if (local_err) {
1334 error_propagate(errp, local_err);
1335 return;
1336 }
1337 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV10_XSCOM_BASE(chip));
1338
1339 pcc->parent_realize(dev, &local_err);
1340 if (local_err) {
1341 error_propagate(errp, local_err);
1342 return;
1343 }
8b50ce85
CLG		 1344
1345 /* Processor Service Interface (PSI) Host Bridge */
1346 object_property_set_int(OBJECT(&chip10->psi), PNV10_PSIHB_BASE(chip),
1347 "bar", &error_fatal);
1348 object_property_set_bool(OBJECT(&chip10->psi), true, "realized",
1349 &local_err);
1350 if (local_err) {
1351 error_propagate(errp, local_err);
1352 return;
1353 }
1354 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE,
1355 &PNV_PSI(&chip10->psi)->xscom_regs);
2661f6ab
CLG		 1356
1357 /* LPC */
1358 object_property_set_link(OBJECT(&chip10->lpc), OBJECT(&chip10->psi), "psi",
1359 &error_abort);
1360 object_property_set_bool(OBJECT(&chip10->lpc), true, "realized",
1361 &local_err);
1362 if (local_err) {
1363 error_propagate(errp, local_err);
1364 return;
1365 }
1366 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip),
1367 &chip10->lpc.xscom_regs);
1368
1369 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0",
1370 (uint64_t) PNV10_LPCM_BASE(chip));
2b548a42
CLG		 1371}
1372
1373static void pnv_chip_power10_class_init(ObjectClass *klass, void *data)
1374{
1375 DeviceClass *dc = DEVICE_CLASS(klass);
1376 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1377
1378 k->chip_type = PNV_CHIP_POWER10;
1379 k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */
1380 k->cores_mask = POWER10_CORE_MASK;
1381 k->core_pir = pnv_chip_core_pir_p10;
1382 k->intc_create = pnv_chip_power10_intc_create;
1383 k->intc_reset = pnv_chip_power10_intc_reset;
1384 k->intc_destroy = pnv_chip_power10_intc_destroy;
1385 k->isa_create = pnv_chip_power10_isa_create;
1386 k->dt_populate = pnv_chip_power10_dt_populate;
1387 k->pic_print_info = pnv_chip_power10_pic_print_info;
1388 dc->desc = "PowerNV Chip POWER10";
1389
1390 device_class_set_parent_realize(dc, pnv_chip_power10_realize,
1391 &k->parent_realize);
1392}
1393
397a79e7
CLG		 1394static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp)
1395{
1396 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
1397 int cores_max;
1398
1399 /*
1400 * No custom mask for this chip, let's use the default one from *
1401 * the chip class
1402 */
1403 if (!chip->cores_mask) {
1404 chip->cores_mask = pcc->cores_mask;
1405 }
1406
1407 /* filter alien core ids ! some are reserved */
1408 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) {
1409 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !",
1410 chip->cores_mask);
1411 return;
1412 }
1413 chip->cores_mask &= pcc->cores_mask;
1414
1415 /* now that we have a sane layout, let check the number of cores */
27d9ffd4 1416 cores_max = ctpop64(chip->cores_mask);
397a79e7
CLG		 1417 if (chip->nr_cores > cores_max) {
1418 error_setg(errp, "warning: too many cores for chip ! Limit is %d",
1419 cores_max);
1420 return;
1421 }
1422}
1423
51c04728 1424static void pnv_chip_core_realize(PnvChip *chip, Error **errp)
e997040e 1425{
fe6b6346 1426 MachineState *ms = MACHINE(qdev_get_machine());
397a79e7 1427 Error *error = NULL;
d2fd9612 1428 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
40abf43f 1429 const char *typename = pnv_chip_core_typename(chip);
d2fd9612
CLG		 1430 int i, core_hwid;
1431
1432 if (!object_class_by_name(typename)) {
1433 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename);
1434 return;
1435 }
397a79e7 1436
d2fd9612 1437 /* Cores */
397a79e7
CLG		 1438 pnv_chip_core_sanitize(chip, &error);
1439 if (error) {
1440 error_propagate(errp, error);
1441 return;
1442 }
d2fd9612 1443
4fa28f23 1444 chip->cores = g_new0(PnvCore *, chip->nr_cores);
d2fd9612
CLG		 1445
1446 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8)
1447 && (i < chip->nr_cores); core_hwid++) {
1448 char core_name[32];
4fa28f23 1449 PnvCore *pnv_core;
c035851a 1450 uint64_t xscom_core_base;
d2fd9612
CLG		 1451
1452 if (!(chip->cores_mask & (1ull << core_hwid))) {
1453 continue;
1454 }
1455
4fa28f23
GK		 1456 pnv_core = PNV_CORE(object_new(typename));
1457
d2fd9612 1458 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid);
4fa28f23
GK		 1459 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core),
1460 &error_abort);
1461 chip->cores[i] = pnv_core;
fe6b6346 1462 object_property_set_int(OBJECT(pnv_core), ms->smp.threads, "nr-threads",
d2fd9612
CLG		 1463 &error_fatal);
1464 object_property_set_int(OBJECT(pnv_core), core_hwid,
1465 CPU_CORE_PROP_CORE_ID, &error_fatal);
1466 object_property_set_int(OBJECT(pnv_core),
1467 pcc->core_pir(chip, core_hwid),
1468 "pir", &error_fatal);
158e17a6
GK		 1469 object_property_set_link(OBJECT(pnv_core), OBJECT(chip), "chip",
1470 &error_abort);
d2fd9612
CLG		 1471 object_property_set_bool(OBJECT(pnv_core), true, "realized",
1472 &error_fatal);
24ece072
CLG		 1473
1474 /* Each core has an XSCOM MMIO region */
2b548a42
CLG		 1475 if (pnv_chip_is_power10(chip)) {
1476 xscom_core_base = PNV10_XSCOM_EC_BASE(core_hwid);
1477 } else if (pnv_chip_is_power9(chip)) {
5dad902c 1478 xscom_core_base = PNV9_XSCOM_EC_BASE(core_hwid);
2b548a42
CLG		 1479 } else {
1480 xscom_core_base = PNV_XSCOM_EX_BASE(core_hwid);
c035851a
CLG		 1481 }
1482
1483 pnv_xscom_add_subregion(chip, xscom_core_base,
4fa28f23 1484 &pnv_core->xscom_regs);
d2fd9612
CLG		 1485 i++;
1486 }
51c04728
CLG		 1487}
1488
1489static void pnv_chip_realize(DeviceState *dev, Error **errp)
1490{
1491 PnvChip *chip = PNV_CHIP(dev);
1492 Error *error = NULL;
1493
51c04728
CLG		 1494 /* Cores */
1495 pnv_chip_core_realize(chip, &error);
1496 if (error) {
1497 error_propagate(errp, error);
1498 return;
1499 }
e997040e
CLG		 1500}
1501
1502static Property pnv_chip_properties[] = {
1503 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0),
1504 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0),
1505 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0),
397a79e7
CLG		 1506 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1),
1507 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0),
e997040e
CLG		 1508 DEFINE_PROP_END_OF_LIST(),
1509};
1510
1511static void pnv_chip_class_init(ObjectClass *klass, void *data)
1512{
1513 DeviceClass *dc = DEVICE_CLASS(klass);
1514
9d169fb3 1515 set_bit(DEVICE_CATEGORY_CPU, dc->categories);
e997040e
CLG		 1516 dc->realize = pnv_chip_realize;
1517 dc->props = pnv_chip_properties;
1518 dc->desc = "PowerNV Chip";
1519}
1520
119eaa9d
CLG		 1521PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir)
1522{
1523 int i, j;
1524
1525 for (i = 0; i < chip->nr_cores; i++) {
1526 PnvCore *pc = chip->cores[i];
1527 CPUCore *cc = CPU_CORE(pc);
1528
1529 for (j = 0; j < cc->nr_threads; j++) {
1530 if (ppc_cpu_pir(pc->threads[j]) == pir) {
1531 return pc->threads[j];
1532 }
1533 }
1534 }
1535 return NULL;
1536}
1537
54f59d78
CLG		 1538static ICSState *pnv_ics_get(XICSFabric *xi, int irq)
1539{
b168a138 1540 PnvMachineState *pnv = PNV_MACHINE(xi);
54f59d78
CLG		 1541 int i;
1542
1543 for (i = 0; i < pnv->num_chips; i++) {
77864267
CLG		 1544 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]);
1545
1546 if (ics_valid_irq(&chip8->psi.ics, irq)) {
1547 return &chip8->psi.ics;
54f59d78
CLG		 1548 }
1549 }
1550 return NULL;
1551}
1552
1553static void pnv_ics_resend(XICSFabric *xi)
1554{
b168a138 1555 PnvMachineState *pnv = PNV_MACHINE(xi);
54f59d78
CLG		 1556 int i;
1557
1558 for (i = 0; i < pnv->num_chips; i++) {
77864267
CLG		 1559 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]);
1560 ics_resend(&chip8->psi.ics);
54f59d78
CLG		 1561 }
1562}
1563
36fc6f08
CLG		 1564static ICPState *pnv_icp_get(XICSFabric *xi, int pir)
1565{
1566 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir);
1567
956b8f46 1568 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL;
36fc6f08
CLG		 1569}
1570
47fea43a
CLG		 1571static void pnv_pic_print_info(InterruptStatsProvider *obj,
1572 Monitor *mon)
1573{
b168a138 1574 PnvMachineState *pnv = PNV_MACHINE(obj);
54f59d78 1575 int i;
47fea43a
CLG		 1576 CPUState *cs;
1577
1578 CPU_FOREACH(cs) {
1579 PowerPCCPU *cpu = POWERPC_CPU(cs);
1580
d8e4aad5
CLG		 1581 if (pnv_chip_is_power9(pnv->chips[0])) {
1582 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon);
1583 } else {
1584 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon);
1585 }
47fea43a 1586 }
54f59d78
CLG		 1587
1588 for (i = 0; i < pnv->num_chips; i++) {
d8e4aad5 1589 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon);
54f59d78 1590 }
47fea43a
CLG		 1591}
1592
c722579e
CLG		 1593static int pnv_match_nvt(XiveFabric *xfb, uint8_t format,
1594 uint8_t nvt_blk, uint32_t nvt_idx,
1595 bool cam_ignore, uint8_t priority,
1596 uint32_t logic_serv,
1597 XiveTCTXMatch *match)
1598{
1599 PnvMachineState *pnv = PNV_MACHINE(xfb);
1600 int total_count = 0;
1601 int i;
1602
1603 for (i = 0; i < pnv->num_chips; i++) {
1604 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]);
1605 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive);
1606 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr);
1607 int count;
1608
1609 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore,
1610 priority, logic_serv, match);
1611
1612 if (count < 0) {
1613 return count;
1614 }
1615
1616 total_count += count;
1617 }
1618
1619 return total_count;
1620}
1621
5373c61d
CLG		 1622PnvChip *pnv_get_chip(uint32_t chip_id)
1623{
1624 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
1625 int i;
1626
1627 for (i = 0; i < pnv->num_chips; i++) {
1628 PnvChip *chip = pnv->chips[i];
1629 if (chip->chip_id == chip_id) {
1630 return chip;
1631 }
1632 }
1633 return NULL;
1634}
1635
e997040e
CLG		 1636static void pnv_get_num_chips(Object *obj, Visitor *v, const char *name,
1637 void *opaque, Error **errp)
1638{
b168a138 1639 visit_type_uint32(v, name, &PNV_MACHINE(obj)->num_chips, errp);
e997040e
CLG		 1640}
1641
1642static void pnv_set_num_chips(Object *obj, Visitor *v, const char *name,
1643 void *opaque, Error **errp)
1644{
b168a138 1645 PnvMachineState *pnv = PNV_MACHINE(obj);
e997040e
CLG		 1646 uint32_t num_chips;
1647 Error *local_err = NULL;
1648
1649 visit_type_uint32(v, name, &num_chips, &local_err);
1650 if (local_err) {
1651 error_propagate(errp, local_err);
1652 return;
1653 }
1654
1655 /*
1656 * TODO: should we decide on how many chips we can create based
1657 * on #cores and Venice vs. Murano vs. Naples chip type etc...,
1658 */
1659 if (!is_power_of_2(num_chips) || num_chips > 4) {
1660 error_setg(errp, "invalid number of chips: '%d'", num_chips);
1661 return;
1662 }
1663
1664 pnv->num_chips = num_chips;
1665}
1666
77864267 1667static void pnv_machine_instance_init(Object *obj)
e997040e 1668{
b168a138 1669 PnvMachineState *pnv = PNV_MACHINE(obj);
e997040e
CLG		 1670 pnv->num_chips = 1;
1671}
1672
b168a138 1673static void pnv_machine_class_props_init(ObjectClass *oc)
e997040e 1674{
1e507bb0 1675 object_class_property_add(oc, "num-chips", "uint32",
e997040e
CLG		 1676 pnv_get_num_chips, pnv_set_num_chips,
1677 NULL, NULL, NULL);
1678 object_class_property_set_description(oc, "num-chips",
1679 "Specifies the number of processor chips",
1680 NULL);
9e933f4a
BH		 1681}
1682
f30c843c 1683static void pnv_machine_power8_class_init(ObjectClass *oc, void *data)
9e933f4a
BH		 1684{
1685 MachineClass *mc = MACHINE_CLASS(oc);
36fc6f08 1686 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc);
f30c843c
CLG		 1687
1688 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8";
1689 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0");
1690
1691 xic->icp_get = pnv_icp_get;
1692 xic->ics_get = pnv_ics_get;
1693 xic->ics_resend = pnv_ics_resend;
1694}
1695
1696static void pnv_machine_power9_class_init(ObjectClass *oc, void *data)
1697{
1698 MachineClass *mc = MACHINE_CLASS(oc);
c722579e 1699 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc);
f30c843c
CLG		 1700
1701 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9";
1702 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0");
c722579e 1703 xfc->match_nvt = pnv_match_nvt;
f30c843c
CLG		 1704
1705 mc->alias = "powernv";
1706}
1707
2b548a42
CLG		 1708static void pnv_machine_power10_class_init(ObjectClass *oc, void *data)
1709{
1710 MachineClass *mc = MACHINE_CLASS(oc);
1711
1712 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10";
1713 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v1.0");
1714}
1715
f30c843c
CLG		 1716static void pnv_machine_class_init(ObjectClass *oc, void *data)
1717{
1718 MachineClass *mc = MACHINE_CLASS(oc);
47fea43a 1719 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);
9e933f4a
BH		 1720
1721 mc->desc = "IBM PowerNV (Non-Virtualized)";
b168a138
CLG		 1722 mc->init = pnv_init;
1723 mc->reset = pnv_reset;
9e933f4a 1724 mc->max_cpus = MAX_CPUS;
59b7c1c2
B		 1725 /* Pnv provides a AHCI device for storage */
1726 mc->block_default_type = IF_IDE;
9e933f4a
BH		 1727 mc->no_parallel = 1;
1728 mc->default_boot_order = NULL;
f1d18b0a
JS		 1729 /*
1730 * RAM defaults to less than 2048 for 32-bit hosts, and large
1731 * enough to fit the maximum initrd size at it's load address
1732 */
1733 mc->default_ram_size = INITRD_LOAD_ADDR + INITRD_MAX_SIZE;
47fea43a 1734 ispc->print_info = pnv_pic_print_info;
e997040e 1735
b168a138 1736 pnv_machine_class_props_init(oc);
9e933f4a
BH		 1737}
1738
77864267
CLG		 1739#define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \
1740 { \
1741 .name = type, \
1742 .class_init = class_initfn, \
1743 .parent = TYPE_PNV8_CHIP, \
1744 }
1745
1746#define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \
1747 { \
1748 .name = type, \
1749 .class_init = class_initfn, \
1750 .parent = TYPE_PNV9_CHIP, \
beba5c0f
IM		 1751 }
1752
2b548a42
CLG		 1753#define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \
1754 { \
1755 .name = type, \
1756 .class_init = class_initfn, \
1757 .parent = TYPE_PNV10_CHIP, \
1758 }
1759
beba5c0f 1760static const TypeInfo types[] = {
2b548a42
CLG		 1761 {
1762 .name = MACHINE_TYPE_NAME("powernv10"),
1763 .parent = TYPE_PNV_MACHINE,
1764 .class_init = pnv_machine_power10_class_init,
1765 },
1aba8716
CLG		 1766 {
1767 .name = MACHINE_TYPE_NAME("powernv9"),
1768 .parent = TYPE_PNV_MACHINE,
1769 .class_init = pnv_machine_power9_class_init,
c722579e
CLG		 1770 .interfaces = (InterfaceInfo[]) {
1771 { TYPE_XIVE_FABRIC },
1772 { },
1773 },
1aba8716
CLG		 1774 },
1775 {
1776 .name = MACHINE_TYPE_NAME("powernv8"),
1777 .parent = TYPE_PNV_MACHINE,
1778 .class_init = pnv_machine_power8_class_init,
1779 .interfaces = (InterfaceInfo[]) {
1780 { TYPE_XICS_FABRIC },
1781 { },
1782 },
1783 },
beba5c0f 1784 {
b168a138 1785 .name = TYPE_PNV_MACHINE,
beba5c0f 1786 .parent = TYPE_MACHINE,
f30c843c 1787 .abstract = true,
beba5c0f 1788 .instance_size = sizeof(PnvMachineState),
77864267 1789 .instance_init = pnv_machine_instance_init,
b168a138 1790 .class_init = pnv_machine_class_init,
beba5c0f 1791 .interfaces = (InterfaceInfo[]) {
beba5c0f
IM		 1792 { TYPE_INTERRUPT_STATS_PROVIDER },
1793 { },
1794 },
36fc6f08 1795 },
beba5c0f
IM		 1796 {
1797 .name = TYPE_PNV_CHIP,
1798 .parent = TYPE_SYS_BUS_DEVICE,
1799 .class_init = pnv_chip_class_init,
beba5c0f
IM		 1800 .instance_size = sizeof(PnvChip),
1801 .class_size = sizeof(PnvChipClass),
1802 .abstract = true,
1803 },
77864267 1804
2b548a42
CLG		 1805 /*
1806 * P10 chip and variants
1807 */
1808 {
1809 .name = TYPE_PNV10_CHIP,
1810 .parent = TYPE_PNV_CHIP,
1811 .instance_init = pnv_chip_power10_instance_init,
1812 .instance_size = sizeof(Pnv10Chip),
1813 },
1814 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init),
1815
77864267
CLG		 1816 /*
1817 * P9 chip and variants
1818 */
1819 {
1820 .name = TYPE_PNV9_CHIP,
1821 .parent = TYPE_PNV_CHIP,
1822 .instance_init = pnv_chip_power9_instance_init,
1823 .instance_size = sizeof(Pnv9Chip),
1824 },
1825 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init),
1826
1827 /*
1828 * P8 chip and variants
1829 */
1830 {
1831 .name = TYPE_PNV8_CHIP,
1832 .parent = TYPE_PNV_CHIP,
1833 .instance_init = pnv_chip_power8_instance_init,
1834 .instance_size = sizeof(Pnv8Chip),
1835 },
1836 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init),
1837 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init),
1838 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL,
1839 pnv_chip_power8nvl_class_init),
9e933f4a
BH		 1840};
1841
beba5c0f 1842DEFINE_TYPES(types)
Empty description
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