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Commit | Line | Data |
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ad0ebb91 DG |
1 | /* |
2 | * QEMU sPAPR IOMMU (TCE) code | |
3 | * | |
4 | * Copyright (c) 2010 David Gibson, IBM Corporation <[email protected]> | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
0d75590d | 19 | #include "qemu/osdep.h" |
df7625d4 | 20 | #include "qemu/error-report.h" |
83c9f4ca | 21 | #include "hw/hw.h" |
03dd024f | 22 | #include "qemu/log.h" |
9c17d615 | 23 | #include "sysemu/kvm.h" |
83c9f4ca | 24 | #include "hw/qdev.h" |
ad0ebb91 | 25 | #include "kvm_ppc.h" |
9c17d615 | 26 | #include "sysemu/dma.h" |
022c62cb | 27 | #include "exec/address-spaces.h" |
7e472264 | 28 | #include "trace.h" |
ad0ebb91 | 29 | |
0d09e41a | 30 | #include "hw/ppc/spapr.h" |
ee9a569a | 31 | #include "hw/ppc/spapr_vio.h" |
ad0ebb91 DG |
32 | |
33 | #include <libfdt.h> | |
34 | ||
ad0ebb91 DG |
35 | enum sPAPRTCEAccess { |
36 | SPAPR_TCE_FAULT = 0, | |
37 | SPAPR_TCE_RO = 1, | |
38 | SPAPR_TCE_WO = 2, | |
39 | SPAPR_TCE_RW = 3, | |
40 | }; | |
41 | ||
650f33ad AK |
42 | #define IOMMU_PAGE_SIZE(shift) (1ULL << (shift)) |
43 | #define IOMMU_PAGE_MASK(shift) (~(IOMMU_PAGE_SIZE(shift) - 1)) | |
44 | ||
6a0a70b0 | 45 | static QLIST_HEAD(spapr_tce_tables, sPAPRTCETable) spapr_tce_tables; |
ad0ebb91 | 46 | |
f9ce8e0a | 47 | sPAPRTCETable *spapr_tce_find_by_liobn(target_ulong liobn) |
ad0ebb91 DG |
48 | { |
49 | sPAPRTCETable *tcet; | |
50 | ||
d4261662 DG |
51 | if (liobn & 0xFFFFFFFF00000000ULL) { |
52 | hcall_dprintf("Request for out-of-bounds LIOBN 0x" TARGET_FMT_lx "\n", | |
53 | liobn); | |
54 | return NULL; | |
55 | } | |
56 | ||
ad0ebb91 | 57 | QLIST_FOREACH(tcet, &spapr_tce_tables, list) { |
f9ce8e0a | 58 | if (tcet->liobn == (uint32_t)liobn) { |
ad0ebb91 DG |
59 | return tcet; |
60 | } | |
61 | } | |
62 | ||
63 | return NULL; | |
64 | } | |
65 | ||
5709af3b GK |
66 | static IOMMUAccessFlags spapr_tce_iommu_access_flags(uint64_t tce) |
67 | { | |
68 | switch (tce & SPAPR_TCE_RW) { | |
69 | case SPAPR_TCE_FAULT: | |
70 | return IOMMU_NONE; | |
71 | case SPAPR_TCE_RO: | |
72 | return IOMMU_RO; | |
73 | case SPAPR_TCE_WO: | |
74 | return IOMMU_WO; | |
75 | default: /* SPAPR_TCE_RW */ | |
76 | return IOMMU_RW; | |
77 | } | |
78 | } | |
79 | ||
fec5d3a1 AK |
80 | static uint64_t *spapr_tce_alloc_table(uint32_t liobn, |
81 | uint32_t page_shift, | |
82 | uint32_t nb_table, | |
83 | int *fd, | |
84 | bool need_vfio) | |
85 | { | |
86 | uint64_t *table = NULL; | |
87 | uint64_t window_size = (uint64_t)nb_table << page_shift; | |
88 | ||
89 | if (kvm_enabled() && !(window_size >> 32)) { | |
90 | table = kvmppc_create_spapr_tce(liobn, window_size, fd, need_vfio); | |
91 | } | |
92 | ||
93 | if (!table) { | |
94 | *fd = -1; | |
95 | table = g_malloc0(nb_table * sizeof(uint64_t)); | |
96 | } | |
97 | ||
98 | trace_spapr_iommu_new_table(liobn, table, *fd); | |
99 | ||
100 | return table; | |
101 | } | |
102 | ||
103 | static void spapr_tce_free_table(uint64_t *table, int fd, uint32_t nb_table) | |
104 | { | |
105 | if (!kvm_enabled() || | |
106 | (kvmppc_remove_spapr_tce(table, fd, nb_table) != 0)) { | |
107 | g_free(table); | |
108 | } | |
109 | } | |
110 | ||
79e2b9ae | 111 | /* Called from RCU critical section */ |
8d7b8cb9 LT |
112 | static IOMMUTLBEntry spapr_tce_translate_iommu(MemoryRegion *iommu, hwaddr addr, |
113 | bool is_write) | |
ad0ebb91 | 114 | { |
a84bb436 | 115 | sPAPRTCETable *tcet = container_of(iommu, sPAPRTCETable, iommu); |
ad0ebb91 | 116 | uint64_t tce; |
7e472264 AK |
117 | IOMMUTLBEntry ret = { |
118 | .target_as = &address_space_memory, | |
119 | .iova = 0, | |
120 | .translated_addr = 0, | |
121 | .addr_mask = ~(hwaddr)0, | |
122 | .perm = IOMMU_NONE, | |
123 | }; | |
ad0ebb91 | 124 | |
ee9a569a | 125 | if ((addr >> tcet->page_shift) < tcet->nb_table) { |
7e472264 | 126 | /* Check if we are in bound */ |
650f33ad AK |
127 | hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift); |
128 | ||
129 | tce = tcet->table[addr >> tcet->page_shift]; | |
130 | ret.iova = addr & page_mask; | |
131 | ret.translated_addr = tce & page_mask; | |
132 | ret.addr_mask = ~page_mask; | |
5709af3b | 133 | ret.perm = spapr_tce_iommu_access_flags(tce); |
ad0ebb91 | 134 | } |
7e472264 AK |
135 | trace_spapr_iommu_xlate(tcet->liobn, addr, ret.iova, ret.perm, |
136 | ret.addr_mask); | |
ad0ebb91 | 137 | |
7e472264 | 138 | return ret; |
a71bfbfe PB |
139 | } |
140 | ||
a26fdf39 AK |
141 | static void spapr_tce_table_pre_save(void *opaque) |
142 | { | |
143 | sPAPRTCETable *tcet = SPAPR_TCE_TABLE(opaque); | |
144 | ||
145 | tcet->mig_table = tcet->table; | |
146 | tcet->mig_nb_table = tcet->nb_table; | |
147 | ||
148 | trace_spapr_iommu_pre_save(tcet->liobn, tcet->mig_nb_table, | |
149 | tcet->bus_offset, tcet->page_shift); | |
150 | } | |
151 | ||
f682e9c2 AK |
152 | static uint64_t spapr_tce_get_min_page_size(MemoryRegion *iommu) |
153 | { | |
154 | sPAPRTCETable *tcet = container_of(iommu, sPAPRTCETable, iommu); | |
155 | ||
156 | return 1ULL << tcet->page_shift; | |
157 | } | |
158 | ||
5bf3d319 PX |
159 | static void spapr_tce_notify_flag_changed(MemoryRegion *iommu, |
160 | IOMMUNotifierFlag old, | |
161 | IOMMUNotifierFlag new) | |
606b5498 | 162 | { |
5bf3d319 | 163 | struct sPAPRTCETable *tbl = container_of(iommu, sPAPRTCETable, iommu); |
606b5498 | 164 | |
5bf3d319 PX |
165 | if (old == IOMMU_NOTIFIER_NONE && new != IOMMU_NOTIFIER_NONE) { |
166 | spapr_tce_set_need_vfio(tbl, true); | |
167 | } else if (old != IOMMU_NOTIFIER_NONE && new == IOMMU_NOTIFIER_NONE) { | |
168 | spapr_tce_set_need_vfio(tbl, false); | |
169 | } | |
606b5498 AK |
170 | } |
171 | ||
ee9a569a AK |
172 | static int spapr_tce_table_post_load(void *opaque, int version_id) |
173 | { | |
174 | sPAPRTCETable *tcet = SPAPR_TCE_TABLE(opaque); | |
a26fdf39 AK |
175 | uint32_t old_nb_table = tcet->nb_table; |
176 | uint64_t old_bus_offset = tcet->bus_offset; | |
177 | uint32_t old_page_shift = tcet->page_shift; | |
ee9a569a AK |
178 | |
179 | if (tcet->vdev) { | |
180 | spapr_vio_set_bypass(tcet->vdev, tcet->bypass); | |
181 | } | |
182 | ||
a26fdf39 AK |
183 | if (tcet->mig_nb_table != tcet->nb_table) { |
184 | spapr_tce_table_disable(tcet); | |
185 | } | |
186 | ||
187 | if (tcet->mig_nb_table) { | |
188 | if (!tcet->nb_table) { | |
189 | spapr_tce_table_enable(tcet, old_page_shift, old_bus_offset, | |
190 | tcet->mig_nb_table); | |
191 | } | |
192 | ||
193 | memcpy(tcet->table, tcet->mig_table, | |
194 | tcet->nb_table * sizeof(tcet->table[0])); | |
195 | ||
196 | free(tcet->mig_table); | |
197 | tcet->mig_table = NULL; | |
198 | } | |
199 | ||
200 | trace_spapr_iommu_post_load(tcet->liobn, old_nb_table, tcet->nb_table, | |
201 | tcet->bus_offset, tcet->page_shift); | |
202 | ||
ee9a569a AK |
203 | return 0; |
204 | } | |
205 | ||
a26fdf39 AK |
206 | static bool spapr_tce_table_ex_needed(void *opaque) |
207 | { | |
208 | sPAPRTCETable *tcet = opaque; | |
209 | ||
210 | return tcet->bus_offset || tcet->page_shift != 0xC; | |
211 | } | |
212 | ||
213 | static const VMStateDescription vmstate_spapr_tce_table_ex = { | |
214 | .name = "spapr_iommu_ex", | |
215 | .version_id = 1, | |
216 | .minimum_version_id = 1, | |
217 | .needed = spapr_tce_table_ex_needed, | |
218 | .fields = (VMStateField[]) { | |
219 | VMSTATE_UINT64(bus_offset, sPAPRTCETable), | |
220 | VMSTATE_UINT32(page_shift, sPAPRTCETable), | |
221 | VMSTATE_END_OF_LIST() | |
222 | }, | |
223 | }; | |
224 | ||
a83000f5 AL |
225 | static const VMStateDescription vmstate_spapr_tce_table = { |
226 | .name = "spapr_iommu", | |
523e7b8a AK |
227 | .version_id = 2, |
228 | .minimum_version_id = 2, | |
a26fdf39 | 229 | .pre_save = spapr_tce_table_pre_save, |
ee9a569a | 230 | .post_load = spapr_tce_table_post_load, |
523e7b8a | 231 | .fields = (VMStateField []) { |
a83000f5 AL |
232 | /* Sanity check */ |
233 | VMSTATE_UINT32_EQUAL(liobn, sPAPRTCETable), | |
a83000f5 AL |
234 | |
235 | /* IOMMU state */ | |
a26fdf39 | 236 | VMSTATE_UINT32(mig_nb_table, sPAPRTCETable), |
a83000f5 | 237 | VMSTATE_BOOL(bypass, sPAPRTCETable), |
a26fdf39 AK |
238 | VMSTATE_VARRAY_UINT32_ALLOC(mig_table, sPAPRTCETable, mig_nb_table, 0, |
239 | vmstate_info_uint64, uint64_t), | |
a83000f5 AL |
240 | |
241 | VMSTATE_END_OF_LIST() | |
242 | }, | |
a26fdf39 AK |
243 | .subsections = (const VMStateDescription*[]) { |
244 | &vmstate_spapr_tce_table_ex, | |
245 | NULL | |
246 | } | |
a83000f5 AL |
247 | }; |
248 | ||
a84bb436 PB |
249 | static MemoryRegionIOMMUOps spapr_iommu_ops = { |
250 | .translate = spapr_tce_translate_iommu, | |
f682e9c2 | 251 | .get_min_page_size = spapr_tce_get_min_page_size, |
5bf3d319 | 252 | .notify_flag_changed = spapr_tce_notify_flag_changed, |
a84bb436 | 253 | }; |
ad0ebb91 | 254 | |
a83000f5 | 255 | static int spapr_tce_table_realize(DeviceState *dev) |
ad0ebb91 | 256 | { |
a83000f5 | 257 | sPAPRTCETable *tcet = SPAPR_TCE_TABLE(dev); |
b4b6eb77 AK |
258 | Object *tcetobj = OBJECT(tcet); |
259 | char tmp[32]; | |
ad0ebb91 | 260 | |
fec5d3a1 | 261 | tcet->fd = -1; |
df7625d4 | 262 | tcet->need_vfio = false; |
b4b6eb77 AK |
263 | snprintf(tmp, sizeof(tmp), "tce-root-%x", tcet->liobn); |
264 | memory_region_init(&tcet->root, tcetobj, tmp, UINT64_MAX); | |
265 | ||
266 | snprintf(tmp, sizeof(tmp), "tce-iommu-%x", tcet->liobn); | |
267 | memory_region_init_iommu(&tcet->iommu, tcetobj, &spapr_iommu_ops, tmp, 0); | |
a84bb436 | 268 | |
ad0ebb91 DG |
269 | QLIST_INSERT_HEAD(&spapr_tce_tables, tcet, list); |
270 | ||
00d4f525 AK |
271 | vmstate_register(DEVICE(tcet), tcet->liobn, &vmstate_spapr_tce_table, |
272 | tcet); | |
273 | ||
a83000f5 AL |
274 | return 0; |
275 | } | |
276 | ||
c10325d6 DG |
277 | void spapr_tce_set_need_vfio(sPAPRTCETable *tcet, bool need_vfio) |
278 | { | |
279 | size_t table_size = tcet->nb_table * sizeof(uint64_t); | |
280 | void *newtable; | |
281 | ||
282 | if (need_vfio == tcet->need_vfio) { | |
283 | /* Nothing to do */ | |
284 | return; | |
285 | } | |
286 | ||
287 | if (!need_vfio) { | |
288 | /* FIXME: We don't support transition back to KVM accelerated | |
289 | * TCEs yet */ | |
290 | return; | |
291 | } | |
292 | ||
293 | tcet->need_vfio = true; | |
294 | ||
295 | if (tcet->fd < 0) { | |
296 | /* Table is already in userspace, nothing to be do */ | |
297 | return; | |
298 | } | |
299 | ||
300 | newtable = g_malloc(table_size); | |
301 | memcpy(newtable, tcet->table, table_size); | |
302 | ||
303 | kvmppc_remove_spapr_tce(tcet->table, tcet->fd, tcet->nb_table); | |
304 | ||
305 | tcet->fd = -1; | |
306 | tcet->table = newtable; | |
307 | } | |
308 | ||
df7625d4 | 309 | sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn) |
a83000f5 AL |
310 | { |
311 | sPAPRTCETable *tcet; | |
df7625d4 | 312 | char tmp[32]; |
a83000f5 AL |
313 | |
314 | if (spapr_tce_find_by_liobn(liobn)) { | |
ce9863b7 CLG |
315 | error_report("Attempted to create TCE table with duplicate" |
316 | " LIOBN 0x%x", liobn); | |
a83000f5 AL |
317 | return NULL; |
318 | } | |
319 | ||
a83000f5 AL |
320 | tcet = SPAPR_TCE_TABLE(object_new(TYPE_SPAPR_TCE_TABLE)); |
321 | tcet->liobn = liobn; | |
a83000f5 | 322 | |
dea1b3ce AK |
323 | snprintf(tmp, sizeof(tmp), "tce-table-%x", liobn); |
324 | object_property_add_child(OBJECT(owner), tmp, OBJECT(tcet), NULL); | |
a83000f5 | 325 | |
e4c35b78 | 326 | object_property_set_bool(OBJECT(tcet), true, "realized", NULL); |
a83000f5 | 327 | |
2b7dc949 | 328 | return tcet; |
ad0ebb91 DG |
329 | } |
330 | ||
df7625d4 AK |
331 | void spapr_tce_table_enable(sPAPRTCETable *tcet, |
332 | uint32_t page_shift, uint64_t bus_offset, | |
333 | uint32_t nb_table) | |
334 | { | |
335 | if (tcet->nb_table) { | |
336 | error_report("Warning: trying to enable already enabled TCE table"); | |
337 | return; | |
338 | } | |
339 | ||
340 | tcet->bus_offset = bus_offset; | |
341 | tcet->page_shift = page_shift; | |
342 | tcet->nb_table = nb_table; | |
343 | tcet->table = spapr_tce_alloc_table(tcet->liobn, | |
344 | tcet->page_shift, | |
345 | tcet->nb_table, | |
346 | &tcet->fd, | |
347 | tcet->need_vfio); | |
348 | ||
349 | memory_region_set_size(&tcet->iommu, | |
350 | (uint64_t)tcet->nb_table << tcet->page_shift); | |
b4b6eb77 | 351 | memory_region_add_subregion(&tcet->root, tcet->bus_offset, &tcet->iommu); |
df7625d4 AK |
352 | } |
353 | ||
a26fdf39 | 354 | void spapr_tce_table_disable(sPAPRTCETable *tcet) |
df7625d4 AK |
355 | { |
356 | if (!tcet->nb_table) { | |
357 | return; | |
358 | } | |
359 | ||
b4b6eb77 | 360 | memory_region_del_subregion(&tcet->root, &tcet->iommu); |
df7625d4 AK |
361 | memory_region_set_size(&tcet->iommu, 0); |
362 | ||
363 | spapr_tce_free_table(tcet->table, tcet->fd, tcet->nb_table); | |
364 | tcet->fd = -1; | |
365 | tcet->table = NULL; | |
366 | tcet->bus_offset = 0; | |
367 | tcet->page_shift = 0; | |
368 | tcet->nb_table = 0; | |
369 | } | |
370 | ||
5f9490de | 371 | static void spapr_tce_table_unrealize(DeviceState *dev, Error **errp) |
ad0ebb91 | 372 | { |
5f9490de | 373 | sPAPRTCETable *tcet = SPAPR_TCE_TABLE(dev); |
a83000f5 | 374 | |
2b7dc949 | 375 | QLIST_REMOVE(tcet, list); |
ad0ebb91 | 376 | |
df7625d4 | 377 | spapr_tce_table_disable(tcet); |
ad0ebb91 DG |
378 | } |
379 | ||
a84bb436 PB |
380 | MemoryRegion *spapr_tce_get_iommu(sPAPRTCETable *tcet) |
381 | { | |
b4b6eb77 | 382 | return &tcet->root; |
a84bb436 PB |
383 | } |
384 | ||
a83000f5 | 385 | static void spapr_tce_reset(DeviceState *dev) |
eddeed26 | 386 | { |
a83000f5 | 387 | sPAPRTCETable *tcet = SPAPR_TCE_TABLE(dev); |
523e7b8a | 388 | size_t table_size = tcet->nb_table * sizeof(uint64_t); |
eddeed26 | 389 | |
57c0eb1e DG |
390 | if (tcet->nb_table) { |
391 | memset(tcet->table, 0, table_size); | |
392 | } | |
eddeed26 DG |
393 | } |
394 | ||
edded454 DG |
395 | static target_ulong put_tce_emu(sPAPRTCETable *tcet, target_ulong ioba, |
396 | target_ulong tce) | |
397 | { | |
a84bb436 | 398 | IOMMUTLBEntry entry; |
650f33ad | 399 | hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift); |
1b8eceee | 400 | unsigned long index = (ioba - tcet->bus_offset) >> tcet->page_shift; |
edded454 | 401 | |
1b8eceee | 402 | if (index >= tcet->nb_table) { |
b55519a0 | 403 | hcall_dprintf("spapr_vio_put_tce on out-of-bounds IOBA 0x" |
edded454 DG |
404 | TARGET_FMT_lx "\n", ioba); |
405 | return H_PARAMETER; | |
406 | } | |
407 | ||
1b8eceee | 408 | tcet->table[index] = tce; |
edded454 | 409 | |
a84bb436 | 410 | entry.target_as = &address_space_memory, |
d78c19b5 | 411 | entry.iova = (ioba - tcet->bus_offset) & page_mask; |
650f33ad AK |
412 | entry.translated_addr = tce & page_mask; |
413 | entry.addr_mask = ~page_mask; | |
5709af3b | 414 | entry.perm = spapr_tce_iommu_access_flags(tce); |
a84bb436 PB |
415 | memory_region_notify_iommu(&tcet->iommu, entry); |
416 | ||
edded454 DG |
417 | return H_SUCCESS; |
418 | } | |
ad0ebb91 | 419 | |
da95324e | 420 | static target_ulong h_put_tce_indirect(PowerPCCPU *cpu, |
28e02042 | 421 | sPAPRMachineState *spapr, |
da95324e AK |
422 | target_ulong opcode, target_ulong *args) |
423 | { | |
424 | int i; | |
425 | target_ulong liobn = args[0]; | |
426 | target_ulong ioba = args[1]; | |
427 | target_ulong ioba1 = ioba; | |
428 | target_ulong tce_list = args[2]; | |
429 | target_ulong npages = args[3]; | |
f1215ea7 | 430 | target_ulong ret = H_PARAMETER, tce = 0; |
da95324e AK |
431 | sPAPRTCETable *tcet = spapr_tce_find_by_liobn(liobn); |
432 | CPUState *cs = CPU(cpu); | |
650f33ad | 433 | hwaddr page_mask, page_size; |
da95324e AK |
434 | |
435 | if (!tcet) { | |
436 | return H_PARAMETER; | |
437 | } | |
438 | ||
650f33ad | 439 | if ((npages > 512) || (tce_list & SPAPR_TCE_PAGE_MASK)) { |
da95324e AK |
440 | return H_PARAMETER; |
441 | } | |
442 | ||
650f33ad AK |
443 | page_mask = IOMMU_PAGE_MASK(tcet->page_shift); |
444 | page_size = IOMMU_PAGE_SIZE(tcet->page_shift); | |
445 | ioba &= page_mask; | |
446 | ||
447 | for (i = 0; i < npages; ++i, ioba += page_size) { | |
4d9ab7d4 | 448 | tce = ldq_be_phys(cs->as, tce_list + i * sizeof(target_ulong)); |
da95324e | 449 | |
da95324e AK |
450 | ret = put_tce_emu(tcet, ioba, tce); |
451 | if (ret) { | |
452 | break; | |
453 | } | |
454 | } | |
455 | ||
456 | /* Trace last successful or the first problematic entry */ | |
457 | i = i ? (i - 1) : 0; | |
d9d96a3c AK |
458 | if (SPAPR_IS_PCI_LIOBN(liobn)) { |
459 | trace_spapr_iommu_pci_indirect(liobn, ioba1, tce_list, i, tce, ret); | |
460 | } else { | |
461 | trace_spapr_iommu_indirect(liobn, ioba1, tce_list, i, tce, ret); | |
462 | } | |
da95324e AK |
463 | return ret; |
464 | } | |
465 | ||
28e02042 | 466 | static target_ulong h_stuff_tce(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
da95324e AK |
467 | target_ulong opcode, target_ulong *args) |
468 | { | |
469 | int i; | |
470 | target_ulong liobn = args[0]; | |
471 | target_ulong ioba = args[1]; | |
472 | target_ulong tce_value = args[2]; | |
473 | target_ulong npages = args[3]; | |
474 | target_ulong ret = H_PARAMETER; | |
475 | sPAPRTCETable *tcet = spapr_tce_find_by_liobn(liobn); | |
650f33ad | 476 | hwaddr page_mask, page_size; |
da95324e AK |
477 | |
478 | if (!tcet) { | |
479 | return H_PARAMETER; | |
480 | } | |
481 | ||
482 | if (npages > tcet->nb_table) { | |
483 | return H_PARAMETER; | |
484 | } | |
485 | ||
650f33ad AK |
486 | page_mask = IOMMU_PAGE_MASK(tcet->page_shift); |
487 | page_size = IOMMU_PAGE_SIZE(tcet->page_shift); | |
488 | ioba &= page_mask; | |
da95324e | 489 | |
650f33ad | 490 | for (i = 0; i < npages; ++i, ioba += page_size) { |
da95324e AK |
491 | ret = put_tce_emu(tcet, ioba, tce_value); |
492 | if (ret) { | |
493 | break; | |
494 | } | |
495 | } | |
d9d96a3c AK |
496 | if (SPAPR_IS_PCI_LIOBN(liobn)) { |
497 | trace_spapr_iommu_pci_stuff(liobn, ioba, tce_value, npages, ret); | |
498 | } else { | |
499 | trace_spapr_iommu_stuff(liobn, ioba, tce_value, npages, ret); | |
500 | } | |
da95324e AK |
501 | |
502 | return ret; | |
503 | } | |
504 | ||
28e02042 | 505 | static target_ulong h_put_tce(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
ad0ebb91 DG |
506 | target_ulong opcode, target_ulong *args) |
507 | { | |
508 | target_ulong liobn = args[0]; | |
509 | target_ulong ioba = args[1]; | |
510 | target_ulong tce = args[2]; | |
7e472264 | 511 | target_ulong ret = H_PARAMETER; |
ad0ebb91 | 512 | sPAPRTCETable *tcet = spapr_tce_find_by_liobn(liobn); |
ad0ebb91 | 513 | |
edded454 | 514 | if (tcet) { |
650f33ad AK |
515 | hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift); |
516 | ||
517 | ioba &= page_mask; | |
518 | ||
7e472264 | 519 | ret = put_tce_emu(tcet, ioba, tce); |
edded454 | 520 | } |
d9d96a3c AK |
521 | if (SPAPR_IS_PCI_LIOBN(liobn)) { |
522 | trace_spapr_iommu_pci_put(liobn, ioba, tce, ret); | |
523 | } else { | |
524 | trace_spapr_iommu_put(liobn, ioba, tce, ret); | |
525 | } | |
ad0ebb91 | 526 | |
7e472264 | 527 | return ret; |
ad0ebb91 DG |
528 | } |
529 | ||
a0fcac9c LD |
530 | static target_ulong get_tce_emu(sPAPRTCETable *tcet, target_ulong ioba, |
531 | target_ulong *tce) | |
532 | { | |
1b8eceee AK |
533 | unsigned long index = (ioba - tcet->bus_offset) >> tcet->page_shift; |
534 | ||
535 | if (index >= tcet->nb_table) { | |
a0fcac9c LD |
536 | hcall_dprintf("spapr_iommu_get_tce on out-of-bounds IOBA 0x" |
537 | TARGET_FMT_lx "\n", ioba); | |
538 | return H_PARAMETER; | |
539 | } | |
540 | ||
1b8eceee | 541 | *tce = tcet->table[index]; |
a0fcac9c LD |
542 | |
543 | return H_SUCCESS; | |
544 | } | |
545 | ||
28e02042 | 546 | static target_ulong h_get_tce(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
a0fcac9c LD |
547 | target_ulong opcode, target_ulong *args) |
548 | { | |
549 | target_ulong liobn = args[0]; | |
550 | target_ulong ioba = args[1]; | |
551 | target_ulong tce = 0; | |
552 | target_ulong ret = H_PARAMETER; | |
553 | sPAPRTCETable *tcet = spapr_tce_find_by_liobn(liobn); | |
554 | ||
a0fcac9c | 555 | if (tcet) { |
650f33ad AK |
556 | hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift); |
557 | ||
558 | ioba &= page_mask; | |
559 | ||
a0fcac9c LD |
560 | ret = get_tce_emu(tcet, ioba, &tce); |
561 | if (!ret) { | |
562 | args[0] = tce; | |
563 | } | |
564 | } | |
d9d96a3c AK |
565 | if (SPAPR_IS_PCI_LIOBN(liobn)) { |
566 | trace_spapr_iommu_pci_get(liobn, ioba, ret, tce); | |
567 | } else { | |
568 | trace_spapr_iommu_get(liobn, ioba, ret, tce); | |
569 | } | |
a0fcac9c LD |
570 | |
571 | return ret; | |
572 | } | |
573 | ||
ad0ebb91 | 574 | int spapr_dma_dt(void *fdt, int node_off, const char *propname, |
5c4cbcf2 | 575 | uint32_t liobn, uint64_t window, uint32_t size) |
ad0ebb91 | 576 | { |
5c4cbcf2 AK |
577 | uint32_t dma_prop[5]; |
578 | int ret; | |
579 | ||
580 | dma_prop[0] = cpu_to_be32(liobn); | |
581 | dma_prop[1] = cpu_to_be32(window >> 32); | |
582 | dma_prop[2] = cpu_to_be32(window & 0xFFFFFFFF); | |
583 | dma_prop[3] = 0; /* window size is 32 bits */ | |
584 | dma_prop[4] = cpu_to_be32(size); | |
585 | ||
586 | ret = fdt_setprop_cell(fdt, node_off, "ibm,#dma-address-cells", 2); | |
587 | if (ret < 0) { | |
588 | return ret; | |
589 | } | |
ad0ebb91 | 590 | |
5c4cbcf2 AK |
591 | ret = fdt_setprop_cell(fdt, node_off, "ibm,#dma-size-cells", 2); |
592 | if (ret < 0) { | |
593 | return ret; | |
594 | } | |
ad0ebb91 | 595 | |
5c4cbcf2 AK |
596 | ret = fdt_setprop(fdt, node_off, propname, dma_prop, sizeof(dma_prop)); |
597 | if (ret < 0) { | |
598 | return ret; | |
ad0ebb91 DG |
599 | } |
600 | ||
601 | return 0; | |
602 | } | |
5c4cbcf2 AK |
603 | |
604 | int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname, | |
2b7dc949 | 605 | sPAPRTCETable *tcet) |
5c4cbcf2 | 606 | { |
2b7dc949 | 607 | if (!tcet) { |
5c4cbcf2 AK |
608 | return 0; |
609 | } | |
610 | ||
2b7dc949 | 611 | return spapr_dma_dt(fdt, node_off, propname, |
650f33ad | 612 | tcet->liobn, 0, tcet->nb_table << tcet->page_shift); |
5c4cbcf2 | 613 | } |
a83000f5 AL |
614 | |
615 | static void spapr_tce_table_class_init(ObjectClass *klass, void *data) | |
616 | { | |
617 | DeviceClass *dc = DEVICE_CLASS(klass); | |
a83000f5 AL |
618 | dc->init = spapr_tce_table_realize; |
619 | dc->reset = spapr_tce_reset; | |
5f9490de | 620 | dc->unrealize = spapr_tce_table_unrealize; |
a83000f5 AL |
621 | |
622 | QLIST_INIT(&spapr_tce_tables); | |
623 | ||
624 | /* hcall-tce */ | |
625 | spapr_register_hypercall(H_PUT_TCE, h_put_tce); | |
a0fcac9c | 626 | spapr_register_hypercall(H_GET_TCE, h_get_tce); |
da95324e AK |
627 | spapr_register_hypercall(H_PUT_TCE_INDIRECT, h_put_tce_indirect); |
628 | spapr_register_hypercall(H_STUFF_TCE, h_stuff_tce); | |
a83000f5 AL |
629 | } |
630 | ||
631 | static TypeInfo spapr_tce_table_info = { | |
632 | .name = TYPE_SPAPR_TCE_TABLE, | |
633 | .parent = TYPE_DEVICE, | |
634 | .instance_size = sizeof(sPAPRTCETable), | |
635 | .class_init = spapr_tce_table_class_init, | |
a83000f5 AL |
636 | }; |
637 | ||
638 | static void register_types(void) | |
639 | { | |
640 | type_register_static(&spapr_tce_table_info); | |
641 | } | |
642 | ||
643 | type_init(register_types); |