[qemu.git] / hw / xtensa / xtfpga.c

/*
 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *     * Redistributions of source code must retain the above copyright
 *       notice, this list of conditions and the following disclaimer.
 *     * Redistributions in binary form must reproduce the above copyright
 *       notice, this list of conditions and the following disclaimer in the
 *       documentation and/or other materials provided with the distribution.
 *     * Neither the name of the Open Source and Linux Lab nor the
 *       names of its contributors may be used to endorse or promote products
 *       derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#include "sysemu/sysemu.h"
#include "hw/boards.h"
#include "hw/loader.h"
#include "elf.h"
#include "exec/memory.h"
#include "exec/address-spaces.h"
#include "hw/char/serial.h"
#include "net/net.h"
#include "hw/sysbus.h"
#include "hw/block/flash.h"
#include "sysemu/block-backend.h"
#include "sysemu/char.h"
#include "sysemu/device_tree.h"
#include "qemu/error-report.h"
#include "bootparam.h"

typedef struct LxBoardDesc {
    hwaddr flash_base;
    size_t flash_size;
    size_t flash_boot_base;
    size_t flash_sector_size;
    size_t sram_size;
} LxBoardDesc;

typedef struct Lx60FpgaState {
    MemoryRegion iomem;
    uint32_t leds;
    uint32_t switches;
} Lx60FpgaState;

static void lx60_fpga_reset(void *opaque)
{
    Lx60FpgaState *s = opaque;

    s->leds = 0;
    s->switches = 0;
}

static uint64_t lx60_fpga_read(void *opaque, hwaddr addr,
        unsigned size)
{
    Lx60FpgaState *s = opaque;

    switch (addr) {
    case 0x0: /*build date code*/
        return 0x09272011;

    case 0x4: /*processor clock frequency, Hz*/
        return 10000000;

    case 0x8: /*LEDs (off = 0, on = 1)*/
        return s->leds;

    case 0xc: /*DIP switches (off = 0, on = 1)*/
        return s->switches;
    }
    return 0;
}

static void lx60_fpga_write(void *opaque, hwaddr addr,
        uint64_t val, unsigned size)
{
    Lx60FpgaState *s = opaque;

    switch (addr) {
    case 0x8: /*LEDs (off = 0, on = 1)*/
        s->leds = val;
        break;

    case 0x10: /*board reset*/
        if (val == 0xdead) {
            qemu_system_reset_request();
        }
        break;
    }
}

static const MemoryRegionOps lx60_fpga_ops = {
    .read = lx60_fpga_read,
    .write = lx60_fpga_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static Lx60FpgaState *lx60_fpga_init(MemoryRegion *address_space,
        hwaddr base)
{
    Lx60FpgaState *s = g_malloc(sizeof(Lx60FpgaState));

    memory_region_init_io(&s->iomem, NULL, &lx60_fpga_ops, s,
            "lx60.fpga", 0x10000);
    memory_region_add_subregion(address_space, base, &s->iomem);
    lx60_fpga_reset(s);
    qemu_register_reset(lx60_fpga_reset, s);
    return s;
}

static void lx60_net_init(MemoryRegion *address_space,
        hwaddr base,
        hwaddr descriptors,
        hwaddr buffers,
        qemu_irq irq, NICInfo *nd)
{
    DeviceState *dev;
    SysBusDevice *s;
    MemoryRegion *ram;

    dev = qdev_create(NULL, "open_eth");
    qdev_set_nic_properties(dev, nd);
    qdev_init_nofail(dev);

    s = SYS_BUS_DEVICE(dev);
    sysbus_connect_irq(s, 0, irq);
    memory_region_add_subregion(address_space, base,
            sysbus_mmio_get_region(s, 0));
    memory_region_add_subregion(address_space, descriptors,
            sysbus_mmio_get_region(s, 1));

    ram = g_malloc(sizeof(*ram));
    memory_region_init_ram(ram, OBJECT(s), "open_eth.ram", 16384, &error_abort);
    vmstate_register_ram_global(ram);
    memory_region_add_subregion(address_space, buffers, ram);
}

static uint64_t translate_phys_addr(void *opaque, uint64_t addr)
{
    XtensaCPU *cpu = opaque;

    return cpu_get_phys_page_debug(CPU(cpu), addr);
}

static void lx60_reset(void *opaque)
{
    XtensaCPU *cpu = opaque;

    cpu_reset(CPU(cpu));
}

static void lx_init(const LxBoardDesc *board, MachineState *machine)
{
#ifdef TARGET_WORDS_BIGENDIAN
    int be = 1;
#else
    int be = 0;
#endif
    MemoryRegion *system_memory = get_system_memory();
    XtensaCPU *cpu = NULL;
    CPUXtensaState *env = NULL;
    MemoryRegion *ram, *rom, *system_io;
    DriveInfo *dinfo;
    pflash_t *flash = NULL;
    QemuOpts *machine_opts = qemu_get_machine_opts();
    const char *cpu_model = machine->cpu_model;
    const char *kernel_filename = qemu_opt_get(machine_opts, "kernel");
    const char *kernel_cmdline = qemu_opt_get(machine_opts, "append");
    const char *dtb_filename = qemu_opt_get(machine_opts, "dtb");
    const char *initrd_filename = qemu_opt_get(machine_opts, "initrd");
    int n;

    if (!cpu_model) {
        cpu_model = XTENSA_DEFAULT_CPU_MODEL;
    }

    for (n = 0; n < smp_cpus; n++) {
        cpu = cpu_xtensa_init(cpu_model);
        if (cpu == NULL) {
            error_report("unable to find CPU definition '%s'\n",
                         cpu_model);
            exit(EXIT_FAILURE);
        }
        env = &cpu->env;

        env->sregs[PRID] = n;
        qemu_register_reset(lx60_reset, cpu);
        /* Need MMU initialized prior to ELF loading,
         * so that ELF gets loaded into virtual addresses
         */
        cpu_reset(CPU(cpu));
    }

    ram = g_malloc(sizeof(*ram));
    memory_region_init_ram(ram, NULL, "lx60.dram", machine->ram_size,
                           &error_abort);
    vmstate_register_ram_global(ram);
    memory_region_add_subregion(system_memory, 0, ram);

    system_io = g_malloc(sizeof(*system_io));
    memory_region_init(system_io, NULL, "lx60.io", 224 * 1024 * 1024);
    memory_region_add_subregion(system_memory, 0xf0000000, system_io);
    lx60_fpga_init(system_io, 0x0d020000);
    if (nd_table[0].used) {
        lx60_net_init(system_io, 0x0d030000, 0x0d030400, 0x0d800000,
                xtensa_get_extint(env, 1), nd_table);
    }

    if (!serial_hds[0]) {
        serial_hds[0] = qemu_chr_new("serial0", "null", NULL);
    }

    serial_mm_init(system_io, 0x0d050020, 2, xtensa_get_extint(env, 0),
            115200, serial_hds[0], DEVICE_NATIVE_ENDIAN);

    dinfo = drive_get(IF_PFLASH, 0, 0);
    if (dinfo) {
        flash = pflash_cfi01_register(board->flash_base,
                NULL, "lx60.io.flash", board->flash_size,
                blk_by_legacy_dinfo(dinfo),
                board->flash_sector_size,
                board->flash_size / board->flash_sector_size,
                4, 0x0000, 0x0000, 0x0000, 0x0000, be);
        if (flash == NULL) {
            error_report("unable to mount pflash\n");
            exit(EXIT_FAILURE);
        }
    }

    /* Use presence of kernel file name as 'boot from SRAM' switch. */
    if (kernel_filename) {
        uint32_t entry_point = env->pc;
        size_t bp_size = 3 * get_tag_size(0); /* first/last and memory tags */
        uint32_t tagptr = 0xfe000000 + board->sram_size;
        uint32_t cur_tagptr;
        BpMemInfo memory_location = {
            .type = tswap32(MEMORY_TYPE_CONVENTIONAL),
            .start = tswap32(0),
            .end = tswap32(machine->ram_size),
        };
        uint32_t lowmem_end = machine->ram_size < 0x08000000 ?
            machine->ram_size : 0x08000000;
        uint32_t cur_lowmem = QEMU_ALIGN_UP(lowmem_end / 2, 4096);

        rom = g_malloc(sizeof(*rom));
        memory_region_init_ram(rom, NULL, "lx60.sram", board->sram_size,
                               &error_abort);
        vmstate_register_ram_global(rom);
        memory_region_add_subregion(system_memory, 0xfe000000, rom);

        if (kernel_cmdline) {
            bp_size += get_tag_size(strlen(kernel_cmdline) + 1);
        }
        if (dtb_filename) {
            bp_size += get_tag_size(sizeof(uint32_t));
        }
        if (initrd_filename) {
            bp_size += get_tag_size(sizeof(BpMemInfo));
        }

        /* Put kernel bootparameters to the end of that SRAM */
        tagptr = (tagptr - bp_size) & ~0xff;
        cur_tagptr = put_tag(tagptr, BP_TAG_FIRST, 0, NULL);
        cur_tagptr = put_tag(cur_tagptr, BP_TAG_MEMORY,
                             sizeof(memory_location), &memory_location);

        if (kernel_cmdline) {
            cur_tagptr = put_tag(cur_tagptr, BP_TAG_COMMAND_LINE,
                                 strlen(kernel_cmdline) + 1, kernel_cmdline);
        }
        if (dtb_filename) {
            int fdt_size;
            void *fdt = load_device_tree(dtb_filename, &fdt_size);
            uint32_t dtb_addr = tswap32(cur_lowmem);

            if (!fdt) {
                error_report("could not load DTB '%s'\n", dtb_filename);
                exit(EXIT_FAILURE);
            }

            cpu_physical_memory_write(cur_lowmem, fdt, fdt_size);
            cur_tagptr = put_tag(cur_tagptr, BP_TAG_FDT,
                                 sizeof(dtb_addr), &dtb_addr);
            cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + fdt_size, 4096);
        }
        if (initrd_filename) {
            BpMemInfo initrd_location = { 0 };
            int initrd_size = load_ramdisk(initrd_filename, cur_lowmem,
                                           lowmem_end - cur_lowmem);

            if (initrd_size < 0) {
                initrd_size = load_image_targphys(initrd_filename,
                                                  cur_lowmem,
                                                  lowmem_end - cur_lowmem);
            }
            if (initrd_size < 0) {
                error_report("could not load initrd '%s'\n", initrd_filename);
                exit(EXIT_FAILURE);
            }
            initrd_location.start = tswap32(cur_lowmem);
            initrd_location.end = tswap32(cur_lowmem + initrd_size);
            cur_tagptr = put_tag(cur_tagptr, BP_TAG_INITRD,
                                 sizeof(initrd_location), &initrd_location);
            cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + initrd_size, 4096);
        }
        cur_tagptr = put_tag(cur_tagptr, BP_TAG_LAST, 0, NULL);
        env->regs[2] = tagptr;

        uint64_t elf_entry;
        uint64_t elf_lowaddr;
        int success = load_elf(kernel_filename, translate_phys_addr, cpu,
                &elf_entry, &elf_lowaddr, NULL, be, ELF_MACHINE, 0);
        if (success > 0) {
            entry_point = elf_entry;
        } else {
            hwaddr ep;
            int is_linux;
            success = load_uimage(kernel_filename, &ep, NULL, &is_linux,
                                  NULL, NULL);
            if (success > 0 && is_linux) {
                entry_point = ep;
            } else {
                error_report("could not load kernel '%s'\n",
                             kernel_filename);
                exit(EXIT_FAILURE);
            }
        }
        if (entry_point != env->pc) {
            static const uint8_t jx_a0[] = {
#ifdef TARGET_WORDS_BIGENDIAN
                0x0a, 0, 0,
#else
                0xa0, 0, 0,
#endif
            };
            env->regs[0] = entry_point;
            cpu_physical_memory_write(env->pc, jx_a0, sizeof(jx_a0));
        }
    } else {
        if (flash) {
            MemoryRegion *flash_mr = pflash_cfi01_get_memory(flash);
            MemoryRegion *flash_io = g_malloc(sizeof(*flash_io));

            memory_region_init_alias(flash_io, NULL, "lx60.flash",
                    flash_mr, board->flash_boot_base,
                    board->flash_size - board->flash_boot_base < 0x02000000 ?
                    board->flash_size - board->flash_boot_base : 0x02000000);
            memory_region_add_subregion(system_memory, 0xfe000000,
                    flash_io);
        }
    }
}

static void xtensa_lx60_init(MachineState *machine)
{
    static const LxBoardDesc lx60_board = {
        .flash_base = 0xf8000000,
        .flash_size = 0x00400000,
        .flash_sector_size = 0x10000,
        .sram_size = 0x20000,
    };
    lx_init(&lx60_board, machine);
}

static void xtensa_lx200_init(MachineState *machine)
{
    static const LxBoardDesc lx200_board = {
        .flash_base = 0xf8000000,
        .flash_size = 0x01000000,
        .flash_sector_size = 0x20000,
        .sram_size = 0x2000000,
    };
    lx_init(&lx200_board, machine);
}

static void xtensa_ml605_init(MachineState *machine)
{
    static const LxBoardDesc ml605_board = {
        .flash_base = 0xf8000000,
        .flash_size = 0x02000000,
        .flash_sector_size = 0x20000,
        .sram_size = 0x2000000,
    };
    lx_init(&ml605_board, machine);
}

static void xtensa_kc705_init(MachineState *machine)
{
    static const LxBoardDesc kc705_board = {
        .flash_base = 0xf0000000,
        .flash_size = 0x08000000,
        .flash_boot_base = 0x06000000,
        .flash_sector_size = 0x20000,
        .sram_size = 0x2000000,
    };
    lx_init(&kc705_board, machine);
}

static QEMUMachine xtensa_lx60_machine = {
    .name = "lx60",
    .desc = "lx60 EVB (" XTENSA_DEFAULT_CPU_MODEL ")",
    .init = xtensa_lx60_init,
    .max_cpus = 4,
};

static QEMUMachine xtensa_lx200_machine = {
    .name = "lx200",
    .desc = "lx200 EVB (" XTENSA_DEFAULT_CPU_MODEL ")",
    .init = xtensa_lx200_init,
    .max_cpus = 4,
};

static QEMUMachine xtensa_ml605_machine = {
    .name = "ml605",
    .desc = "ml605 EVB (" XTENSA_DEFAULT_CPU_MODEL ")",
    .init = xtensa_ml605_init,
    .max_cpus = 4,
};

static QEMUMachine xtensa_kc705_machine = {
    .name = "kc705",
    .desc = "kc705 EVB (" XTENSA_DEFAULT_CPU_MODEL ")",
    .init = xtensa_kc705_init,
    .max_cpus = 4,
};

static void xtensa_lx_machines_init(void)
{
    qemu_register_machine(&xtensa_lx60_machine);
    qemu_register_machine(&xtensa_lx200_machine);
    qemu_register_machine(&xtensa_ml605_machine);
    qemu_register_machine(&xtensa_kc705_machine);
}

machine_init(xtensa_lx_machines_init);
Commit	Line	Data
0200db65 MF	1	/*
	2	* Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
	3	* All rights reserved.
	4	*
	5	* Redistribution and use in source and binary forms, with or without
	6	* modification, are permitted provided that the following conditions are met:
	7	* * Redistributions of source code must retain the above copyright
	8	* notice, this list of conditions and the following disclaimer.
	9	* * Redistributions in binary form must reproduce the above copyright
	10	* notice, this list of conditions and the following disclaimer in the
	11	* documentation and/or other materials provided with the distribution.
	12	* * Neither the name of the Open Source and Linux Lab nor the
	13	* names of its contributors may be used to endorse or promote products
	14	* derived from this software without specific prior written permission.
	15	*
	16	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
	17	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
	18	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
	19	* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
	20	* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
	21	* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
	22	* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
	23	* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	24	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
	25	* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	26	*/
	27
9c17d615	28	#include "sysemu/sysemu.h"
83c9f4ca PB	29	#include "hw/boards.h"
83c9f4ca PB	30	#include "hw/loader.h"
0200db65	31	#include "elf.h"
022c62cb PB	32	#include "exec/memory.h"
022c62cb PB	33	#include "exec/address-spaces.h"
0d09e41a	34	#include "hw/char/serial.h"
1422e32d	35	#include "net/net.h"
83c9f4ca	36	#include "hw/sysbus.h"
0d09e41a	37	#include "hw/block/flash.h"
fa1d36df	38	#include "sysemu/block-backend.h"
dccfcd0e	39	#include "sysemu/char.h"
996dfe98	40	#include "sysemu/device_tree.h"
8488ab02	41	#include "qemu/error-report.h"
b707ab75	42	#include "bootparam.h"
82b25dc8 MF	43
82b25dc8 MF	44	typedef struct LxBoardDesc {
e0db904d	45	hwaddr flash_base;
82b25dc8	46	size_t flash_size;
37ed7c4b	47	size_t flash_boot_base;
82b25dc8 MF	48	size_t flash_sector_size;
	49	size_t sram_size;
	50	} LxBoardDesc;
0200db65 MF	51
	52	typedef struct Lx60FpgaState {
	53	MemoryRegion iomem;
	54	uint32_t leds;
	55	uint32_t switches;
	56	} Lx60FpgaState;
	57
	58	static void lx60_fpga_reset(void *opaque)
	59	{
	60	Lx60FpgaState *s = opaque;
	61
	62	s->leds = 0;
	63	s->switches = 0;
	64	}
	65
a8170e5e	66	static uint64_t lx60_fpga_read(void *opaque, hwaddr addr,
0200db65 MF	67	unsigned size)
	68	{
	69	Lx60FpgaState *s = opaque;
	70
	71	switch (addr) {
	72	case 0x0: /build date code/
556ba668	73	return 0x09272011;
0200db65 MF	74
	75	case 0x4: /processor clock frequency, Hz/
	76	return 10000000;
	77
	78	case 0x8: /LEDs (off = 0, on = 1)/
	79	return s->leds;
	80
	81	case 0xc: /DIP switches (off = 0, on = 1)/
	82	return s->switches;
	83	}
	84	return 0;
	85	}
	86
a8170e5e	87	static void lx60_fpga_write(void *opaque, hwaddr addr,
0200db65 MF	88	uint64_t val, unsigned size)
	89	{
	90	Lx60FpgaState *s = opaque;
	91
	92	switch (addr) {
	93	case 0x8: /LEDs (off = 0, on = 1)/
	94	s->leds = val;
	95	break;
	96
	97	case 0x10: /board reset/
	98	if (val == 0xdead) {
	99	qemu_system_reset_request();
	100	}
	101	break;
	102	}
	103	}
	104
	105	static const MemoryRegionOps lx60_fpga_ops = {
	106	.read = lx60_fpga_read,
	107	.write = lx60_fpga_write,
	108	.endianness = DEVICE_NATIVE_ENDIAN,
	109	};
	110
	111	static Lx60FpgaState lx60_fpga_init(MemoryRegion address_space,
a8170e5e	112	hwaddr base)
0200db65 MF	113	{
	114	Lx60FpgaState *s = g_malloc(sizeof(Lx60FpgaState));
	115
2c9b15ca	116	memory_region_init_io(&s->iomem, NULL, &lx60_fpga_ops, s,
556ba668	117	"lx60.fpga", 0x10000);
0200db65 MF	118	memory_region_add_subregion(address_space, base, &s->iomem);
	119	lx60_fpga_reset(s);
	120	qemu_register_reset(lx60_fpga_reset, s);
	121	return s;
	122	}
	123
	124	static void lx60_net_init(MemoryRegion *address_space,
a8170e5e AK	125	hwaddr base,
	126	hwaddr descriptors,
	127	hwaddr buffers,
0200db65 MF	128	qemu_irq irq, NICInfo *nd)
	129	{
	130	DeviceState *dev;
	131	SysBusDevice *s;
	132	MemoryRegion *ram;
	133
	134	dev = qdev_create(NULL, "open_eth");
	135	qdev_set_nic_properties(dev, nd);
	136	qdev_init_nofail(dev);
	137
1356b98d	138	s = SYS_BUS_DEVICE(dev);
0200db65 MF	139	sysbus_connect_irq(s, 0, irq);
	140	memory_region_add_subregion(address_space, base,
	141	sysbus_mmio_get_region(s, 0));
	142	memory_region_add_subregion(address_space, descriptors,
	143	sysbus_mmio_get_region(s, 1));
	144
	145	ram = g_malloc(sizeof(*ram));
49946538	146	memory_region_init_ram(ram, OBJECT(s), "open_eth.ram", 16384, &error_abort);
c5705a77	147	vmstate_register_ram_global(ram);
0200db65 MF	148	memory_region_add_subregion(address_space, buffers, ram);
	149	}
	150
00b941e5	151	static uint64_t translate_phys_addr(void *opaque, uint64_t addr)
0200db65	152	{
00b941e5 AF	153	XtensaCPU *cpu = opaque;
	154
	155	return cpu_get_phys_page_debug(CPU(cpu), addr);
0200db65 MF	156	}
0200db65 MF	157
1bba0dc9	158	static void lx60_reset(void *opaque)
0200db65	159	{
eded1267	160	XtensaCPU *cpu = opaque;
1bba0dc9	161
eded1267	162	cpu_reset(CPU(cpu));
0200db65 MF	163	}
0200db65 MF	164
3ef96221	165	static void lx_init(const LxBoardDesc board, MachineState machine)
0200db65 MF	166	{
	167	#ifdef TARGET_WORDS_BIGENDIAN
	168	int be = 1;
	169	#else
	170	int be = 0;
	171	#endif
	172	MemoryRegion *system_memory = get_system_memory();
adbb0f75	173	XtensaCPU *cpu = NULL;
5bfcb36e	174	CPUXtensaState *env = NULL;
0200db65	175	MemoryRegion ram, rom, *system_io;
82b25dc8 MF	176	DriveInfo *dinfo;
82b25dc8 MF	177	pflash_t *flash = NULL;
37b259d0	178	QemuOpts *machine_opts = qemu_get_machine_opts();
3ef96221	179	const char *cpu_model = machine->cpu_model;
37b259d0 MF	180	const char *kernel_filename = qemu_opt_get(machine_opts, "kernel");
37b259d0 MF	181	const char *kernel_cmdline = qemu_opt_get(machine_opts, "append");
996dfe98	182	const char *dtb_filename = qemu_opt_get(machine_opts, "dtb");
f55b32e7	183	const char *initrd_filename = qemu_opt_get(machine_opts, "initrd");
0200db65 MF	184	int n;
0200db65 MF	185
82b25dc8	186	if (!cpu_model) {
e38077ff	187	cpu_model = XTENSA_DEFAULT_CPU_MODEL;
82b25dc8 MF	188	}
82b25dc8 MF	189
0200db65	190	for (n = 0; n < smp_cpus; n++) {
adbb0f75 AF	191	cpu = cpu_xtensa_init(cpu_model);
adbb0f75 AF	192	if (cpu == NULL) {
8488ab02 MF	193	error_report("unable to find CPU definition '%s'\n",
	194	cpu_model);
	195	exit(EXIT_FAILURE);
0200db65	196	}
adbb0f75 AF	197	env = &cpu->env;
adbb0f75 AF	198
0200db65	199	env->sregs[PRID] = n;
eded1267	200	qemu_register_reset(lx60_reset, cpu);
0200db65 MF	201	/* Need MMU initialized prior to ELF loading,
	202	* so that ELF gets loaded into virtual addresses
	203	*/
adbb0f75	204	cpu_reset(CPU(cpu));
0200db65 MF	205	}
	206
	207	ram = g_malloc(sizeof(*ram));
49946538 HT	208	memory_region_init_ram(ram, NULL, "lx60.dram", machine->ram_size,
49946538 HT	209	&error_abort);
c5705a77	210	vmstate_register_ram_global(ram);
0200db65 MF	211	memory_region_add_subregion(system_memory, 0, ram);
0200db65 MF	212
0200db65	213	system_io = g_malloc(sizeof(*system_io));
2c9b15ca	214	memory_region_init(system_io, NULL, "lx60.io", 224 * 1024 * 1024);
0200db65 MF	215	memory_region_add_subregion(system_memory, 0xf0000000, system_io);
0200db65 MF	216	lx60_fpga_init(system_io, 0x0d020000);
a005d073	217	if (nd_table[0].used) {
0200db65 MF	218	lx60_net_init(system_io, 0x0d030000, 0x0d030400, 0x0d800000,
	219	xtensa_get_extint(env, 1), nd_table);
	220	}
	221
	222	if (!serial_hds[0]) {
	223	serial_hds[0] = qemu_chr_new("serial0", "null", NULL);
	224	}
	225
	226	serial_mm_init(system_io, 0x0d050020, 2, xtensa_get_extint(env, 0),
	227	115200, serial_hds[0], DEVICE_NATIVE_ENDIAN);
	228
82b25dc8 MF	229	dinfo = drive_get(IF_PFLASH, 0, 0);
82b25dc8 MF	230	if (dinfo) {
e0db904d	231	flash = pflash_cfi01_register(board->flash_base,
82b25dc8	232	NULL, "lx60.io.flash", board->flash_size,
4be74634	233	blk_by_legacy_dinfo(dinfo),
fa1d36df	234	board->flash_sector_size,
82b25dc8 MF	235	board->flash_size / board->flash_sector_size,
	236	4, 0x0000, 0x0000, 0x0000, 0x0000, be);
	237	if (flash == NULL) {
8488ab02 MF	238	error_report("unable to mount pflash\n");
8488ab02 MF	239	exit(EXIT_FAILURE);
82b25dc8 MF	240	}
	241	}
	242
	243	/* Use presence of kernel file name as 'boot from SRAM' switch. */
0200db65	244	if (kernel_filename) {
364d4802	245	uint32_t entry_point = env->pc;
b6edea8b	246	size_t bp_size = 3 * get_tag_size(0); /* first/last and memory tags */
a9a28591 MF	247	uint32_t tagptr = 0xfe000000 + board->sram_size;
a9a28591 MF	248	uint32_t cur_tagptr;
b6edea8b MF	249	BpMemInfo memory_location = {
	250	.type = tswap32(MEMORY_TYPE_CONVENTIONAL),
	251	.start = tswap32(0),
	252	.end = tswap32(machine->ram_size),
	253	};
996dfe98 MF	254	uint32_t lowmem_end = machine->ram_size < 0x08000000 ?
	255	machine->ram_size : 0x08000000;
	256	uint32_t cur_lowmem = QEMU_ALIGN_UP(lowmem_end / 2, 4096);
a9a28591	257
292627bb	258	rom = g_malloc(sizeof(*rom));
49946538 HT	259	memory_region_init_ram(rom, NULL, "lx60.sram", board->sram_size,
49946538 HT	260	&error_abort);
c5705a77	261	vmstate_register_ram_global(rom);
292627bb MF	262	memory_region_add_subregion(system_memory, 0xfe000000, rom);
292627bb MF	263
a9a28591 MF	264	if (kernel_cmdline) {
	265	bp_size += get_tag_size(strlen(kernel_cmdline) + 1);
	266	}
996dfe98 MF	267	if (dtb_filename) {
	268	bp_size += get_tag_size(sizeof(uint32_t));
	269	}
f55b32e7 MF	270	if (initrd_filename) {
	271	bp_size += get_tag_size(sizeof(BpMemInfo));
	272	}
a9a28591	273
292627bb	274	/* Put kernel bootparameters to the end of that SRAM */
a9a28591 MF	275	tagptr = (tagptr - bp_size) & ~0xff;
a9a28591 MF	276	cur_tagptr = put_tag(tagptr, BP_TAG_FIRST, 0, NULL);
b6edea8b MF	277	cur_tagptr = put_tag(cur_tagptr, BP_TAG_MEMORY,
b6edea8b MF	278	sizeof(memory_location), &memory_location);
a9a28591	279
292627bb	280	if (kernel_cmdline) {
a9a28591 MF	281	cur_tagptr = put_tag(cur_tagptr, BP_TAG_COMMAND_LINE,
a9a28591 MF	282	strlen(kernel_cmdline) + 1, kernel_cmdline);
292627bb	283	}
996dfe98 MF	284	if (dtb_filename) {
	285	int fdt_size;
	286	void *fdt = load_device_tree(dtb_filename, &fdt_size);
	287	uint32_t dtb_addr = tswap32(cur_lowmem);
	288
	289	if (!fdt) {
	290	error_report("could not load DTB '%s'\n", dtb_filename);
	291	exit(EXIT_FAILURE);
	292	}
	293
	294	cpu_physical_memory_write(cur_lowmem, fdt, fdt_size);
	295	cur_tagptr = put_tag(cur_tagptr, BP_TAG_FDT,
	296	sizeof(dtb_addr), &dtb_addr);
	297	cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + fdt_size, 4096);
	298	}
f55b32e7 MF	299	if (initrd_filename) {
	300	BpMemInfo initrd_location = { 0 };
	301	int initrd_size = load_ramdisk(initrd_filename, cur_lowmem,
	302	lowmem_end - cur_lowmem);
	303
	304	if (initrd_size < 0) {
	305	initrd_size = load_image_targphys(initrd_filename,
	306	cur_lowmem,
	307	lowmem_end - cur_lowmem);
	308	}
	309	if (initrd_size < 0) {
	310	error_report("could not load initrd '%s'\n", initrd_filename);
	311	exit(EXIT_FAILURE);
	312	}
	313	initrd_location.start = tswap32(cur_lowmem);
	314	initrd_location.end = tswap32(cur_lowmem + initrd_size);
	315	cur_tagptr = put_tag(cur_tagptr, BP_TAG_INITRD,
	316	sizeof(initrd_location), &initrd_location);
	317	cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + initrd_size, 4096);
	318	}
a9a28591 MF	319	cur_tagptr = put_tag(cur_tagptr, BP_TAG_LAST, 0, NULL);
	320	env->regs[2] = tagptr;
	321
0200db65 MF	322	uint64_t elf_entry;
0200db65 MF	323	uint64_t elf_lowaddr;
00b941e5	324	int success = load_elf(kernel_filename, translate_phys_addr, cpu,
0200db65 MF	325	&elf_entry, &elf_lowaddr, NULL, be, ELF_MACHINE, 0);
0200db65 MF	326	if (success > 0) {
364d4802 MF	327	entry_point = elf_entry;
	328	} else {
	329	hwaddr ep;
	330	int is_linux;
25bda50a MF	331	success = load_uimage(kernel_filename, &ep, NULL, &is_linux,
25bda50a MF	332	NULL, NULL);
364d4802 MF	333	if (success > 0 && is_linux) {
	334	entry_point = ep;
	335	} else {
	336	error_report("could not load kernel '%s'\n",
	337	kernel_filename);
	338	exit(EXIT_FAILURE);
	339	}
	340	}
	341	if (entry_point != env->pc) {
	342	static const uint8_t jx_a0[] = {
	343	#ifdef TARGET_WORDS_BIGENDIAN
	344	0x0a, 0, 0,
	345	#else
	346	0xa0, 0, 0,
	347	#endif
	348	};
	349	env->regs[0] = entry_point;
	350	cpu_physical_memory_write(env->pc, jx_a0, sizeof(jx_a0));
0200db65	351	}
82b25dc8 MF	352	} else {
	353	if (flash) {
	354	MemoryRegion *flash_mr = pflash_cfi01_get_memory(flash);
	355	MemoryRegion flash_io = g_malloc(sizeof(flash_io));
	356
2c9b15ca	357	memory_region_init_alias(flash_io, NULL, "lx60.flash",
37ed7c4b MF	358	flash_mr, board->flash_boot_base,
	359	board->flash_size - board->flash_boot_base < 0x02000000 ?
	360	board->flash_size - board->flash_boot_base : 0x02000000);
82b25dc8 MF	361	memory_region_add_subregion(system_memory, 0xfe000000,
	362	flash_io);
	363	}
0200db65 MF	364	}
	365	}
	366
3ef96221	367	static void xtensa_lx60_init(MachineState *machine)
0200db65	368	{
82b25dc8	369	static const LxBoardDesc lx60_board = {
e0db904d MF	370	.flash_base = 0xf8000000,
e0db904d MF	371	.flash_size = 0x00400000,
82b25dc8 MF	372	.flash_sector_size = 0x10000,
	373	.sram_size = 0x20000,
	374	};
3ef96221	375	lx_init(&lx60_board, machine);
82b25dc8 MF	376	}
82b25dc8 MF	377
3ef96221	378	static void xtensa_lx200_init(MachineState *machine)
82b25dc8 MF	379	{
82b25dc8 MF	380	static const LxBoardDesc lx200_board = {
e0db904d MF	381	.flash_base = 0xf8000000,
e0db904d MF	382	.flash_size = 0x01000000,
82b25dc8 MF	383	.flash_sector_size = 0x20000,
	384	.sram_size = 0x2000000,
	385	};
3ef96221	386	lx_init(&lx200_board, machine);
0200db65 MF	387	}
0200db65 MF	388
3ef96221	389	static void xtensa_ml605_init(MachineState *machine)
e0db904d MF	390	{
	391	static const LxBoardDesc ml605_board = {
	392	.flash_base = 0xf8000000,
	393	.flash_size = 0x02000000,
	394	.flash_sector_size = 0x20000,
	395	.sram_size = 0x2000000,
	396	};
3ef96221	397	lx_init(&ml605_board, machine);
e0db904d MF	398	}
e0db904d MF	399
3ef96221	400	static void xtensa_kc705_init(MachineState *machine)
e0db904d MF	401	{
	402	static const LxBoardDesc kc705_board = {
	403	.flash_base = 0xf0000000,
	404	.flash_size = 0x08000000,
37ed7c4b	405	.flash_boot_base = 0x06000000,
e0db904d MF	406	.flash_sector_size = 0x20000,
	407	.sram_size = 0x2000000,
	408	};
3ef96221	409	lx_init(&kc705_board, machine);
e0db904d MF	410	}
e0db904d MF	411
0200db65 MF	412	static QEMUMachine xtensa_lx60_machine = {
0200db65 MF	413	.name = "lx60",
e38077ff	414	.desc = "lx60 EVB (" XTENSA_DEFAULT_CPU_MODEL ")",
0200db65 MF	415	.init = xtensa_lx60_init,
	416	.max_cpus = 4,
	417	};
	418
82b25dc8 MF	419	static QEMUMachine xtensa_lx200_machine = {
82b25dc8 MF	420	.name = "lx200",
e38077ff	421	.desc = "lx200 EVB (" XTENSA_DEFAULT_CPU_MODEL ")",
82b25dc8 MF	422	.init = xtensa_lx200_init,
	423	.max_cpus = 4,
	424	};
	425
e0db904d MF	426	static QEMUMachine xtensa_ml605_machine = {
	427	.name = "ml605",
	428	.desc = "ml605 EVB (" XTENSA_DEFAULT_CPU_MODEL ")",
	429	.init = xtensa_ml605_init,
	430	.max_cpus = 4,
	431	};
	432
	433	static QEMUMachine xtensa_kc705_machine = {
	434	.name = "kc705",
	435	.desc = "kc705 EVB (" XTENSA_DEFAULT_CPU_MODEL ")",
	436	.init = xtensa_kc705_init,
	437	.max_cpus = 4,
	438	};
	439
82b25dc8	440	static void xtensa_lx_machines_init(void)
0200db65 MF	441	{
0200db65 MF	442	qemu_register_machine(&xtensa_lx60_machine);
82b25dc8	443	qemu_register_machine(&xtensa_lx200_machine);
e0db904d MF	444	qemu_register_machine(&xtensa_ml605_machine);
e0db904d MF	445	qemu_register_machine(&xtensa_kc705_machine);
0200db65 MF	446	}
0200db65 MF	447
82b25dc8	448	machine_init(xtensa_lx_machines_init);