[qemu.git] / hw / xilinx_ethlite.c

/*
 * QEMU model of the Xilinx Ethernet Lite MAC.
 *
 * Copyright (c) 2009 Edgar E. Iglesias.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "sysbus.h"
#include "hw.h"
#include "net.h"

#define D(x)
#define R_TX_BUF0     0
#define R_TX_LEN0     (0x07f4 / 4)
#define R_TX_GIE0     (0x07f8 / 4)
#define R_TX_CTRL0    (0x07fc / 4)
#define R_TX_BUF1     (0x0800 / 4)
#define R_TX_LEN1     (0x0ff4 / 4)
#define R_TX_CTRL1    (0x0ffc / 4)

#define R_RX_BUF0     (0x1000 / 4)
#define R_RX_CTRL0    (0x17fc / 4)
#define R_RX_BUF1     (0x1800 / 4)
#define R_RX_CTRL1    (0x1ffc / 4)
#define R_MAX         (0x2000 / 4)

#define GIE_GIE    0x80000000

#define CTRL_I     0x8
#define CTRL_P     0x2
#define CTRL_S     0x1

struct xlx_ethlite
{
    SysBusDevice busdev;
    qemu_irq irq;
    NICState *nic;
    NICConf conf;

    uint32_t c_tx_pingpong;
    uint32_t c_rx_pingpong;
    unsigned int txbuf;
    unsigned int rxbuf;

    uint32_t regs[R_MAX];
};

static inline void eth_pulse_irq(struct xlx_ethlite *s)
{
    /* Only the first gie reg is active.  */
    if (s->regs[R_TX_GIE0] & GIE_GIE) {
        qemu_irq_pulse(s->irq);
    }
}

static uint32_t eth_readl (void *opaque, target_phys_addr_t addr)
{
    struct xlx_ethlite *s = opaque;
    uint32_t r = 0;

    addr >>= 2;

    switch (addr)
    {
        case R_TX_GIE0:
        case R_TX_LEN0:
        case R_TX_LEN1:
        case R_TX_CTRL1:
        case R_TX_CTRL0:
        case R_RX_CTRL1:
        case R_RX_CTRL0:
            r = s->regs[addr];
            D(qemu_log("%s %x=%x\n", __func__, addr * 4, r));
            break;

        /* Rx packet data is endian fixed at the way into the rx rams. This
         * speeds things up because the ethlite MAC does not have a len
         * register. That means the CPU will issue MMIO reads for the entire
         * 2k rx buffer even for small packets.
         */
        default:
            r = s->regs[addr];
            break;
    }
    return r;
}

static void
eth_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
    struct xlx_ethlite *s = opaque;
    unsigned int base = 0;

    addr >>= 2;
    switch (addr) 
    {
        case R_TX_CTRL0:
        case R_TX_CTRL1:
            if (addr == R_TX_CTRL1)
                base = 0x800 / 4;

            D(qemu_log("%s addr=%x val=%x\n", __func__, addr * 4, value));
            if ((value & (CTRL_P | CTRL_S)) == CTRL_S) {
                qemu_send_packet(&s->nic->nc,
                                 (void *) &s->regs[base],
                                 s->regs[base + R_TX_LEN0]);
                D(qemu_log("eth_tx %d\n", s->regs[base + R_TX_LEN0]));
                if (s->regs[base + R_TX_CTRL0] & CTRL_I)
                    eth_pulse_irq(s);
            } else if ((value & (CTRL_P | CTRL_S)) == (CTRL_P | CTRL_S)) {
                memcpy(&s->conf.macaddr.a[0], &s->regs[base], 6);
                if (s->regs[base + R_TX_CTRL0] & CTRL_I)
                    eth_pulse_irq(s);
            }

            /* We are fast and get ready pretty much immediately so
               we actually never flip the S nor P bits to one.  */
            s->regs[addr] = value & ~(CTRL_P | CTRL_S);
            break;

        /* Keep these native.  */
        case R_TX_LEN0:
        case R_TX_LEN1:
        case R_TX_GIE0:
        case R_RX_CTRL0:
        case R_RX_CTRL1:
            D(qemu_log("%s addr=%x val=%x\n", __func__, addr * 4, value));
            s->regs[addr] = value;
            break;

        /* Packet data, make sure it stays BE.  */
        default:
            s->regs[addr] = cpu_to_be32(value);
            break;
    }
}

static CPUReadMemoryFunc * const eth_read[] = {
    NULL, NULL, &eth_readl,
};

static CPUWriteMemoryFunc * const eth_write[] = {
    NULL, NULL, &eth_writel,
};

static int eth_can_rx(VLANClientState *nc)
{
    struct xlx_ethlite *s = DO_UPCAST(NICState, nc, nc)->opaque;
    int r;
    r = !(s->regs[R_RX_CTRL0] & CTRL_S);
    return r;
}

static ssize_t eth_rx(VLANClientState *nc, const uint8_t *buf, size_t size)
{
    struct xlx_ethlite *s = DO_UPCAST(NICState, nc, nc)->opaque;
    unsigned int rxbase = s->rxbuf * (0x800 / 4);
    int i;

    /* DA filter.  */
    if (!(buf[0] & 0x80) && memcmp(&s->conf.macaddr.a[0], buf, 6))
        return size;

    if (s->regs[rxbase + R_RX_CTRL0] & CTRL_S) {
        D(qemu_log("ethlite lost packet %x\n", s->regs[R_RX_CTRL0]));
        return -1;
    }

    D(qemu_log("%s %d rxbase=%x\n", __func__, size, rxbase));
    memcpy(&s->regs[rxbase + R_RX_BUF0], buf, size);

    /* Bring it into host endianess.  */
    for (i = 0; i < ((size + 3) / 4); i++) {
       uint32_t d = s->regs[rxbase + R_RX_BUF0 + i];
       s->regs[rxbase + R_RX_BUF0 + i] = be32_to_cpu(d);
    }

    s->regs[rxbase + R_RX_CTRL0] |= CTRL_S;
    if (s->regs[rxbase + R_RX_CTRL0] & CTRL_I)
        eth_pulse_irq(s);

    /* If c_rx_pingpong was set flip buffers.  */
    s->rxbuf ^= s->c_rx_pingpong;
    return size;
}

static void eth_cleanup(VLANClientState *nc)
{
    struct xlx_ethlite *s = DO_UPCAST(NICState, nc, nc)->opaque;

    s->nic = NULL;
}

static NetClientInfo net_xilinx_ethlite_info = {
    .type = NET_CLIENT_TYPE_NIC,
    .size = sizeof(NICState),
    .can_receive = eth_can_rx,
    .receive = eth_rx,
    .cleanup = eth_cleanup,
};

static int xilinx_ethlite_init(SysBusDevice *dev)
{
    struct xlx_ethlite *s = FROM_SYSBUS(typeof (*s), dev);
    int regs;

    sysbus_init_irq(dev, &s->irq);
    s->rxbuf = 0;

    regs = cpu_register_io_memory(eth_read, eth_write, s, DEVICE_NATIVE_ENDIAN);
    sysbus_init_mmio(dev, R_MAX * 4, regs);

    qemu_macaddr_default_if_unset(&s->conf.macaddr);
    s->nic = qemu_new_nic(&net_xilinx_ethlite_info, &s->conf,
                          dev->qdev.info->name, dev->qdev.id, s);
    qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
    return 0;
}

static SysBusDeviceInfo xilinx_ethlite_info = {
    .init = xilinx_ethlite_init,
    .qdev.name  = "xilinx,ethlite",
    .qdev.size  = sizeof(struct xlx_ethlite),
    .qdev.props = (Property[]) {
        DEFINE_PROP_UINT32("txpingpong", struct xlx_ethlite, c_tx_pingpong, 1),
        DEFINE_PROP_UINT32("rxpingpong", struct xlx_ethlite, c_rx_pingpong, 1),
        DEFINE_NIC_PROPERTIES(struct xlx_ethlite, conf),
        DEFINE_PROP_END_OF_LIST(),
    }
};

static void xilinx_ethlite_register(void)
{
    sysbus_register_withprop(&xilinx_ethlite_info);
}

device_init(xilinx_ethlite_register)
Commit	Line	Data
b43848a1 EI	1	/*
	2	* QEMU model of the Xilinx Ethernet Lite MAC.
	3	*
	4	* Copyright (c) 2009 Edgar E. Iglesias.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24
	25	#include "sysbus.h"
	26	#include "hw.h"
	27	#include "net.h"
	28
	29	#define D(x)
	30	#define R_TX_BUF0 0
	31	#define R_TX_LEN0 (0x07f4 / 4)
	32	#define R_TX_GIE0 (0x07f8 / 4)
	33	#define R_TX_CTRL0 (0x07fc / 4)
	34	#define R_TX_BUF1 (0x0800 / 4)
	35	#define R_TX_LEN1 (0x0ff4 / 4)
	36	#define R_TX_CTRL1 (0x0ffc / 4)
	37
	38	#define R_RX_BUF0 (0x1000 / 4)
	39	#define R_RX_CTRL0 (0x17fc / 4)
	40	#define R_RX_BUF1 (0x1800 / 4)
	41	#define R_RX_CTRL1 (0x1ffc / 4)
	42	#define R_MAX (0x2000 / 4)
	43
	44	#define GIE_GIE 0x80000000
	45
	46	#define CTRL_I 0x8
	47	#define CTRL_P 0x2
	48	#define CTRL_S 0x1
	49
	50	struct xlx_ethlite
	51	{
	52	SysBusDevice busdev;
	53	qemu_irq irq;
d7539ab4	54	NICState *nic;
17d1ae3c	55	NICConf conf;
b43848a1	56
ee6847d1 GH	57	uint32_t c_tx_pingpong;
ee6847d1 GH	58	uint32_t c_rx_pingpong;
b43848a1 EI	59	unsigned int txbuf;
	60	unsigned int rxbuf;
	61
b43848a1 EI	62	uint32_t regs[R_MAX];
	63	};
	64
	65	static inline void eth_pulse_irq(struct xlx_ethlite *s)
	66	{
	67	/* Only the first gie reg is active. */
	68	if (s->regs[R_TX_GIE0] & GIE_GIE) {
	69	qemu_irq_pulse(s->irq);
	70	}
	71	}
	72
c227f099	73	static uint32_t eth_readl (void *opaque, target_phys_addr_t addr)
b43848a1 EI	74	{
	75	struct xlx_ethlite *s = opaque;
	76	uint32_t r = 0;
	77
	78	addr >>= 2;
	79
	80	switch (addr)
	81	{
	82	case R_TX_GIE0:
	83	case R_TX_LEN0:
	84	case R_TX_LEN1:
	85	case R_TX_CTRL1:
	86	case R_TX_CTRL0:
	87	case R_RX_CTRL1:
	88	case R_RX_CTRL0:
	89	r = s->regs[addr];
	90	D(qemu_log("%s %x=%x\n", __func__, addr * 4, r));
	91	break;
	92
	93	/* Rx packet data is endian fixed at the way into the rx rams. This
	94	* speeds things up because the ethlite MAC does not have a len
	95	* register. That means the CPU will issue MMIO reads for the entire
	96	* 2k rx buffer even for small packets.
	97	*/
	98	default:
	99	r = s->regs[addr];
	100	break;
	101	}
	102	return r;
	103	}
	104
	105	static void
c227f099	106	eth_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
b43848a1 EI	107	{
	108	struct xlx_ethlite *s = opaque;
	109	unsigned int base = 0;
	110
	111	addr >>= 2;
	112	switch (addr)
	113	{
	114	case R_TX_CTRL0:
	115	case R_TX_CTRL1:
	116	if (addr == R_TX_CTRL1)
	117	base = 0x800 / 4;
	118
	119	D(qemu_log("%s addr=%x val=%x\n", __func__, addr * 4, value));
	120	if ((value & (CTRL_P \| CTRL_S)) == CTRL_S) {
d7539ab4	121	qemu_send_packet(&s->nic->nc,
b43848a1 EI	122	(void *) &s->regs[base],
	123	s->regs[base + R_TX_LEN0]);
	124	D(qemu_log("eth_tx %d\n", s->regs[base + R_TX_LEN0]));
	125	if (s->regs[base + R_TX_CTRL0] & CTRL_I)
	126	eth_pulse_irq(s);
	127	} else if ((value & (CTRL_P \| CTRL_S)) == (CTRL_P \| CTRL_S)) {
17d1ae3c	128	memcpy(&s->conf.macaddr.a[0], &s->regs[base], 6);
b43848a1 EI	129	if (s->regs[base + R_TX_CTRL0] & CTRL_I)
	130	eth_pulse_irq(s);
	131	}
	132
	133	/* We are fast and get ready pretty much immediately so
	134	we actually never flip the S nor P bits to one. */
	135	s->regs[addr] = value & ~(CTRL_P \| CTRL_S);
	136	break;
	137
	138	/* Keep these native. */
	139	case R_TX_LEN0:
	140	case R_TX_LEN1:
	141	case R_TX_GIE0:
	142	case R_RX_CTRL0:
	143	case R_RX_CTRL1:
	144	D(qemu_log("%s addr=%x val=%x\n", __func__, addr * 4, value));
	145	s->regs[addr] = value;
	146	break;
	147
	148	/* Packet data, make sure it stays BE. */
	149	default:
	150	s->regs[addr] = cpu_to_be32(value);
	151	break;
	152	}
	153	}
	154
d60efc6b	155	static CPUReadMemoryFunc * const eth_read[] = {
b43848a1 EI	156	NULL, NULL, &eth_readl,
	157	};
	158
d60efc6b	159	static CPUWriteMemoryFunc * const eth_write[] = {
b43848a1 EI	160	NULL, NULL, &eth_writel,
	161	};
	162
d7539ab4	163	static int eth_can_rx(VLANClientState *nc)
b43848a1	164	{
d7539ab4	165	struct xlx_ethlite *s = DO_UPCAST(NICState, nc, nc)->opaque;
b43848a1 EI	166	int r;
b43848a1 EI	167	r = !(s->regs[R_RX_CTRL0] & CTRL_S);
b43848a1 EI	168	return r;
	169	}
	170
d7539ab4	171	static ssize_t eth_rx(VLANClientState nc, const uint8_t buf, size_t size)
b43848a1	172	{
d7539ab4	173	struct xlx_ethlite *s = DO_UPCAST(NICState, nc, nc)->opaque;
b43848a1 EI	174	unsigned int rxbase = s->rxbuf * (0x800 / 4);
	175	int i;
	176
	177	/* DA filter. */
17d1ae3c	178	if (!(buf[0] & 0x80) && memcmp(&s->conf.macaddr.a[0], buf, 6))
df12c1f5	179	return size;
b43848a1 EI	180
	181	if (s->regs[rxbase + R_RX_CTRL0] & CTRL_S) {
	182	D(qemu_log("ethlite lost packet %x\n", s->regs[R_RX_CTRL0]));
df12c1f5	183	return -1;
b43848a1 EI	184	}
	185
	186	D(qemu_log("%s %d rxbase=%x\n", __func__, size, rxbase));
	187	memcpy(&s->regs[rxbase + R_RX_BUF0], buf, size);
	188
	189	/* Bring it into host endianess. */
	190	for (i = 0; i < ((size + 3) / 4); i++) {
	191	uint32_t d = s->regs[rxbase + R_RX_BUF0 + i];
	192	s->regs[rxbase + R_RX_BUF0 + i] = be32_to_cpu(d);
	193	}
	194
	195	s->regs[rxbase + R_RX_CTRL0] \|= CTRL_S;
	196	if (s->regs[rxbase + R_RX_CTRL0] & CTRL_I)
	197	eth_pulse_irq(s);
	198
	199	/* If c_rx_pingpong was set flip buffers. */
	200	s->rxbuf ^= s->c_rx_pingpong;
df12c1f5	201	return size;
b43848a1 EI	202	}
b43848a1 EI	203
d7539ab4	204	static void eth_cleanup(VLANClientState *nc)
b43848a1	205	{
d7539ab4	206	struct xlx_ethlite *s = DO_UPCAST(NICState, nc, nc)->opaque;
17d1ae3c	207
d7539ab4	208	s->nic = NULL;
b43848a1 EI	209	}
b43848a1 EI	210
d7539ab4 MM	211	static NetClientInfo net_xilinx_ethlite_info = {
	212	.type = NET_CLIENT_TYPE_NIC,
	213	.size = sizeof(NICState),
	214	.can_receive = eth_can_rx,
	215	.receive = eth_rx,
	216	.cleanup = eth_cleanup,
	217	};
	218
81a322d4	219	static int xilinx_ethlite_init(SysBusDevice *dev)
b43848a1 EI	220	{
	221	struct xlx_ethlite s = FROM_SYSBUS(typeof (s), dev);
	222	int regs;
	223
	224	sysbus_init_irq(dev, &s->irq);
b43848a1 EI	225	s->rxbuf = 0;
b43848a1 EI	226
2507c12a	227	regs = cpu_register_io_memory(eth_read, eth_write, s, DEVICE_NATIVE_ENDIAN);
b43848a1 EI	228	sysbus_init_mmio(dev, R_MAX * 4, regs);
b43848a1 EI	229
17d1ae3c	230	qemu_macaddr_default_if_unset(&s->conf.macaddr);
d7539ab4 MM	231	s->nic = qemu_new_nic(&net_xilinx_ethlite_info, &s->conf,
	232	dev->qdev.info->name, dev->qdev.id, s);
	233	qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
81a322d4	234	return 0;
b43848a1 EI	235	}
b43848a1 EI	236
ee6847d1 GH	237	static SysBusDeviceInfo xilinx_ethlite_info = {
	238	.init = xilinx_ethlite_init,
	239	.qdev.name = "xilinx,ethlite",
	240	.qdev.size = sizeof(struct xlx_ethlite),
	241	.qdev.props = (Property[]) {
05f02579 GH	242	DEFINE_PROP_UINT32("txpingpong", struct xlx_ethlite, c_tx_pingpong, 1),
05f02579 GH	243	DEFINE_PROP_UINT32("rxpingpong", struct xlx_ethlite, c_rx_pingpong, 1),
17d1ae3c	244	DEFINE_NIC_PROPERTIES(struct xlx_ethlite, conf),
05f02579	245	DEFINE_PROP_END_OF_LIST(),
ee6847d1 GH	246	}
	247	};
	248
b43848a1 EI	249	static void xilinx_ethlite_register(void)
b43848a1 EI	250	{
ee6847d1	251	sysbus_register_withprop(&xilinx_ethlite_info);
b43848a1 EI	252	}
	253
	254	device_init(xilinx_ethlite_register)