[qemu.git] / hw / pl080.c

/*
 * Arm PrimeCell PL080/PL081 DMA controller
 *
 * Copyright (c) 2006 CodeSourcery.
 * Written by Paul Brook
 *
 * This code is licenced under the GPL.
 */

#include "sysbus.h"

#define PL080_MAX_CHANNELS 8
#define PL080_CONF_E    0x1
#define PL080_CONF_M1   0x2
#define PL080_CONF_M2   0x4

#define PL080_CCONF_H   0x40000
#define PL080_CCONF_A   0x20000
#define PL080_CCONF_L   0x10000
#define PL080_CCONF_ITC 0x08000
#define PL080_CCONF_IE  0x04000
#define PL080_CCONF_E   0x00001

#define PL080_CCTRL_I   0x80000000
#define PL080_CCTRL_DI  0x08000000
#define PL080_CCTRL_SI  0x04000000
#define PL080_CCTRL_D   0x02000000
#define PL080_CCTRL_S   0x01000000

typedef struct {
    uint32_t src;
    uint32_t dest;
    uint32_t lli;
    uint32_t ctrl;
    uint32_t conf;
} pl080_channel;

typedef struct {
    SysBusDevice busdev;
    uint8_t tc_int;
    uint8_t tc_mask;
    uint8_t err_int;
    uint8_t err_mask;
    uint32_t conf;
    uint32_t sync;
    uint32_t req_single;
    uint32_t req_burst;
    pl080_channel chan[PL080_MAX_CHANNELS];
    int nchannels;
    /* Flag to avoid recursive DMA invocations.  */
    int running;
    qemu_irq irq;
} pl080_state;

static const unsigned char pl080_id[] =
{ 0x80, 0x10, 0x04, 0x0a, 0x0d, 0xf0, 0x05, 0xb1 };

static const unsigned char pl081_id[] =
{ 0x81, 0x10, 0x04, 0x0a, 0x0d, 0xf0, 0x05, 0xb1 };

static void pl080_update(pl080_state *s)
{
    if ((s->tc_int & s->tc_mask)
            || (s->err_int & s->err_mask))
        qemu_irq_raise(s->irq);
    else
        qemu_irq_lower(s->irq);
}

static void pl080_run(pl080_state *s)
{
    int c;
    int flow;
    pl080_channel *ch;
    int swidth;
    int dwidth;
    int xsize;
    int n;
    int src_id;
    int dest_id;
    int size;
    uint8_t buff[4];
    uint32_t req;

    s->tc_mask = 0;
    for (c = 0; c < s->nchannels; c++) {
        if (s->chan[c].conf & PL080_CCONF_ITC)
            s->tc_mask |= 1 << c;
        if (s->chan[c].conf & PL080_CCONF_IE)
            s->err_mask |= 1 << c;
    }

    if ((s->conf & PL080_CONF_E) == 0)
        return;

hw_error("DMA active\n");
    /* If we are already in the middle of a DMA operation then indicate that
       there may be new DMA requests and return immediately.  */
    if (s->running) {
        s->running++;
        return;
    }
    s->running = 1;
    while (s->running) {
        for (c = 0; c < s->nchannels; c++) {
            ch = &s->chan[c];
again:
            /* Test if thiws channel has any pending DMA requests.  */
            if ((ch->conf & (PL080_CCONF_H | PL080_CCONF_E))
                    != PL080_CCONF_E)
                continue;
            flow = (ch->conf >> 11) & 7;
            if (flow >= 4) {
                hw_error(
                    "pl080_run: Peripheral flow control not implemented\n");
            }
            src_id = (ch->conf >> 1) & 0x1f;
            dest_id = (ch->conf >> 6) & 0x1f;
            size = ch->ctrl & 0xfff;
            req = s->req_single | s->req_burst;
            switch (flow) {
            case 0:
                break;
            case 1:
                if ((req & (1u << dest_id)) == 0)
                    size = 0;
                break;
            case 2:
                if ((req & (1u << src_id)) == 0)
                    size = 0;
                break;
            case 3:
                if ((req & (1u << src_id)) == 0
                        || (req & (1u << dest_id)) == 0)
                    size = 0;
                break;
            }
            if (!size)
                continue;

            /* Transfer one element.  */
            /* ??? Should transfer multiple elements for a burst request.  */
            /* ??? Unclear what the proper behavior is when source and
               destination widths are different.  */
            swidth = 1 << ((ch->ctrl >> 18) & 7);
            dwidth = 1 << ((ch->ctrl >> 21) & 7);
            for (n = 0; n < dwidth; n+= swidth) {
                cpu_physical_memory_read(ch->src, buff + n, swidth);
                if (ch->ctrl & PL080_CCTRL_SI)
                    ch->src += swidth;
            }
            xsize = (dwidth < swidth) ? swidth : dwidth;
            /* ??? This may pad the value incorrectly for dwidth < 32.  */
            for (n = 0; n < xsize; n += dwidth) {
                cpu_physical_memory_write(ch->dest + n, buff + n, dwidth);
                if (ch->ctrl & PL080_CCTRL_DI)
                    ch->dest += swidth;
            }

            size--;
            ch->ctrl = (ch->ctrl & 0xfffff000) | size;
            if (size == 0) {
                /* Transfer complete.  */
                if (ch->lli) {
                    ch->src = ldl_phys(ch->lli);
                    ch->dest = ldl_phys(ch->lli + 4);
                    ch->ctrl = ldl_phys(ch->lli + 12);
                    ch->lli = ldl_phys(ch->lli + 8);
                } else {
                    ch->conf &= ~PL080_CCONF_E;
                }
                if (ch->ctrl & PL080_CCTRL_I) {
                    s->tc_int |= 1 << c;
                }
            }
            goto again;
        }
        if (--s->running)
            s->running = 1;
    }
}

static uint32_t pl080_read(void *opaque, target_phys_addr_t offset)
{
    pl080_state *s = (pl080_state *)opaque;
    uint32_t i;
    uint32_t mask;

    if (offset >= 0xfe0 && offset < 0x1000) {
        if (s->nchannels == 8) {
            return pl080_id[(offset - 0xfe0) >> 2];
        } else {
            return pl081_id[(offset - 0xfe0) >> 2];
        }
    }
    if (offset >= 0x100 && offset < 0x200) {
        i = (offset & 0xe0) >> 5;
        if (i >= s->nchannels)
            goto bad_offset;
        switch (offset >> 2) {
        case 0: /* SrcAddr */
            return s->chan[i].src;
        case 1: /* DestAddr */
            return s->chan[i].dest;
        case 2: /* LLI */
            return s->chan[i].lli;
        case 3: /* Control */
            return s->chan[i].ctrl;
        case 4: /* Configuration */
            return s->chan[i].conf;
        default:
            goto bad_offset;
        }
    }
    switch (offset >> 2) {
    case 0: /* IntStatus */
        return (s->tc_int & s->tc_mask) | (s->err_int & s->err_mask);
    case 1: /* IntTCStatus */
        return (s->tc_int & s->tc_mask);
    case 3: /* IntErrorStatus */
        return (s->err_int & s->err_mask);
    case 5: /* RawIntTCStatus */
        return s->tc_int;
    case 6: /* RawIntErrorStatus */
        return s->err_int;
    case 7: /* EnbldChns */
        mask = 0;
        for (i = 0; i < s->nchannels; i++) {
            if (s->chan[i].conf & PL080_CCONF_E)
                mask |= 1 << i;
        }
        return mask;
    case 8: /* SoftBReq */
    case 9: /* SoftSReq */
    case 10: /* SoftLBReq */
    case 11: /* SoftLSReq */
        /* ??? Implement these. */
        return 0;
    case 12: /* Configuration */
        return s->conf;
    case 13: /* Sync */
        return s->sync;
    default:
    bad_offset:
        hw_error("pl080_read: Bad offset %x\n", (int)offset);
        return 0;
    }
}

static void pl080_write(void *opaque, target_phys_addr_t offset,
                          uint32_t value)
{
    pl080_state *s = (pl080_state *)opaque;
    int i;

    if (offset >= 0x100 && offset < 0x200) {
        i = (offset & 0xe0) >> 5;
        if (i >= s->nchannels)
            goto bad_offset;
        switch (offset >> 2) {
        case 0: /* SrcAddr */
            s->chan[i].src = value;
            break;
        case 1: /* DestAddr */
            s->chan[i].dest = value;
            break;
        case 2: /* LLI */
            s->chan[i].lli = value;
            break;
        case 3: /* Control */
            s->chan[i].ctrl = value;
            break;
        case 4: /* Configuration */
            s->chan[i].conf = value;
            pl080_run(s);
            break;
        }
    }
    switch (offset >> 2) {
    case 2: /* IntTCClear */
        s->tc_int &= ~value;
        break;
    case 4: /* IntErrorClear */
        s->err_int &= ~value;
        break;
    case 8: /* SoftBReq */
    case 9: /* SoftSReq */
    case 10: /* SoftLBReq */
    case 11: /* SoftLSReq */
        /* ??? Implement these.  */
        hw_error("pl080_write: Soft DMA not implemented\n");
        break;
    case 12: /* Configuration */
        s->conf = value;
        if (s->conf & (PL080_CONF_M1 | PL080_CONF_M1)) {
            hw_error("pl080_write: Big-endian DMA not implemented\n");
        }
        pl080_run(s);
        break;
    case 13: /* Sync */
        s->sync = value;
        break;
    default:
    bad_offset:
        hw_error("pl080_write: Bad offset %x\n", (int)offset);
    }
    pl080_update(s);
}

static CPUReadMemoryFunc * const pl080_readfn[] = {
   pl080_read,
   pl080_read,
   pl080_read
};

static CPUWriteMemoryFunc * const pl080_writefn[] = {
   pl080_write,
   pl080_write,
   pl080_write
};

static int pl08x_init(SysBusDevice *dev, int nchannels)
{
    int iomemtype;
    pl080_state *s = FROM_SYSBUS(pl080_state, dev);

    iomemtype = cpu_register_io_memory(pl080_readfn,
                                       pl080_writefn, s,
                                       DEVICE_NATIVE_ENDIAN);
    sysbus_init_mmio(dev, 0x1000, iomemtype);
    sysbus_init_irq(dev, &s->irq);
    s->nchannels = nchannels;
    /* ??? Save/restore.  */
    return 0;
}

static int pl080_init(SysBusDevice *dev)
{
    return pl08x_init(dev, 8);
}

static int pl081_init(SysBusDevice *dev)
{
    return pl08x_init(dev, 2);
}

/* The PL080 and PL081 are the same except for the number of channels
   they implement (8 and 2 respectively).  */
static void pl080_register_devices(void)
{
    sysbus_register_dev("pl080", sizeof(pl080_state), pl080_init);
    sysbus_register_dev("pl081", sizeof(pl080_state), pl081_init);
}

device_init(pl080_register_devices)
Commit	Line	Data
5fafdf24	1	/*
e69954b9	2	* Arm PrimeCell PL080/PL081 DMA controller
cdbdb648 PB	3	*
	4	* Copyright (c) 2006 CodeSourcery.
	5	* Written by Paul Brook
	6	*
	7	* This code is licenced under the GPL.
	8	*/
	9
b4496b13	10	#include "sysbus.h"
cdbdb648	11
e69954b9	12	#define PL080_MAX_CHANNELS 8
cdbdb648 PB	13	#define PL080_CONF_E 0x1
	14	#define PL080_CONF_M1 0x2
	15	#define PL080_CONF_M2 0x4
	16
	17	#define PL080_CCONF_H 0x40000
	18	#define PL080_CCONF_A 0x20000
	19	#define PL080_CCONF_L 0x10000
	20	#define PL080_CCONF_ITC 0x08000
	21	#define PL080_CCONF_IE 0x04000
	22	#define PL080_CCONF_E 0x00001
	23
	24	#define PL080_CCTRL_I 0x80000000
	25	#define PL080_CCTRL_DI 0x08000000
	26	#define PL080_CCTRL_SI 0x04000000
	27	#define PL080_CCTRL_D 0x02000000
	28	#define PL080_CCTRL_S 0x01000000
	29
	30	typedef struct {
	31	uint32_t src;
	32	uint32_t dest;
	33	uint32_t lli;
	34	uint32_t ctrl;
	35	uint32_t conf;
	36	} pl080_channel;
	37
	38	typedef struct {
b4496b13	39	SysBusDevice busdev;
cdbdb648 PB	40	uint8_t tc_int;
	41	uint8_t tc_mask;
	42	uint8_t err_int;
	43	uint8_t err_mask;
	44	uint32_t conf;
	45	uint32_t sync;
	46	uint32_t req_single;
	47	uint32_t req_burst;
e69954b9 PB	48	pl080_channel chan[PL080_MAX_CHANNELS];
e69954b9 PB	49	int nchannels;
cdbdb648 PB	50	/* Flag to avoid recursive DMA invocations. */
cdbdb648 PB	51	int running;
d537cf6c	52	qemu_irq irq;
cdbdb648 PB	53	} pl080_state;
	54
	55	static const unsigned char pl080_id[] =
	56	{ 0x80, 0x10, 0x04, 0x0a, 0x0d, 0xf0, 0x05, 0xb1 };
	57
e69954b9 PB	58	static const unsigned char pl081_id[] =
	59	{ 0x81, 0x10, 0x04, 0x0a, 0x0d, 0xf0, 0x05, 0xb1 };
	60
cdbdb648 PB	61	static void pl080_update(pl080_state *s)
	62	{
	63	if ((s->tc_int & s->tc_mask)
	64	\|\| (s->err_int & s->err_mask))
d537cf6c	65	qemu_irq_raise(s->irq);
cdbdb648	66	else
d537cf6c	67	qemu_irq_lower(s->irq);
cdbdb648 PB	68	}
	69
	70	static void pl080_run(pl080_state *s)
	71	{
	72	int c;
	73	int flow;
	74	pl080_channel *ch;
	75	int swidth;
	76	int dwidth;
	77	int xsize;
	78	int n;
	79	int src_id;
	80	int dest_id;
	81	int size;
b55266b5	82	uint8_t buff[4];
cdbdb648 PB	83	uint32_t req;
	84
	85	s->tc_mask = 0;
e69954b9	86	for (c = 0; c < s->nchannels; c++) {
cdbdb648 PB	87	if (s->chan[c].conf & PL080_CCONF_ITC)
	88	s->tc_mask \|= 1 << c;
	89	if (s->chan[c].conf & PL080_CCONF_IE)
	90	s->err_mask \|= 1 << c;
	91	}
	92
	93	if ((s->conf & PL080_CONF_E) == 0)
	94	return;
	95
2ac71179	96	hw_error("DMA active\n");
cdbdb648 PB	97	/* If we are already in the middle of a DMA operation then indicate that
	98	there may be new DMA requests and return immediately. */
	99	if (s->running) {
	100	s->running++;
	101	return;
	102	}
	103	s->running = 1;
	104	while (s->running) {
e69954b9	105	for (c = 0; c < s->nchannels; c++) {
cdbdb648 PB	106	ch = &s->chan[c];
	107	again:
	108	/* Test if thiws channel has any pending DMA requests. */
	109	if ((ch->conf & (PL080_CCONF_H \| PL080_CCONF_E))
	110	!= PL080_CCONF_E)
	111	continue;
	112	flow = (ch->conf >> 11) & 7;
	113	if (flow >= 4) {
2ac71179	114	hw_error(
cdbdb648 PB	115	"pl080_run: Peripheral flow control not implemented\n");
	116	}
	117	src_id = (ch->conf >> 1) & 0x1f;
	118	dest_id = (ch->conf >> 6) & 0x1f;
	119	size = ch->ctrl & 0xfff;
	120	req = s->req_single \| s->req_burst;
	121	switch (flow) {
	122	case 0:
	123	break;
	124	case 1:
	125	if ((req & (1u << dest_id)) == 0)
	126	size = 0;
	127	break;
	128	case 2:
	129	if ((req & (1u << src_id)) == 0)
	130	size = 0;
	131	break;
	132	case 3:
	133	if ((req & (1u << src_id)) == 0
	134	\|\| (req & (1u << dest_id)) == 0)
	135	size = 0;
	136	break;
	137	}
	138	if (!size)
	139	continue;
	140
	141	/* Transfer one element. */
	142	/* ??? Should transfer multiple elements for a burst request. */
	143	/* ??? Unclear what the proper behavior is when source and
	144	destination widths are different. */
	145	swidth = 1 << ((ch->ctrl >> 18) & 7);
	146	dwidth = 1 << ((ch->ctrl >> 21) & 7);
	147	for (n = 0; n < dwidth; n+= swidth) {
	148	cpu_physical_memory_read(ch->src, buff + n, swidth);
	149	if (ch->ctrl & PL080_CCTRL_SI)
	150	ch->src += swidth;
	151	}
	152	xsize = (dwidth < swidth) ? swidth : dwidth;
	153	/* ??? This may pad the value incorrectly for dwidth < 32. */
	154	for (n = 0; n < xsize; n += dwidth) {
	155	cpu_physical_memory_write(ch->dest + n, buff + n, dwidth);
	156	if (ch->ctrl & PL080_CCTRL_DI)
	157	ch->dest += swidth;
	158	}
	159
	160	size--;
	161	ch->ctrl = (ch->ctrl & 0xfffff000) \| size;
	162	if (size == 0) {
	163	/* Transfer complete. */
	164	if (ch->lli) {
	165	ch->src = ldl_phys(ch->lli);
	166	ch->dest = ldl_phys(ch->lli + 4);
	167	ch->ctrl = ldl_phys(ch->lli + 12);
	168	ch->lli = ldl_phys(ch->lli + 8);
	169	} else {
	170	ch->conf &= ~PL080_CCONF_E;
	171	}
	172	if (ch->ctrl & PL080_CCTRL_I) {
	173	s->tc_int \|= 1 << c;
	174	}
	175	}
	176	goto again;
	177	}
	178	if (--s->running)
179	s->running = 1;
180	}
181	}
182
c227f099	183	static uint32_t pl080_read(void *opaque, target_phys_addr_t offset)
cdbdb648 PB	184	{
	185	pl080_state s = (pl080_state )opaque;
	186	uint32_t i;
	187	uint32_t mask;
	188
cdbdb648	189	if (offset >= 0xfe0 && offset < 0x1000) {
e69954b9 PB	190	if (s->nchannels == 8) {
	191	return pl080_id[(offset - 0xfe0) >> 2];
	192	} else {
	193	return pl081_id[(offset - 0xfe0) >> 2];
	194	}
cdbdb648 PB	195	}
	196	if (offset >= 0x100 && offset < 0x200) {
	197	i = (offset & 0xe0) >> 5;
e69954b9 PB	198	if (i >= s->nchannels)
e69954b9 PB	199	goto bad_offset;
cdbdb648 PB	200	switch (offset >> 2) {
	201	case 0: /* SrcAddr */
	202	return s->chan[i].src;
	203	case 1: /* DestAddr */
	204	return s->chan[i].dest;
	205	case 2: /* LLI */
	206	return s->chan[i].lli;
	207	case 3: /* Control */
	208	return s->chan[i].ctrl;
	209	case 4: /* Configuration */
	210	return s->chan[i].conf;
	211	default:
	212	goto bad_offset;
	213	}
	214	}
	215	switch (offset >> 2) {
	216	case 0: /* IntStatus */
	217	return (s->tc_int & s->tc_mask) \| (s->err_int & s->err_mask);
	218	case 1: /* IntTCStatus */
	219	return (s->tc_int & s->tc_mask);
	220	case 3: /* IntErrorStatus */
	221	return (s->err_int & s->err_mask);
	222	case 5: /* RawIntTCStatus */
	223	return s->tc_int;
	224	case 6: /* RawIntErrorStatus */
	225	return s->err_int;
	226	case 7: /* EnbldChns */
	227	mask = 0;
e69954b9	228	for (i = 0; i < s->nchannels; i++) {
cdbdb648 PB	229	if (s->chan[i].conf & PL080_CCONF_E)
	230	mask \|= 1 << i;
	231	}
	232	return mask;
	233	case 8: /* SoftBReq */
	234	case 9: /* SoftSReq */
	235	case 10: /* SoftLBReq */
	236	case 11: /* SoftLSReq */
	237	/* ??? Implement these. */
	238	return 0;
	239	case 12: /* Configuration */
	240	return s->conf;
	241	case 13: /* Sync */
	242	return s->sync;
	243	default:
	244	bad_offset:
2ac71179	245	hw_error("pl080_read: Bad offset %x\n", (int)offset);
cdbdb648 PB	246	return 0;
	247	}
	248	}
	249
c227f099	250	static void pl080_write(void *opaque, target_phys_addr_t offset,
cdbdb648 PB	251	uint32_t value)
	252	{
	253	pl080_state s = (pl080_state )opaque;
	254	int i;
	255
cdbdb648 PB	256	if (offset >= 0x100 && offset < 0x200) {
cdbdb648 PB	257	i = (offset & 0xe0) >> 5;
e69954b9 PB	258	if (i >= s->nchannels)
e69954b9 PB	259	goto bad_offset;
cdbdb648 PB	260	switch (offset >> 2) {
	261	case 0: /* SrcAddr */
	262	s->chan[i].src = value;
	263	break;
	264	case 1: /* DestAddr */
	265	s->chan[i].dest = value;
	266	break;
	267	case 2: /* LLI */
	268	s->chan[i].lli = value;
	269	break;
	270	case 3: /* Control */
	271	s->chan[i].ctrl = value;
	272	break;
	273	case 4: /* Configuration */
	274	s->chan[i].conf = value;
	275	pl080_run(s);
	276	break;
	277	}
	278	}
	279	switch (offset >> 2) {
	280	case 2: /* IntTCClear */
	281	s->tc_int &= ~value;
	282	break;
	283	case 4: /* IntErrorClear */
	284	s->err_int &= ~value;
	285	break;
	286	case 8: /* SoftBReq */
	287	case 9: /* SoftSReq */
	288	case 10: /* SoftLBReq */
	289	case 11: /* SoftLSReq */
	290	/* ??? Implement these. */
2ac71179	291	hw_error("pl080_write: Soft DMA not implemented\n");
cdbdb648 PB	292	break;
	293	case 12: /* Configuration */
	294	s->conf = value;
	295	if (s->conf & (PL080_CONF_M1 \| PL080_CONF_M1)) {
2ac71179	296	hw_error("pl080_write: Big-endian DMA not implemented\n");
cdbdb648 PB	297	}
	298	pl080_run(s);
	299	break;
	300	case 13: /* Sync */
	301	s->sync = value;
	302	break;
	303	default:
e69954b9	304	bad_offset:
2ac71179	305	hw_error("pl080_write: Bad offset %x\n", (int)offset);
cdbdb648 PB	306	}
	307	pl080_update(s);
	308	}
	309
d60efc6b	310	static CPUReadMemoryFunc * const pl080_readfn[] = {
cdbdb648 PB	311	pl080_read,
	312	pl080_read,
	313	pl080_read
	314	};
	315
d60efc6b	316	static CPUWriteMemoryFunc * const pl080_writefn[] = {
cdbdb648 PB	317	pl080_write,
	318	pl080_write,
	319	pl080_write
	320	};
	321
81a322d4	322	static int pl08x_init(SysBusDevice *dev, int nchannels)
cdbdb648 PB	323	{
cdbdb648 PB	324	int iomemtype;
b4496b13	325	pl080_state *s = FROM_SYSBUS(pl080_state, dev);
cdbdb648	326
1eed09cb	327	iomemtype = cpu_register_io_memory(pl080_readfn,
2507c12a AG	328	pl080_writefn, s,
2507c12a AG	329	DEVICE_NATIVE_ENDIAN);
b4496b13 PB	330	sysbus_init_mmio(dev, 0x1000, iomemtype);
b4496b13 PB	331	sysbus_init_irq(dev, &s->irq);
e69954b9	332	s->nchannels = nchannels;
cdbdb648	333	/* ??? Save/restore. */
81a322d4	334	return 0;
cdbdb648	335	}
b4496b13	336
81a322d4	337	static int pl080_init(SysBusDevice *dev)
b4496b13	338	{
81a322d4	339	return pl08x_init(dev, 8);
b4496b13 PB	340	}
b4496b13 PB	341
81a322d4	342	static int pl081_init(SysBusDevice *dev)
b4496b13	343	{
81a322d4	344	return pl08x_init(dev, 2);
b4496b13 PB	345	}
	346
	347	/* The PL080 and PL081 are the same except for the number of channels
	348	they implement (8 and 2 respectively). */
	349	static void pl080_register_devices(void)
	350	{
	351	sysbus_register_dev("pl080", sizeof(pl080_state), pl080_init);
	352	sysbus_register_dev("pl081", sizeof(pl080_state), pl081_init);
	353	}
	354
	355	device_init(pl080_register_devices)