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5e953812 RK |
1 | /* |
2 | * Definitions for Hyper-V guest/hypervisor interaction | |
3 | * | |
4 | * Copyright (C) 2017 Parallels International GmbH | |
5 | * | |
6 | * This work is licensed under the terms of the GNU GPL, version 2 or later. | |
7 | * See the COPYING file in the top-level directory. | |
8 | */ | |
9 | ||
10 | #ifndef TARGET_I386_HYPERV_PROTO_H | |
11 | #define TARGET_I386_HYPERV_PROTO_H | |
12 | ||
13 | #include "qemu/bitmap.h" | |
14 | ||
15 | #define HV_CPUID_VENDOR_AND_MAX_FUNCTIONS 0x40000000 | |
16 | #define HV_CPUID_INTERFACE 0x40000001 | |
17 | #define HV_CPUID_VERSION 0x40000002 | |
18 | #define HV_CPUID_FEATURES 0x40000003 | |
19 | #define HV_CPUID_ENLIGHTMENT_INFO 0x40000004 | |
20 | #define HV_CPUID_IMPLEMENT_LIMITS 0x40000005 | |
21 | #define HV_CPUID_MIN 0x40000005 | |
22 | #define HV_CPUID_MAX 0x4000ffff | |
23 | #define HV_HYPERVISOR_PRESENT_BIT 0x80000000 | |
24 | ||
25 | /* | |
26 | * HV_CPUID_FEATURES.EAX bits | |
27 | */ | |
28 | #define HV_VP_RUNTIME_AVAILABLE (1u << 0) | |
29 | #define HV_TIME_REF_COUNT_AVAILABLE (1u << 1) | |
30 | #define HV_SYNIC_AVAILABLE (1u << 2) | |
31 | #define HV_SYNTIMERS_AVAILABLE (1u << 3) | |
32 | #define HV_APIC_ACCESS_AVAILABLE (1u << 4) | |
33 | #define HV_HYPERCALL_AVAILABLE (1u << 5) | |
34 | #define HV_VP_INDEX_AVAILABLE (1u << 6) | |
35 | #define HV_RESET_AVAILABLE (1u << 7) | |
36 | #define HV_REFERENCE_TSC_AVAILABLE (1u << 9) | |
37 | #define HV_ACCESS_FREQUENCY_MSRS (1u << 11) | |
ba6a4fd9 | 38 | #define HV_ACCESS_REENLIGHTENMENTS_CONTROL (1u << 13) |
5e953812 RK |
39 | |
40 | /* | |
41 | * HV_CPUID_FEATURES.EDX bits | |
42 | */ | |
43 | #define HV_MWAIT_AVAILABLE (1u << 0) | |
44 | #define HV_GUEST_DEBUGGING_AVAILABLE (1u << 1) | |
45 | #define HV_PERF_MONITOR_AVAILABLE (1u << 2) | |
46 | #define HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE (1u << 3) | |
47 | #define HV_HYPERCALL_PARAMS_XMM_AVAILABLE (1u << 4) | |
48 | #define HV_GUEST_IDLE_STATE_AVAILABLE (1u << 5) | |
49 | #define HV_FREQUENCY_MSRS_AVAILABLE (1u << 8) | |
50 | #define HV_GUEST_CRASH_MSR_AVAILABLE (1u << 10) | |
51 | ||
52 | /* | |
53 | * HV_CPUID_ENLIGHTMENT_INFO.EAX bits | |
54 | */ | |
55 | #define HV_AS_SWITCH_RECOMMENDED (1u << 0) | |
56 | #define HV_LOCAL_TLB_FLUSH_RECOMMENDED (1u << 1) | |
57 | #define HV_REMOTE_TLB_FLUSH_RECOMMENDED (1u << 2) | |
58 | #define HV_APIC_ACCESS_RECOMMENDED (1u << 3) | |
59 | #define HV_SYSTEM_RESET_RECOMMENDED (1u << 4) | |
60 | #define HV_RELAXED_TIMING_RECOMMENDED (1u << 5) | |
6b7a9830 | 61 | #define HV_CLUSTER_IPI_RECOMMENDED (1u << 10) |
47512009 | 62 | #define HV_EX_PROCESSOR_MASKS_RECOMMENDED (1u << 11) |
5e953812 RK |
63 | |
64 | /* | |
65 | * Basic virtualized MSRs | |
66 | */ | |
67 | #define HV_X64_MSR_GUEST_OS_ID 0x40000000 | |
68 | #define HV_X64_MSR_HYPERCALL 0x40000001 | |
69 | #define HV_X64_MSR_VP_INDEX 0x40000002 | |
70 | #define HV_X64_MSR_RESET 0x40000003 | |
71 | #define HV_X64_MSR_VP_RUNTIME 0x40000010 | |
72 | #define HV_X64_MSR_TIME_REF_COUNT 0x40000020 | |
73 | #define HV_X64_MSR_REFERENCE_TSC 0x40000021 | |
74 | #define HV_X64_MSR_TSC_FREQUENCY 0x40000022 | |
75 | #define HV_X64_MSR_APIC_FREQUENCY 0x40000023 | |
76 | ||
77 | /* | |
78 | * Virtual APIC MSRs | |
79 | */ | |
80 | #define HV_X64_MSR_EOI 0x40000070 | |
81 | #define HV_X64_MSR_ICR 0x40000071 | |
82 | #define HV_X64_MSR_TPR 0x40000072 | |
83 | #define HV_X64_MSR_APIC_ASSIST_PAGE 0x40000073 | |
84 | ||
85 | /* | |
86 | * Synthetic interrupt controller MSRs | |
87 | */ | |
88 | #define HV_X64_MSR_SCONTROL 0x40000080 | |
89 | #define HV_X64_MSR_SVERSION 0x40000081 | |
90 | #define HV_X64_MSR_SIEFP 0x40000082 | |
91 | #define HV_X64_MSR_SIMP 0x40000083 | |
92 | #define HV_X64_MSR_EOM 0x40000084 | |
93 | #define HV_X64_MSR_SINT0 0x40000090 | |
94 | #define HV_X64_MSR_SINT1 0x40000091 | |
95 | #define HV_X64_MSR_SINT2 0x40000092 | |
96 | #define HV_X64_MSR_SINT3 0x40000093 | |
97 | #define HV_X64_MSR_SINT4 0x40000094 | |
98 | #define HV_X64_MSR_SINT5 0x40000095 | |
99 | #define HV_X64_MSR_SINT6 0x40000096 | |
100 | #define HV_X64_MSR_SINT7 0x40000097 | |
101 | #define HV_X64_MSR_SINT8 0x40000098 | |
102 | #define HV_X64_MSR_SINT9 0x40000099 | |
103 | #define HV_X64_MSR_SINT10 0x4000009A | |
104 | #define HV_X64_MSR_SINT11 0x4000009B | |
105 | #define HV_X64_MSR_SINT12 0x4000009C | |
106 | #define HV_X64_MSR_SINT13 0x4000009D | |
107 | #define HV_X64_MSR_SINT14 0x4000009E | |
108 | #define HV_X64_MSR_SINT15 0x4000009F | |
109 | ||
110 | /* | |
111 | * Synthetic timer MSRs | |
112 | */ | |
113 | #define HV_X64_MSR_STIMER0_CONFIG 0x400000B0 | |
114 | #define HV_X64_MSR_STIMER0_COUNT 0x400000B1 | |
115 | #define HV_X64_MSR_STIMER1_CONFIG 0x400000B2 | |
116 | #define HV_X64_MSR_STIMER1_COUNT 0x400000B3 | |
117 | #define HV_X64_MSR_STIMER2_CONFIG 0x400000B4 | |
118 | #define HV_X64_MSR_STIMER2_COUNT 0x400000B5 | |
119 | #define HV_X64_MSR_STIMER3_CONFIG 0x400000B6 | |
120 | #define HV_X64_MSR_STIMER3_COUNT 0x400000B7 | |
121 | ||
122 | /* | |
123 | * Guest crash notification MSRs | |
124 | */ | |
125 | #define HV_X64_MSR_CRASH_P0 0x40000100 | |
126 | #define HV_X64_MSR_CRASH_P1 0x40000101 | |
127 | #define HV_X64_MSR_CRASH_P2 0x40000102 | |
128 | #define HV_X64_MSR_CRASH_P3 0x40000103 | |
129 | #define HV_X64_MSR_CRASH_P4 0x40000104 | |
130 | #define HV_CRASH_PARAMS (HV_X64_MSR_CRASH_P4 - HV_X64_MSR_CRASH_P0 + 1) | |
131 | #define HV_X64_MSR_CRASH_CTL 0x40000105 | |
132 | #define HV_CRASH_CTL_NOTIFY (1ull << 63) | |
133 | ||
ba6a4fd9 VK |
134 | /* |
135 | * Reenlightenment notification MSRs | |
136 | */ | |
137 | #define HV_X64_MSR_REENLIGHTENMENT_CONTROL 0x40000106 | |
138 | #define HV_X64_MSR_TSC_EMULATION_CONTROL 0x40000107 | |
139 | #define HV_X64_MSR_TSC_EMULATION_STATUS 0x40000108 | |
140 | ||
5e953812 RK |
141 | /* |
142 | * Hypercall status code | |
143 | */ | |
144 | #define HV_STATUS_SUCCESS 0 | |
145 | #define HV_STATUS_INVALID_HYPERCALL_CODE 2 | |
146 | #define HV_STATUS_INVALID_HYPERCALL_INPUT 3 | |
147 | #define HV_STATUS_INVALID_ALIGNMENT 4 | |
148 | #define HV_STATUS_INVALID_PARAMETER 5 | |
149 | #define HV_STATUS_INSUFFICIENT_MEMORY 11 | |
150 | #define HV_STATUS_INVALID_CONNECTION_ID 18 | |
151 | #define HV_STATUS_INSUFFICIENT_BUFFERS 19 | |
152 | ||
153 | /* | |
154 | * Hypercall numbers | |
155 | */ | |
156 | #define HV_POST_MESSAGE 0x005c | |
157 | #define HV_SIGNAL_EVENT 0x005d | |
158 | #define HV_HYPERCALL_FAST (1u << 16) | |
159 | ||
160 | /* | |
161 | * Hypercall MSR bits | |
162 | */ | |
163 | #define HV_HYPERCALL_ENABLE (1u << 0) | |
164 | ||
165 | /* | |
166 | * Synthetic interrupt controller definitions | |
167 | */ | |
168 | #define HV_SYNIC_VERSION 1 | |
169 | #define HV_SINT_COUNT 16 | |
170 | #define HV_SYNIC_ENABLE (1u << 0) | |
171 | #define HV_SIMP_ENABLE (1u << 0) | |
172 | #define HV_SIEFP_ENABLE (1u << 0) | |
173 | #define HV_SINT_MASKED (1u << 16) | |
174 | #define HV_SINT_AUTO_EOI (1u << 17) | |
175 | #define HV_SINT_VECTOR_MASK 0xff | |
176 | ||
177 | #define HV_STIMER_COUNT 4 | |
178 | ||
179 | /* | |
180 | * Message size | |
181 | */ | |
182 | #define HV_MESSAGE_PAYLOAD_SIZE 240 | |
183 | ||
184 | /* | |
185 | * Message types | |
186 | */ | |
187 | #define HV_MESSAGE_NONE 0x00000000 | |
188 | #define HV_MESSAGE_VMBUS 0x00000001 | |
189 | #define HV_MESSAGE_UNMAPPED_GPA 0x80000000 | |
190 | #define HV_MESSAGE_GPA_INTERCEPT 0x80000001 | |
191 | #define HV_MESSAGE_TIMER_EXPIRED 0x80000010 | |
192 | #define HV_MESSAGE_INVALID_VP_REGISTER_VALUE 0x80000020 | |
193 | #define HV_MESSAGE_UNRECOVERABLE_EXCEPTION 0x80000021 | |
194 | #define HV_MESSAGE_UNSUPPORTED_FEATURE 0x80000022 | |
195 | #define HV_MESSAGE_EVENTLOG_BUFFERCOMPLETE 0x80000040 | |
196 | #define HV_MESSAGE_X64_IOPORT_INTERCEPT 0x80010000 | |
197 | #define HV_MESSAGE_X64_MSR_INTERCEPT 0x80010001 | |
198 | #define HV_MESSAGE_X64_CPUID_INTERCEPT 0x80010002 | |
199 | #define HV_MESSAGE_X64_EXCEPTION_INTERCEPT 0x80010003 | |
200 | #define HV_MESSAGE_X64_APIC_EOI 0x80010004 | |
201 | #define HV_MESSAGE_X64_LEGACY_FP_ERROR 0x80010005 | |
202 | ||
203 | /* | |
204 | * Message flags | |
205 | */ | |
206 | #define HV_MESSAGE_FLAG_PENDING 0x1 | |
207 | ||
208 | /* | |
209 | * Event flags number per SINT | |
210 | */ | |
211 | #define HV_EVENT_FLAGS_COUNT (256 * 8) | |
212 | ||
213 | /* | |
214 | * Connection id valid bits | |
215 | */ | |
216 | #define HV_CONNECTION_ID_MASK 0x00ffffff | |
217 | ||
218 | /* | |
219 | * Input structure for POST_MESSAGE hypercall | |
220 | */ | |
221 | struct hyperv_post_message_input { | |
222 | uint32_t connection_id; | |
223 | uint32_t _reserved; | |
224 | uint32_t message_type; | |
225 | uint32_t payload_size; | |
226 | uint8_t payload[HV_MESSAGE_PAYLOAD_SIZE]; | |
227 | }; | |
228 | ||
229 | /* | |
230 | * Input structure for SIGNAL_EVENT hypercall | |
231 | */ | |
232 | struct hyperv_signal_event_input { | |
233 | uint32_t connection_id; | |
234 | uint16_t flag_number; | |
235 | uint16_t _reserved_zero; | |
236 | }; | |
237 | ||
238 | /* | |
239 | * SynIC message structures | |
240 | */ | |
241 | struct hyperv_message_header { | |
242 | uint32_t message_type; | |
243 | uint8_t payload_size; | |
244 | uint8_t message_flags; /* HV_MESSAGE_FLAG_XX */ | |
245 | uint8_t _reserved[2]; | |
246 | uint64_t sender; | |
247 | }; | |
248 | ||
249 | struct hyperv_message { | |
250 | struct hyperv_message_header header; | |
251 | uint8_t payload[HV_MESSAGE_PAYLOAD_SIZE]; | |
252 | }; | |
253 | ||
254 | struct hyperv_message_page { | |
255 | struct hyperv_message slot[HV_SINT_COUNT]; | |
256 | }; | |
257 | ||
258 | /* | |
259 | * SynIC event flags structures | |
260 | */ | |
261 | struct hyperv_event_flags { | |
262 | DECLARE_BITMAP(flags, HV_EVENT_FLAGS_COUNT); | |
263 | }; | |
264 | ||
265 | struct hyperv_event_flags_page { | |
266 | struct hyperv_event_flags slot[HV_SINT_COUNT]; | |
267 | }; | |
268 | ||
269 | #endif |