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QMP: Fix asynchronous events delivery
[qemu.git] / hw / rtl8139.c
CommitLineData
a41b2ff2
PB		 1/**
2 * QEMU RTL8139 emulation
5fafdf24 3 *
a41b2ff2 4 * Copyright (c) 2006 Igor Kovalenko
5fafdf24 5 *
a41b2ff2
PB		 6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
5fafdf24 23
a41b2ff2
PB		 24 * Modifications:
25 * 2006-Jan-28 Mark Malakanov : TSAD and CSCR implementation (for Windows driver)
5fafdf24 26 *
6cadb320
FB		 27 * 2006-Apr-28 Juergen Lock : EEPROM emulation changes for FreeBSD driver
28 * HW revision ID changes for FreeBSD driver
5fafdf24 29 *
6cadb320
FB		 30 * 2006-Jul-01 Igor Kovalenko : Implemented loopback mode for FreeBSD driver
31 * Corrected packet transfer reassembly routine for 8139C+ mode
32 * Rearranged debugging print statements
33 * Implemented PCI timer interrupt (disabled by default)
34 * Implemented Tally Counters, increased VM load/save version
35 * Implemented IP/TCP/UDP checksum task offloading
718da2b9
FB		 36 *
37 * 2006-Jul-04 Igor Kovalenko : Implemented TCP segmentation offloading
38 * Fixed MTU=1500 for produced ethernet frames
39 *
40 * 2006-Jul-09 Igor Kovalenko : Fixed TCP header length calculation while processing
41 * segmentation offloading
42 * Removed slirp.h dependency
43 * Added rx/tx buffer reset when enabling rx/tx operation
a41b2ff2
PB		 44 */
45
87ecb68b
PB		 46#include "hw.h"
47#include "pci.h"
48#include "qemu-timer.h"
49#include "net.h"
254111ec 50#include "loader.h"
a41b2ff2 51
a41b2ff2
PB		 52/* debug RTL8139 card */
53//#define DEBUG_RTL8139 1
54
6cadb320
FB		 55#define PCI_FREQUENCY 33000000L
56
a41b2ff2
PB		 57/* debug RTL8139 card C+ mode only */
58//#define DEBUG_RTL8139CP 1
59
ccf1d14a
TS		 60/* Calculate CRCs properly on Rx packets */
61#define RTL8139_CALCULATE_RXCRC 1
a41b2ff2 62
6cadb320
FB		 63/* Uncomment to enable on-board timer interrupts */
64//#define RTL8139_ONBOARD_TIMER 1
a41b2ff2
PB		 65
66#if defined(RTL8139_CALCULATE_RXCRC)
67/* For crc32 */
68#include <zlib.h>
69#endif
70
71#define SET_MASKED(input, mask, curr) \
72 ( ( (input) & ~(mask) ) | ( (curr) & (mask) ) )
73
74/* arg % size for size which is a power of 2 */
75#define MOD2(input, size) \
76 ( ( input ) & ( size - 1 ) )
77
6cadb320
FB		 78#if defined (DEBUG_RTL8139)
79# define DEBUG_PRINT(x) do { printf x ; } while (0)
80#else
81# define DEBUG_PRINT(x)
82#endif
83
a41b2ff2
PB		 84/* Symbolic offsets to registers. */
85enum RTL8139_registers {
86 MAC0 = 0, /* Ethernet hardware address. */
87 MAR0 = 8, /* Multicast filter. */
6cadb320
FB		 88 TxStatus0 = 0x10,/* Transmit status (Four 32bit registers). C mode only */
89 /* Dump Tally Conter control register(64bit). C+ mode only */
90 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
a41b2ff2
PB		 91 RxBuf = 0x30,
92 ChipCmd = 0x37,
93 RxBufPtr = 0x38,
94 RxBufAddr = 0x3A,
95 IntrMask = 0x3C,
96 IntrStatus = 0x3E,
97 TxConfig = 0x40,
98 RxConfig = 0x44,
99 Timer = 0x48, /* A general-purpose counter. */
100 RxMissed = 0x4C, /* 24 bits valid, write clears. */
101 Cfg9346 = 0x50,
102 Config0 = 0x51,
103 Config1 = 0x52,
104 FlashReg = 0x54,
105 MediaStatus = 0x58,
106 Config3 = 0x59,
107 Config4 = 0x5A, /* absent on RTL-8139A */
108 HltClk = 0x5B,
109 MultiIntr = 0x5C,
110 PCIRevisionID = 0x5E,
111 TxSummary = 0x60, /* TSAD register. Transmit Status of All Descriptors*/
112 BasicModeCtrl = 0x62,
113 BasicModeStatus = 0x64,
114 NWayAdvert = 0x66,
115 NWayLPAR = 0x68,
116 NWayExpansion = 0x6A,
117 /* Undocumented registers, but required for proper operation. */
118 FIFOTMS = 0x70, /* FIFO Control and test. */
119 CSCR = 0x74, /* Chip Status and Configuration Register. */
120 PARA78 = 0x78,
121 PARA7c = 0x7c, /* Magic transceiver parameter register. */
122 Config5 = 0xD8, /* absent on RTL-8139A */
123 /* C+ mode */
124 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
125 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
126 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
127 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
128 RxRingAddrLO = 0xE4, /* 64-bit start addr of Rx ring */
129 RxRingAddrHI = 0xE8, /* 64-bit start addr of Rx ring */
130 TxThresh = 0xEC, /* Early Tx threshold */
131};
132
133enum ClearBitMasks {
134 MultiIntrClear = 0xF000,
135 ChipCmdClear = 0xE2,
136 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
137};
138
139enum ChipCmdBits {
140 CmdReset = 0x10,
141 CmdRxEnb = 0x08,
142 CmdTxEnb = 0x04,
143 RxBufEmpty = 0x01,
144};
145
146/* C+ mode */
147enum CplusCmdBits {
6cadb320
FB		 148 CPlusRxVLAN = 0x0040, /* enable receive VLAN detagging */
149 CPlusRxChkSum = 0x0020, /* enable receive checksum offloading */
150 CPlusRxEnb = 0x0002,
151 CPlusTxEnb = 0x0001,
a41b2ff2
PB		 152};
153
154/* Interrupt register bits, using my own meaningful names. */
155enum IntrStatusBits {
156 PCIErr = 0x8000,
157 PCSTimeout = 0x4000,
158 RxFIFOOver = 0x40,
159 RxUnderrun = 0x20,
160 RxOverflow = 0x10,
161 TxErr = 0x08,
162 TxOK = 0x04,
163 RxErr = 0x02,
164 RxOK = 0x01,
165
166 RxAckBits = RxFIFOOver | RxOverflow | RxOK,
167};
168
169enum TxStatusBits {
170 TxHostOwns = 0x2000,
171 TxUnderrun = 0x4000,
172 TxStatOK = 0x8000,
173 TxOutOfWindow = 0x20000000,
174 TxAborted = 0x40000000,
175 TxCarrierLost = 0x80000000,
176};
177enum RxStatusBits {
178 RxMulticast = 0x8000,
179 RxPhysical = 0x4000,
180 RxBroadcast = 0x2000,
181 RxBadSymbol = 0x0020,
182 RxRunt = 0x0010,
183 RxTooLong = 0x0008,
184 RxCRCErr = 0x0004,
185 RxBadAlign = 0x0002,
186 RxStatusOK = 0x0001,
187};
188
189/* Bits in RxConfig. */
190enum rx_mode_bits {
191 AcceptErr = 0x20,
192 AcceptRunt = 0x10,
193 AcceptBroadcast = 0x08,
194 AcceptMulticast = 0x04,
195 AcceptMyPhys = 0x02,
196 AcceptAllPhys = 0x01,
197};
198
199/* Bits in TxConfig. */
200enum tx_config_bits {
201
202 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
203 TxIFGShift = 24,
204 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
205 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */
206 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */
207 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
208
209 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
210 TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */
211 TxClearAbt = (1 << 0), /* Clear abort (WO) */
212 TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */
213 TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */
214
215 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
216};
217
218
219/* Transmit Status of All Descriptors (TSAD) Register */
220enum TSAD_bits {
221 TSAD_TOK3 = 1<<15, // TOK bit of Descriptor 3
222 TSAD_TOK2 = 1<<14, // TOK bit of Descriptor 2
223 TSAD_TOK1 = 1<<13, // TOK bit of Descriptor 1
224 TSAD_TOK0 = 1<<12, // TOK bit of Descriptor 0
225 TSAD_TUN3 = 1<<11, // TUN bit of Descriptor 3
226 TSAD_TUN2 = 1<<10, // TUN bit of Descriptor 2
227 TSAD_TUN1 = 1<<9, // TUN bit of Descriptor 1
228 TSAD_TUN0 = 1<<8, // TUN bit of Descriptor 0
229 TSAD_TABT3 = 1<<07, // TABT bit of Descriptor 3
230 TSAD_TABT2 = 1<<06, // TABT bit of Descriptor 2
231 TSAD_TABT1 = 1<<05, // TABT bit of Descriptor 1
232 TSAD_TABT0 = 1<<04, // TABT bit of Descriptor 0
233 TSAD_OWN3 = 1<<03, // OWN bit of Descriptor 3
234 TSAD_OWN2 = 1<<02, // OWN bit of Descriptor 2
235 TSAD_OWN1 = 1<<01, // OWN bit of Descriptor 1
236 TSAD_OWN0 = 1<<00, // OWN bit of Descriptor 0
237};
238
239
240/* Bits in Config1 */
241enum Config1Bits {
242 Cfg1_PM_Enable = 0x01,
243 Cfg1_VPD_Enable = 0x02,
244 Cfg1_PIO = 0x04,
245 Cfg1_MMIO = 0x08,
246 LWAKE = 0x10, /* not on 8139, 8139A */
247 Cfg1_Driver_Load = 0x20,
248 Cfg1_LED0 = 0x40,
249 Cfg1_LED1 = 0x80,
250 SLEEP = (1 << 1), /* only on 8139, 8139A */
251 PWRDN = (1 << 0), /* only on 8139, 8139A */
252};
253
254/* Bits in Config3 */
255enum Config3Bits {
256 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
257 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
258 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
259 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
260 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
261 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
262 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
263 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
264};
265
266/* Bits in Config4 */
267enum Config4Bits {
268 LWPTN = (1 << 2), /* not on 8139, 8139A */
269};
270
271/* Bits in Config5 */
272enum Config5Bits {
273 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
274 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
275 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
276 Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */
277 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
278 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
279 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
280};
281
282enum RxConfigBits {
283 /* rx fifo threshold */
284 RxCfgFIFOShift = 13,
285 RxCfgFIFONone = (7 << RxCfgFIFOShift),
286
287 /* Max DMA burst */
288 RxCfgDMAShift = 8,
289 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
290
291 /* rx ring buffer length */
292 RxCfgRcv8K = 0,
293 RxCfgRcv16K = (1 << 11),
294 RxCfgRcv32K = (1 << 12),
295 RxCfgRcv64K = (1 << 11) | (1 << 12),
296
297 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
298 RxNoWrap = (1 << 7),
299};
300
301/* Twister tuning parameters from RealTek.
302 Completely undocumented, but required to tune bad links on some boards. */
303/*
304enum CSCRBits {
305 CSCR_LinkOKBit = 0x0400,
306 CSCR_LinkChangeBit = 0x0800,
307 CSCR_LinkStatusBits = 0x0f000,
308 CSCR_LinkDownOffCmd = 0x003c0,
309 CSCR_LinkDownCmd = 0x0f3c0,
310*/
311enum CSCRBits {
5fafdf24 312 CSCR_Testfun = 1<<15, /* 1 = Auto-neg speeds up internal timer, WO, def 0 */
a41b2ff2
PB		 313 CSCR_LD = 1<<9, /* Active low TPI link disable signal. When low, TPI still transmits link pulses and TPI stays in good link state. def 1*/
314 CSCR_HEART_BIT = 1<<8, /* 1 = HEART BEAT enable, 0 = HEART BEAT disable. HEART BEAT function is only valid in 10Mbps mode. def 1*/
315 CSCR_JBEN = 1<<7, /* 1 = enable jabber function. 0 = disable jabber function, def 1*/
5fafdf24 316 CSCR_F_LINK_100 = 1<<6, /* Used to login force good link in 100Mbps for diagnostic purposes. 1 = DISABLE, 0 = ENABLE. def 1*/
a41b2ff2
PB		 317 CSCR_F_Connect = 1<<5, /* Assertion of this bit forces the disconnect function to be bypassed. def 0*/
318 CSCR_Con_status = 1<<3, /* This bit indicates the status of the connection. 1 = valid connected link detected; 0 = disconnected link detected. RO def 0*/
319 CSCR_Con_status_En = 1<<2, /* Assertion of this bit configures LED1 pin to indicate connection status. def 0*/
320 CSCR_PASS_SCR = 1<<0, /* Bypass Scramble, def 0*/
321};
322
323enum Cfg9346Bits {
324 Cfg9346_Lock = 0x00,
325 Cfg9346_Unlock = 0xC0,
326};
327
328typedef enum {
329 CH_8139 = 0,
330 CH_8139_K,
331 CH_8139A,
332 CH_8139A_G,
333 CH_8139B,
334 CH_8130,
335 CH_8139C,
336 CH_8100,
337 CH_8100B_8139D,
338 CH_8101,
c227f099 339} chip_t;
a41b2ff2
PB		 340
341enum chip_flags {
342 HasHltClk = (1 << 0),
343 HasLWake = (1 << 1),
344};
345
346#define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
347 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
348#define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
349
6cadb320
FB		 350#define RTL8139_PCI_REVID_8139 0x10
351#define RTL8139_PCI_REVID_8139CPLUS 0x20
352
353#define RTL8139_PCI_REVID RTL8139_PCI_REVID_8139CPLUS
354
a41b2ff2
PB		 355/* Size is 64 * 16bit words */
356#define EEPROM_9346_ADDR_BITS 6
357#define EEPROM_9346_SIZE (1 << EEPROM_9346_ADDR_BITS)
358#define EEPROM_9346_ADDR_MASK (EEPROM_9346_SIZE - 1)
359
360enum Chip9346Operation
361{
362 Chip9346_op_mask = 0xc0, /* 10 zzzzzz */
363 Chip9346_op_read = 0x80, /* 10 AAAAAA */
364 Chip9346_op_write = 0x40, /* 01 AAAAAA D(15)..D(0) */
365 Chip9346_op_ext_mask = 0xf0, /* 11 zzzzzz */
366 Chip9346_op_write_enable = 0x30, /* 00 11zzzz */
367 Chip9346_op_write_all = 0x10, /* 00 01zzzz */
368 Chip9346_op_write_disable = 0x00, /* 00 00zzzz */
369};
370
371enum Chip9346Mode
372{
373 Chip9346_none = 0,
374 Chip9346_enter_command_mode,
375 Chip9346_read_command,
376 Chip9346_data_read, /* from output register */
377 Chip9346_data_write, /* to input register, then to contents at specified address */
378 Chip9346_data_write_all, /* to input register, then filling contents */
379};
380
381typedef struct EEprom9346
382{
383 uint16_t contents[EEPROM_9346_SIZE];
384 int mode;
385 uint32_t tick;
386 uint8_t address;
387 uint16_t input;
388 uint16_t output;
389
390 uint8_t eecs;
391 uint8_t eesk;
392 uint8_t eedi;
393 uint8_t eedo;
394} EEprom9346;
395
6cadb320
FB		 396typedef struct RTL8139TallyCounters
397{
398 /* Tally counters */
399 uint64_t TxOk;
400 uint64_t RxOk;
401 uint64_t TxERR;
402 uint32_t RxERR;
403 uint16_t MissPkt;
404 uint16_t FAE;
405 uint32_t Tx1Col;
406 uint32_t TxMCol;
407 uint64_t RxOkPhy;
408 uint64_t RxOkBrd;
409 uint32_t RxOkMul;
410 uint16_t TxAbt;
411 uint16_t TxUndrn;
412} RTL8139TallyCounters;
413
414/* Clears all tally counters */
415static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters);
416
417/* Writes tally counters to specified physical memory address */
c227f099 418static void RTL8139TallyCounters_physical_memory_write(target_phys_addr_t tc_addr, RTL8139TallyCounters* counters);
6cadb320 419
a41b2ff2 420typedef struct RTL8139State {
efd6dd45 421 PCIDevice dev;
a41b2ff2
PB		 422 uint8_t phys[8]; /* mac address */
423 uint8_t mult[8]; /* multicast mask array */
424
6cadb320 425 uint32_t TxStatus[4]; /* TxStatus0 in C mode*/ /* also DTCCR[0] and DTCCR[1] in C+ mode */
a41b2ff2
PB		 426 uint32_t TxAddr[4]; /* TxAddr0 */
427 uint32_t RxBuf; /* Receive buffer */
428 uint32_t RxBufferSize;/* internal variable, receive ring buffer size in C mode */
429 uint32_t RxBufPtr;
430 uint32_t RxBufAddr;
431
432 uint16_t IntrStatus;
433 uint16_t IntrMask;
434
435 uint32_t TxConfig;
436 uint32_t RxConfig;
437 uint32_t RxMissed;
438
439 uint16_t CSCR;
440
441 uint8_t Cfg9346;
442 uint8_t Config0;
443 uint8_t Config1;
444 uint8_t Config3;
445 uint8_t Config4;
446 uint8_t Config5;
447
448 uint8_t clock_enabled;
449 uint8_t bChipCmdState;
450
451 uint16_t MultiIntr;
452
453 uint16_t BasicModeCtrl;
454 uint16_t BasicModeStatus;
455 uint16_t NWayAdvert;
456 uint16_t NWayLPAR;
457 uint16_t NWayExpansion;
458
459 uint16_t CpCmd;
460 uint8_t TxThresh;
461
1673ad51 462 NICState *nic;
254111ec 463 NICConf conf;
a41b2ff2
PB		 464 int rtl8139_mmio_io_addr;
465
466 /* C ring mode */
467 uint32_t currTxDesc;
468
469 /* C+ mode */
2c3891ab
AL		 470 uint32_t cplus_enabled;
471
a41b2ff2
PB		 472 uint32_t currCPlusRxDesc;
473 uint32_t currCPlusTxDesc;
474
475 uint32_t RxRingAddrLO;
476 uint32_t RxRingAddrHI;
477
478 EEprom9346 eeprom;
6cadb320
FB		 479
480 uint32_t TCTR;
481 uint32_t TimerInt;
482 int64_t TCTR_base;
483
484 /* Tally counters */
485 RTL8139TallyCounters tally_counters;
486
487 /* Non-persistent data */
488 uint8_t *cplus_txbuffer;
489 int cplus_txbuffer_len;
490 int cplus_txbuffer_offset;
491
492 /* PCI interrupt timer */
493 QEMUTimer *timer;
494
a41b2ff2
PB		 495} RTL8139State;
496
9596ebb7 497static void prom9346_decode_command(EEprom9346 *eeprom, uint8_t command)
a41b2ff2 498{
6cadb320 499 DEBUG_PRINT(("RTL8139: eeprom command 0x%02x\n", command));
a41b2ff2
PB		 500
501 switch (command & Chip9346_op_mask)
502 {
503 case Chip9346_op_read:
504 {
505 eeprom->address = command & EEPROM_9346_ADDR_MASK;
506 eeprom->output = eeprom->contents[eeprom->address];
507 eeprom->eedo = 0;
508 eeprom->tick = 0;
509 eeprom->mode = Chip9346_data_read;
6cadb320
FB		 510 DEBUG_PRINT(("RTL8139: eeprom read from address 0x%02x data=0x%04x\n",
511 eeprom->address, eeprom->output));
a41b2ff2
PB		 512 }
513 break;
514
515 case Chip9346_op_write:
516 {
517 eeprom->address = command & EEPROM_9346_ADDR_MASK;
518 eeprom->input = 0;
519 eeprom->tick = 0;
520 eeprom->mode = Chip9346_none; /* Chip9346_data_write */
6cadb320
FB		 521 DEBUG_PRINT(("RTL8139: eeprom begin write to address 0x%02x\n",
522 eeprom->address));
a41b2ff2
PB		 523 }
524 break;
525 default:
526 eeprom->mode = Chip9346_none;
527 switch (command & Chip9346_op_ext_mask)
528 {
529 case Chip9346_op_write_enable:
6cadb320 530 DEBUG_PRINT(("RTL8139: eeprom write enabled\n"));
a41b2ff2
PB		 531 break;
532 case Chip9346_op_write_all:
6cadb320 533 DEBUG_PRINT(("RTL8139: eeprom begin write all\n"));
a41b2ff2
PB		 534 break;
535 case Chip9346_op_write_disable:
6cadb320 536 DEBUG_PRINT(("RTL8139: eeprom write disabled\n"));
a41b2ff2
PB		 537 break;
538 }
539 break;
540 }
541}
542
9596ebb7 543static void prom9346_shift_clock(EEprom9346 *eeprom)
a41b2ff2
PB		 544{
545 int bit = eeprom->eedi?1:0;
546
547 ++ eeprom->tick;
548
6cadb320 549 DEBUG_PRINT(("eeprom: tick %d eedi=%d eedo=%d\n", eeprom->tick, eeprom->eedi, eeprom->eedo));
a41b2ff2
PB		 550
551 switch (eeprom->mode)
552 {
553 case Chip9346_enter_command_mode:
554 if (bit)
555 {
556 eeprom->mode = Chip9346_read_command;
557 eeprom->tick = 0;
558 eeprom->input = 0;
6cadb320 559 DEBUG_PRINT(("eeprom: +++ synchronized, begin command read\n"));
a41b2ff2
PB		 560 }
561 break;
562
563 case Chip9346_read_command:
564 eeprom->input = (eeprom->input << 1) | (bit & 1);
565 if (eeprom->tick == 8)
566 {
567 prom9346_decode_command(eeprom, eeprom->input & 0xff);
568 }
569 break;
570
571 case Chip9346_data_read:
572 eeprom->eedo = (eeprom->output & 0x8000)?1:0;
573 eeprom->output <<= 1;
574 if (eeprom->tick == 16)
575 {
6cadb320
FB		 576#if 1
577 // the FreeBSD drivers (rl and re) don't explicitly toggle
578 // CS between reads (or does setting Cfg9346 to 0 count too?),
579 // so we need to enter wait-for-command state here
580 eeprom->mode = Chip9346_enter_command_mode;
581 eeprom->input = 0;
582 eeprom->tick = 0;
583
584 DEBUG_PRINT(("eeprom: +++ end of read, awaiting next command\n"));
585#else
586 // original behaviour
a41b2ff2
PB		 587 ++eeprom->address;
588 eeprom->address &= EEPROM_9346_ADDR_MASK;
589 eeprom->output = eeprom->contents[eeprom->address];
590 eeprom->tick = 0;
591
6cadb320
FB		 592 DEBUG_PRINT(("eeprom: +++ read next address 0x%02x data=0x%04x\n",
593 eeprom->address, eeprom->output));
a41b2ff2
PB		 594#endif
595 }
596 break;
597
598 case Chip9346_data_write:
599 eeprom->input = (eeprom->input << 1) | (bit & 1);
600 if (eeprom->tick == 16)
601 {
6cadb320
FB		 602 DEBUG_PRINT(("RTL8139: eeprom write to address 0x%02x data=0x%04x\n",
603 eeprom->address, eeprom->input));
604
a41b2ff2
PB		 605 eeprom->contents[eeprom->address] = eeprom->input;
606 eeprom->mode = Chip9346_none; /* waiting for next command after CS cycle */
607 eeprom->tick = 0;
608 eeprom->input = 0;
609 }
610 break;
611
612 case Chip9346_data_write_all:
613 eeprom->input = (eeprom->input << 1) | (bit & 1);
614 if (eeprom->tick == 16)
615 {
616 int i;
617 for (i = 0; i < EEPROM_9346_SIZE; i++)
618 {
619 eeprom->contents[i] = eeprom->input;
620 }
6cadb320
FB		 621 DEBUG_PRINT(("RTL8139: eeprom filled with data=0x%04x\n",
622 eeprom->input));
623
a41b2ff2
PB		 624 eeprom->mode = Chip9346_enter_command_mode;
625 eeprom->tick = 0;
626 eeprom->input = 0;
627 }
628 break;
629
630 default:
631 break;
632 }
633}
634
9596ebb7 635static int prom9346_get_wire(RTL8139State *s)
a41b2ff2
PB		 636{
637 EEprom9346 *eeprom = &s->eeprom;
638 if (!eeprom->eecs)
639 return 0;
640
641 return eeprom->eedo;
642}
643
9596ebb7
PB		 644/* FIXME: This should be merged into/replaced by eeprom93xx.c. */
645static void prom9346_set_wire(RTL8139State *s, int eecs, int eesk, int eedi)
a41b2ff2
PB		 646{
647 EEprom9346 *eeprom = &s->eeprom;
648 uint8_t old_eecs = eeprom->eecs;
649 uint8_t old_eesk = eeprom->eesk;
650
651 eeprom->eecs = eecs;
652 eeprom->eesk = eesk;
653 eeprom->eedi = eedi;
654
6cadb320
FB		 655 DEBUG_PRINT(("eeprom: +++ wires CS=%d SK=%d DI=%d DO=%d\n",
656 eeprom->eecs, eeprom->eesk, eeprom->eedi, eeprom->eedo));
a41b2ff2
PB		 657
658 if (!old_eecs && eecs)
659 {
660 /* Synchronize start */
661 eeprom->tick = 0;
662 eeprom->input = 0;
663 eeprom->output = 0;
664 eeprom->mode = Chip9346_enter_command_mode;
665
6cadb320 666 DEBUG_PRINT(("=== eeprom: begin access, enter command mode\n"));
a41b2ff2
PB		 667 }
668
669 if (!eecs)
670 {
6cadb320 671 DEBUG_PRINT(("=== eeprom: end access\n"));
a41b2ff2
PB		 672 return;
673 }
674
675 if (!old_eesk && eesk)
676 {
677 /* SK front rules */
678 prom9346_shift_clock(eeprom);
679 }
680}
681
682static void rtl8139_update_irq(RTL8139State *s)
683{
684 int isr;
685 isr = (s->IntrStatus & s->IntrMask) & 0xffff;
6cadb320 686
80a34d67
PB		 687 DEBUG_PRINT(("RTL8139: Set IRQ to %d (%04x %04x)\n",
688 isr ? 1 : 0, s->IntrStatus, s->IntrMask));
6cadb320 689
efd6dd45 690 qemu_set_irq(s->dev.irq[0], (isr != 0));
a41b2ff2
PB		 691}
692
693#define POLYNOMIAL 0x04c11db6
694
695/* From FreeBSD */
696/* XXX: optimize */
697static int compute_mcast_idx(const uint8_t *ep)
698{
699 uint32_t crc;
700 int carry, i, j;
701 uint8_t b;
702
703 crc = 0xffffffff;
704 for (i = 0; i < 6; i++) {
705 b = *ep++;
706 for (j = 0; j < 8; j++) {
707 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
708 crc <<= 1;
709 b >>= 1;
710 if (carry)
711 crc = ((crc ^ POLYNOMIAL) | carry);
712 }
713 }
714 return (crc >> 26);
715}
716
717static int rtl8139_RxWrap(RTL8139State *s)
718{
719 /* wrapping enabled; assume 1.5k more buffer space if size < 65536 */
720 return (s->RxConfig & (1 << 7));
721}
722
723static int rtl8139_receiver_enabled(RTL8139State *s)
724{
725 return s->bChipCmdState & CmdRxEnb;
726}
727
728static int rtl8139_transmitter_enabled(RTL8139State *s)
729{
730 return s->bChipCmdState & CmdTxEnb;
731}
732
733static int rtl8139_cp_receiver_enabled(RTL8139State *s)
734{
735 return s->CpCmd & CPlusRxEnb;
736}
737
738static int rtl8139_cp_transmitter_enabled(RTL8139State *s)
739{
740 return s->CpCmd & CPlusTxEnb;
741}
742
743static void rtl8139_write_buffer(RTL8139State *s, const void *buf, int size)
744{
745 if (s->RxBufAddr + size > s->RxBufferSize)
746 {
747 int wrapped = MOD2(s->RxBufAddr + size, s->RxBufferSize);
748
749 /* write packet data */
ccf1d14a 750 if (wrapped && !(s->RxBufferSize < 65536 && rtl8139_RxWrap(s)))
a41b2ff2 751 {
6cadb320 752 DEBUG_PRINT((">>> RTL8139: rx packet wrapped in buffer at %d\n", size-wrapped));
a41b2ff2
PB		 753
754 if (size > wrapped)
755 {
756 cpu_physical_memory_write( s->RxBuf + s->RxBufAddr,
757 buf, size-wrapped );
758 }
759
760 /* reset buffer pointer */
761 s->RxBufAddr = 0;
762
763 cpu_physical_memory_write( s->RxBuf + s->RxBufAddr,
764 buf + (size-wrapped), wrapped );
765
766 s->RxBufAddr = wrapped;
767
768 return;
769 }
770 }
771
772 /* non-wrapping path or overwrapping enabled */
773 cpu_physical_memory_write( s->RxBuf + s->RxBufAddr, buf, size );
774
775 s->RxBufAddr += size;
776}
777
778#define MIN_BUF_SIZE 60
c227f099 779static inline target_phys_addr_t rtl8139_addr64(uint32_t low, uint32_t high)
a41b2ff2
PB		 780{
781#if TARGET_PHYS_ADDR_BITS > 32
c227f099 782 return low | ((target_phys_addr_t)high << 32);
a41b2ff2
PB		 783#else
784 return low;
785#endif
786}
787
1673ad51 788static int rtl8139_can_receive(VLANClientState *nc)
a41b2ff2 789{
1673ad51 790 RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque;
a41b2ff2
PB		 791 int avail;
792
aa1f17c1 793 /* Receive (drop) packets if card is disabled. */
a41b2ff2
PB		 794 if (!s->clock_enabled)
795 return 1;
796 if (!rtl8139_receiver_enabled(s))
797 return 1;
798
799 if (rtl8139_cp_receiver_enabled(s)) {
800 /* ??? Flow control not implemented in c+ mode.
801 This is a hack to work around slirp deficiencies anyway. */
802 return 1;
803 } else {
804 avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr,
805 s->RxBufferSize);
806 return (avail == 0 || avail >= 1514);
807 }
808}
809
1673ad51 810static ssize_t rtl8139_do_receive(VLANClientState *nc, const uint8_t *buf, size_t size_, int do_interrupt)
a41b2ff2 811{
1673ad51 812 RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque;
4f1c942b 813 int size = size_;
a41b2ff2
PB		 814
815 uint32_t packet_header = 0;
816
817 uint8_t buf1[60];
5fafdf24 818 static const uint8_t broadcast_macaddr[6] =
a41b2ff2
PB		 819 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
820
6cadb320 821 DEBUG_PRINT((">>> RTL8139: received len=%d\n", size));
a41b2ff2
PB		 822
823 /* test if board clock is stopped */
824 if (!s->clock_enabled)
825 {
6cadb320 826 DEBUG_PRINT(("RTL8139: stopped ==========================\n"));
4f1c942b 827 return -1;
a41b2ff2
PB		 828 }
829
830 /* first check if receiver is enabled */
831
832 if (!rtl8139_receiver_enabled(s))
833 {
6cadb320 834 DEBUG_PRINT(("RTL8139: receiver disabled ================\n"));
4f1c942b 835 return -1;
a41b2ff2
PB		 836 }
837
838 /* XXX: check this */
839 if (s->RxConfig & AcceptAllPhys) {
840 /* promiscuous: receive all */
6cadb320 841 DEBUG_PRINT((">>> RTL8139: packet received in promiscuous mode\n"));
a41b2ff2
PB		 842
843 } else {
844 if (!memcmp(buf, broadcast_macaddr, 6)) {
845 /* broadcast address */
846 if (!(s->RxConfig & AcceptBroadcast))
847 {
6cadb320
FB		 848 DEBUG_PRINT((">>> RTL8139: broadcast packet rejected\n"));
849
850 /* update tally counter */
851 ++s->tally_counters.RxERR;
852
4f1c942b 853 return size;
a41b2ff2
PB		 854 }
855
856 packet_header |= RxBroadcast;
857
6cadb320
FB		 858 DEBUG_PRINT((">>> RTL8139: broadcast packet received\n"));
859
860 /* update tally counter */
861 ++s->tally_counters.RxOkBrd;
862
a41b2ff2
PB		 863 } else if (buf[0] & 0x01) {
864 /* multicast */
865 if (!(s->RxConfig & AcceptMulticast))
866 {
6cadb320
FB		 867 DEBUG_PRINT((">>> RTL8139: multicast packet rejected\n"));
868
869 /* update tally counter */
870 ++s->tally_counters.RxERR;
871
4f1c942b 872 return size;
a41b2ff2
PB		 873 }
874
875 int mcast_idx = compute_mcast_idx(buf);
876
877 if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))))
878 {
6cadb320
FB		 879 DEBUG_PRINT((">>> RTL8139: multicast address mismatch\n"));
880
881 /* update tally counter */
882 ++s->tally_counters.RxERR;
883
4f1c942b 884 return size;
a41b2ff2
PB		 885 }
886
887 packet_header |= RxMulticast;
888
6cadb320
FB		 889 DEBUG_PRINT((">>> RTL8139: multicast packet received\n"));
890
891 /* update tally counter */
892 ++s->tally_counters.RxOkMul;
893
a41b2ff2 894 } else if (s->phys[0] == buf[0] &&
3b46e624
TS		 895 s->phys[1] == buf[1] &&
896 s->phys[2] == buf[2] &&
897 s->phys[3] == buf[3] &&
898 s->phys[4] == buf[4] &&
a41b2ff2
PB		 899 s->phys[5] == buf[5]) {
900 /* match */
901 if (!(s->RxConfig & AcceptMyPhys))
902 {
6cadb320
FB		 903 DEBUG_PRINT((">>> RTL8139: rejecting physical address matching packet\n"));
904
905 /* update tally counter */
906 ++s->tally_counters.RxERR;
907
4f1c942b 908 return size;
a41b2ff2
PB		 909 }
910
911 packet_header |= RxPhysical;
912
6cadb320
FB		 913 DEBUG_PRINT((">>> RTL8139: physical address matching packet received\n"));
914
915 /* update tally counter */
916 ++s->tally_counters.RxOkPhy;
a41b2ff2
PB		 917
918 } else {
919
6cadb320
FB		 920 DEBUG_PRINT((">>> RTL8139: unknown packet\n"));
921
922 /* update tally counter */
923 ++s->tally_counters.RxERR;
924
4f1c942b 925 return size;
a41b2ff2
PB		 926 }
927 }
928
929 /* if too small buffer, then expand it */
930 if (size < MIN_BUF_SIZE) {
931 memcpy(buf1, buf, size);
932 memset(buf1 + size, 0, MIN_BUF_SIZE - size);
933 buf = buf1;
934 size = MIN_BUF_SIZE;
935 }
936
937 if (rtl8139_cp_receiver_enabled(s))
938 {
6cadb320 939 DEBUG_PRINT(("RTL8139: in C+ Rx mode ================\n"));
a41b2ff2
PB		 940
941 /* begin C+ receiver mode */
942
943/* w0 ownership flag */
944#define CP_RX_OWN (1<<31)
945/* w0 end of ring flag */
946#define CP_RX_EOR (1<<30)
947/* w0 bits 0...12 : buffer size */
948#define CP_RX_BUFFER_SIZE_MASK ((1<<13) - 1)
949/* w1 tag available flag */
950#define CP_RX_TAVA (1<<16)
951/* w1 bits 0...15 : VLAN tag */
952#define CP_RX_VLAN_TAG_MASK ((1<<16) - 1)
953/* w2 low 32bit of Rx buffer ptr */
954/* w3 high 32bit of Rx buffer ptr */
955
956 int descriptor = s->currCPlusRxDesc;
c227f099 957 target_phys_addr_t cplus_rx_ring_desc;
a41b2ff2
PB		 958
959 cplus_rx_ring_desc = rtl8139_addr64(s->RxRingAddrLO, s->RxRingAddrHI);
960 cplus_rx_ring_desc += 16 * descriptor;
961
6cadb320
FB		 962 DEBUG_PRINT(("RTL8139: +++ C+ mode reading RX descriptor %d from host memory at %08x %08x = %016" PRIx64 "\n",
963 descriptor, s->RxRingAddrHI, s->RxRingAddrLO, (uint64_t)cplus_rx_ring_desc));
a41b2ff2
PB		 964
965 uint32_t val, rxdw0,rxdw1,rxbufLO,rxbufHI;
966
967 cpu_physical_memory_read(cplus_rx_ring_desc, (uint8_t *)&val, 4);
968 rxdw0 = le32_to_cpu(val);
969 cpu_physical_memory_read(cplus_rx_ring_desc+4, (uint8_t *)&val, 4);
970 rxdw1 = le32_to_cpu(val);
971 cpu_physical_memory_read(cplus_rx_ring_desc+8, (uint8_t *)&val, 4);
972 rxbufLO = le32_to_cpu(val);
973 cpu_physical_memory_read(cplus_rx_ring_desc+12, (uint8_t *)&val, 4);
974 rxbufHI = le32_to_cpu(val);
975
6cadb320 976 DEBUG_PRINT(("RTL8139: +++ C+ mode RX descriptor %d %08x %08x %08x %08x\n",
a41b2ff2 977 descriptor,
6cadb320 978 rxdw0, rxdw1, rxbufLO, rxbufHI));
a41b2ff2
PB		 979
980 if (!(rxdw0 & CP_RX_OWN))
981 {
6cadb320
FB		 982 DEBUG_PRINT(("RTL8139: C+ Rx mode : descriptor %d is owned by host\n", descriptor));
983
a41b2ff2
PB		 984 s->IntrStatus |= RxOverflow;
985 ++s->RxMissed;
6cadb320
FB		 986
987 /* update tally counter */
988 ++s->tally_counters.RxERR;
989 ++s->tally_counters.MissPkt;
990
a41b2ff2 991 rtl8139_update_irq(s);
4f1c942b 992 return size_;
a41b2ff2
PB		 993 }
994
995 uint32_t rx_space = rxdw0 & CP_RX_BUFFER_SIZE_MASK;
996
6cadb320
FB		 997 /* TODO: scatter the packet over available receive ring descriptors space */
998
a41b2ff2
PB		 999 if (size+4 > rx_space)
1000 {
6cadb320
FB		 1001 DEBUG_PRINT(("RTL8139: C+ Rx mode : descriptor %d size %d received %d + 4\n",
1002 descriptor, rx_space, size));
1003
a41b2ff2
PB		 1004 s->IntrStatus |= RxOverflow;
1005 ++s->RxMissed;
6cadb320
FB		 1006
1007 /* update tally counter */
1008 ++s->tally_counters.RxERR;
1009 ++s->tally_counters.MissPkt;
1010
a41b2ff2 1011 rtl8139_update_irq(s);
4f1c942b 1012 return size_;
a41b2ff2
PB		 1013 }
1014
c227f099 1015 target_phys_addr_t rx_addr = rtl8139_addr64(rxbufLO, rxbufHI);
a41b2ff2
PB		 1016
1017 /* receive/copy to target memory */
1018 cpu_physical_memory_write( rx_addr, buf, size );
1019
6cadb320
FB		 1020 if (s->CpCmd & CPlusRxChkSum)
1021 {
1022 /* do some packet checksumming */
1023 }
1024
a41b2ff2
PB		 1025 /* write checksum */
1026#if defined (RTL8139_CALCULATE_RXCRC)
ccf1d14a 1027 val = cpu_to_le32(crc32(0, buf, size));
a41b2ff2
PB		 1028#else
1029 val = 0;
1030#endif
1031 cpu_physical_memory_write( rx_addr+size, (uint8_t *)&val, 4);
1032
1033/* first segment of received packet flag */
1034#define CP_RX_STATUS_FS (1<<29)
1035/* last segment of received packet flag */
1036#define CP_RX_STATUS_LS (1<<28)
1037/* multicast packet flag */
1038#define CP_RX_STATUS_MAR (1<<26)
1039/* physical-matching packet flag */
1040#define CP_RX_STATUS_PAM (1<<25)
1041/* broadcast packet flag */
1042#define CP_RX_STATUS_BAR (1<<24)
1043/* runt packet flag */
1044#define CP_RX_STATUS_RUNT (1<<19)
1045/* crc error flag */
1046#define CP_RX_STATUS_CRC (1<<18)
1047/* IP checksum error flag */
1048#define CP_RX_STATUS_IPF (1<<15)
1049/* UDP checksum error flag */
1050#define CP_RX_STATUS_UDPF (1<<14)
1051/* TCP checksum error flag */
1052#define CP_RX_STATUS_TCPF (1<<13)
1053
1054 /* transfer ownership to target */
1055 rxdw0 &= ~CP_RX_OWN;
1056
1057 /* set first segment bit */
1058 rxdw0 |= CP_RX_STATUS_FS;
1059
1060 /* set last segment bit */
1061 rxdw0 |= CP_RX_STATUS_LS;
1062
1063 /* set received packet type flags */
1064 if (packet_header & RxBroadcast)
1065 rxdw0 |= CP_RX_STATUS_BAR;
1066 if (packet_header & RxMulticast)
1067 rxdw0 |= CP_RX_STATUS_MAR;
1068 if (packet_header & RxPhysical)
1069 rxdw0 |= CP_RX_STATUS_PAM;
1070
1071 /* set received size */
1072 rxdw0 &= ~CP_RX_BUFFER_SIZE_MASK;
1073 rxdw0 |= (size+4);
1074
1075 /* reset VLAN tag flag */
1076 rxdw1 &= ~CP_RX_TAVA;
1077
1078 /* update ring data */
1079 val = cpu_to_le32(rxdw0);
1080 cpu_physical_memory_write(cplus_rx_ring_desc, (uint8_t *)&val, 4);
1081 val = cpu_to_le32(rxdw1);
1082 cpu_physical_memory_write(cplus_rx_ring_desc+4, (uint8_t *)&val, 4);
1083
6cadb320
FB		 1084 /* update tally counter */
1085 ++s->tally_counters.RxOk;
1086
a41b2ff2
PB		 1087 /* seek to next Rx descriptor */
1088 if (rxdw0 & CP_RX_EOR)
1089 {
1090 s->currCPlusRxDesc = 0;
1091 }
1092 else
1093 {
1094 ++s->currCPlusRxDesc;
1095 }
1096
6cadb320 1097 DEBUG_PRINT(("RTL8139: done C+ Rx mode ----------------\n"));
a41b2ff2
PB		 1098
1099 }
1100 else
1101 {
6cadb320
FB		 1102 DEBUG_PRINT(("RTL8139: in ring Rx mode ================\n"));
1103
a41b2ff2
PB		 1104 /* begin ring receiver mode */
1105 int avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, s->RxBufferSize);
1106
1107 /* if receiver buffer is empty then avail == 0 */
1108
1109 if (avail != 0 && size + 8 >= avail)
1110 {
6cadb320
FB		 1111 DEBUG_PRINT(("rx overflow: rx buffer length %d head 0x%04x read 0x%04x === available 0x%04x need 0x%04x\n",
1112 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr, avail, size + 8));
1113
a41b2ff2
PB		 1114 s->IntrStatus |= RxOverflow;
1115 ++s->RxMissed;
1116 rtl8139_update_irq(s);
4f1c942b 1117 return size_;
a41b2ff2
PB		 1118 }
1119
1120 packet_header |= RxStatusOK;
1121
1122 packet_header |= (((size+4) << 16) & 0xffff0000);
1123
1124 /* write header */
1125 uint32_t val = cpu_to_le32(packet_header);
1126
1127 rtl8139_write_buffer(s, (uint8_t *)&val, 4);
1128
1129 rtl8139_write_buffer(s, buf, size);
1130
1131 /* write checksum */
1132#if defined (RTL8139_CALCULATE_RXCRC)
ccf1d14a 1133 val = cpu_to_le32(crc32(0, buf, size));
a41b2ff2
PB		 1134#else
1135 val = 0;
1136#endif
1137
1138 rtl8139_write_buffer(s, (uint8_t *)&val, 4);
1139
1140 /* correct buffer write pointer */
1141 s->RxBufAddr = MOD2((s->RxBufAddr + 3) & ~0x3, s->RxBufferSize);
1142
1143 /* now we can signal we have received something */
1144
6cadb320
FB		 1145 DEBUG_PRINT((" received: rx buffer length %d head 0x%04x read 0x%04x\n",
1146 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr));
a41b2ff2
PB		 1147 }
1148
1149 s->IntrStatus |= RxOK;
6cadb320
FB		 1150
1151 if (do_interrupt)
1152 {
1153 rtl8139_update_irq(s);
1154 }
4f1c942b
MM		 1155
1156 return size_;
6cadb320
FB		 1157}
1158
1673ad51 1159static ssize_t rtl8139_receive(VLANClientState *nc, const uint8_t *buf, size_t size)
6cadb320 1160{
1673ad51 1161 return rtl8139_do_receive(nc, buf, size, 1);
a41b2ff2
PB		 1162}
1163
1164static void rtl8139_reset_rxring(RTL8139State *s, uint32_t bufferSize)
1165{
1166 s->RxBufferSize = bufferSize;
1167 s->RxBufPtr = 0;
1168 s->RxBufAddr = 0;
1169}
1170
7f23f812 1171static void rtl8139_reset(DeviceState *d)
a41b2ff2 1172{
7f23f812 1173 RTL8139State *s = container_of(d, RTL8139State, dev.qdev);
a41b2ff2
PB		 1174 int i;
1175
1176 /* restore MAC address */
254111ec 1177 memcpy(s->phys, s->conf.macaddr.a, 6);
a41b2ff2
PB		 1178
1179 /* reset interrupt mask */
1180 s->IntrStatus = 0;
1181 s->IntrMask = 0;
1182
1183 rtl8139_update_irq(s);
1184
1185 /* prepare eeprom */
1186 s->eeprom.contents[0] = 0x8129;
6cadb320
FB		 1187#if 1
1188 // PCI vendor and device ID should be mirrored here
deb54399
AL		 1189 s->eeprom.contents[1] = PCI_VENDOR_ID_REALTEK;
1190 s->eeprom.contents[2] = PCI_DEVICE_ID_REALTEK_8139;
6cadb320 1191#endif
290a0933 1192
254111ec
GH		 1193 s->eeprom.contents[7] = s->conf.macaddr.a[0] | s->conf.macaddr.a[1] << 8;
1194 s->eeprom.contents[8] = s->conf.macaddr.a[2] | s->conf.macaddr.a[3] << 8;
1195 s->eeprom.contents[9] = s->conf.macaddr.a[4] | s->conf.macaddr.a[5] << 8;
a41b2ff2
PB		 1196
1197 /* mark all status registers as owned by host */
1198 for (i = 0; i < 4; ++i)
1199 {
1200 s->TxStatus[i] = TxHostOwns;
1201 }
1202
1203 s->currTxDesc = 0;
1204 s->currCPlusRxDesc = 0;
1205 s->currCPlusTxDesc = 0;
1206
1207 s->RxRingAddrLO = 0;
1208 s->RxRingAddrHI = 0;
1209
1210 s->RxBuf = 0;
1211
1212 rtl8139_reset_rxring(s, 8192);
1213
1214 /* ACK the reset */
1215 s->TxConfig = 0;
1216
1217#if 0
1218// s->TxConfig |= HW_REVID(1, 0, 0, 0, 0, 0, 0); // RTL-8139 HasHltClk
1219 s->clock_enabled = 0;
1220#else
6cadb320 1221 s->TxConfig |= HW_REVID(1, 1, 1, 0, 1, 1, 0); // RTL-8139C+ HasLWake
a41b2ff2
PB		 1222 s->clock_enabled = 1;
1223#endif
1224
1225 s->bChipCmdState = CmdReset; /* RxBufEmpty bit is calculated on read from ChipCmd */;
1226
1227 /* set initial state data */
1228 s->Config0 = 0x0; /* No boot ROM */
1229 s->Config1 = 0xC; /* IO mapped and MEM mapped registers available */
1230 s->Config3 = 0x1; /* fast back-to-back compatible */
1231 s->Config5 = 0x0;
1232
5fafdf24 1233 s->CSCR = CSCR_F_LINK_100 | CSCR_HEART_BIT | CSCR_LD;
a41b2ff2
PB		 1234
1235 s->CpCmd = 0x0; /* reset C+ mode */
2c3891ab
AL		 1236 s->cplus_enabled = 0;
1237
a41b2ff2
PB		 1238
1239// s->BasicModeCtrl = 0x3100; // 100Mbps, full duplex, autonegotiation
1240// s->BasicModeCtrl = 0x2100; // 100Mbps, full duplex
1241 s->BasicModeCtrl = 0x1000; // autonegotiation
1242
1243 s->BasicModeStatus = 0x7809;
1244 //s->BasicModeStatus |= 0x0040; /* UTP medium */
1245 s->BasicModeStatus |= 0x0020; /* autonegotiation completed */
1246 s->BasicModeStatus |= 0x0004; /* link is up */
1247
1248 s->NWayAdvert = 0x05e1; /* all modes, full duplex */
1249 s->NWayLPAR = 0x05e1; /* all modes, full duplex */
1250 s->NWayExpansion = 0x0001; /* autonegotiation supported */
6cadb320
FB		 1251
1252 /* also reset timer and disable timer interrupt */
1253 s->TCTR = 0;
1254 s->TimerInt = 0;
1255 s->TCTR_base = 0;
1256
1257 /* reset tally counters */
1258 RTL8139TallyCounters_clear(&s->tally_counters);
1259}
1260
b1d8e52e 1261static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters)
6cadb320
FB		 1262{
1263 counters->TxOk = 0;
1264 counters->RxOk = 0;
1265 counters->TxERR = 0;
1266 counters->RxERR = 0;
1267 counters->MissPkt = 0;
1268 counters->FAE = 0;
1269 counters->Tx1Col = 0;
1270 counters->TxMCol = 0;
1271 counters->RxOkPhy = 0;
1272 counters->RxOkBrd = 0;
1273 counters->RxOkMul = 0;
1274 counters->TxAbt = 0;
1275 counters->TxUndrn = 0;
1276}
1277
c227f099 1278static void RTL8139TallyCounters_physical_memory_write(target_phys_addr_t tc_addr, RTL8139TallyCounters* tally_counters)
6cadb320
FB		 1279{
1280 uint16_t val16;
1281 uint32_t val32;
1282 uint64_t val64;
1283
1284 val64 = cpu_to_le64(tally_counters->TxOk);
1285 cpu_physical_memory_write(tc_addr + 0, (uint8_t *)&val64, 8);
1286
1287 val64 = cpu_to_le64(tally_counters->RxOk);
1288 cpu_physical_memory_write(tc_addr + 8, (uint8_t *)&val64, 8);
1289
1290 val64 = cpu_to_le64(tally_counters->TxERR);
1291 cpu_physical_memory_write(tc_addr + 16, (uint8_t *)&val64, 8);
1292
1293 val32 = cpu_to_le32(tally_counters->RxERR);
1294 cpu_physical_memory_write(tc_addr + 24, (uint8_t *)&val32, 4);
1295
1296 val16 = cpu_to_le16(tally_counters->MissPkt);
1297 cpu_physical_memory_write(tc_addr + 28, (uint8_t *)&val16, 2);
1298
1299 val16 = cpu_to_le16(tally_counters->FAE);
1300 cpu_physical_memory_write(tc_addr + 30, (uint8_t *)&val16, 2);
1301
1302 val32 = cpu_to_le32(tally_counters->Tx1Col);
1303 cpu_physical_memory_write(tc_addr + 32, (uint8_t *)&val32, 4);
1304
1305 val32 = cpu_to_le32(tally_counters->TxMCol);
1306 cpu_physical_memory_write(tc_addr + 36, (uint8_t *)&val32, 4);
1307
1308 val64 = cpu_to_le64(tally_counters->RxOkPhy);
1309 cpu_physical_memory_write(tc_addr + 40, (uint8_t *)&val64, 8);
1310
1311 val64 = cpu_to_le64(tally_counters->RxOkBrd);
1312 cpu_physical_memory_write(tc_addr + 48, (uint8_t *)&val64, 8);
1313
1314 val32 = cpu_to_le32(tally_counters->RxOkMul);
1315 cpu_physical_memory_write(tc_addr + 56, (uint8_t *)&val32, 4);
1316
1317 val16 = cpu_to_le16(tally_counters->TxAbt);
1318 cpu_physical_memory_write(tc_addr + 60, (uint8_t *)&val16, 2);
1319
1320 val16 = cpu_to_le16(tally_counters->TxUndrn);
1321 cpu_physical_memory_write(tc_addr + 62, (uint8_t *)&val16, 2);
1322}
1323
1324/* Loads values of tally counters from VM state file */
9d29cdea
JQ		 1325
1326static const VMStateDescription vmstate_tally_counters = {
1327 .name = "tally_counters",
1328 .version_id = 1,
1329 .minimum_version_id = 1,
1330 .minimum_version_id_old = 1,
1331 .fields = (VMStateField []) {
1332 VMSTATE_UINT64(TxOk, RTL8139TallyCounters),
1333 VMSTATE_UINT64(RxOk, RTL8139TallyCounters),
1334 VMSTATE_UINT64(TxERR, RTL8139TallyCounters),
1335 VMSTATE_UINT32(RxERR, RTL8139TallyCounters),
1336 VMSTATE_UINT16(MissPkt, RTL8139TallyCounters),
1337 VMSTATE_UINT16(FAE, RTL8139TallyCounters),
1338 VMSTATE_UINT32(Tx1Col, RTL8139TallyCounters),
1339 VMSTATE_UINT32(TxMCol, RTL8139TallyCounters),
1340 VMSTATE_UINT64(RxOkPhy, RTL8139TallyCounters),
1341 VMSTATE_UINT64(RxOkBrd, RTL8139TallyCounters),
1342 VMSTATE_UINT16(TxAbt, RTL8139TallyCounters),
1343 VMSTATE_UINT16(TxUndrn, RTL8139TallyCounters),
1344 VMSTATE_END_OF_LIST()
1345 }
1346};
a41b2ff2
PB		 1347
1348static void rtl8139_ChipCmd_write(RTL8139State *s, uint32_t val)
1349{
1350 val &= 0xff;
1351
6cadb320 1352 DEBUG_PRINT(("RTL8139: ChipCmd write val=0x%08x\n", val));
a41b2ff2
PB		 1353
1354 if (val & CmdReset)
1355 {
6cadb320 1356 DEBUG_PRINT(("RTL8139: ChipCmd reset\n"));
7f23f812 1357 rtl8139_reset(&s->dev.qdev);
a41b2ff2
PB		 1358 }
1359 if (val & CmdRxEnb)
1360 {
6cadb320 1361 DEBUG_PRINT(("RTL8139: ChipCmd enable receiver\n"));
718da2b9
FB		 1362
1363 s->currCPlusRxDesc = 0;
a41b2ff2
PB		 1364 }
1365 if (val & CmdTxEnb)
1366 {
6cadb320 1367 DEBUG_PRINT(("RTL8139: ChipCmd enable transmitter\n"));
718da2b9
FB		 1368
1369 s->currCPlusTxDesc = 0;
a41b2ff2
PB		 1370 }
1371
1372 /* mask unwriteable bits */
1373 val = SET_MASKED(val, 0xe3, s->bChipCmdState);
1374
1375 /* Deassert reset pin before next read */
1376 val &= ~CmdReset;
1377
1378 s->bChipCmdState = val;
1379}
1380
1381static int rtl8139_RxBufferEmpty(RTL8139State *s)
1382{
1383 int unread = MOD2(s->RxBufferSize + s->RxBufAddr - s->RxBufPtr, s->RxBufferSize);
1384
1385 if (unread != 0)
1386 {
6cadb320 1387 DEBUG_PRINT(("RTL8139: receiver buffer data available 0x%04x\n", unread));
a41b2ff2
PB		 1388 return 0;
1389 }
1390
6cadb320 1391 DEBUG_PRINT(("RTL8139: receiver buffer is empty\n"));
a41b2ff2
PB		 1392
1393 return 1;
1394}
1395
1396static uint32_t rtl8139_ChipCmd_read(RTL8139State *s)
1397{
1398 uint32_t ret = s->bChipCmdState;
1399
1400 if (rtl8139_RxBufferEmpty(s))
1401 ret |= RxBufEmpty;
1402
6cadb320 1403 DEBUG_PRINT(("RTL8139: ChipCmd read val=0x%04x\n", ret));
a41b2ff2
PB		 1404
1405 return ret;
1406}
1407
1408static void rtl8139_CpCmd_write(RTL8139State *s, uint32_t val)
1409{
1410 val &= 0xffff;
1411
6cadb320 1412 DEBUG_PRINT(("RTL8139C+ command register write(w) val=0x%04x\n", val));
a41b2ff2 1413
2c3891ab
AL		 1414 s->cplus_enabled = 1;
1415
a41b2ff2
PB		 1416 /* mask unwriteable bits */
1417 val = SET_MASKED(val, 0xff84, s->CpCmd);
1418
1419 s->CpCmd = val;
1420}
1421
1422static uint32_t rtl8139_CpCmd_read(RTL8139State *s)
1423{
1424 uint32_t ret = s->CpCmd;
1425
6cadb320
FB		 1426 DEBUG_PRINT(("RTL8139C+ command register read(w) val=0x%04x\n", ret));
1427
1428 return ret;
1429}
1430
1431static void rtl8139_IntrMitigate_write(RTL8139State *s, uint32_t val)
1432{
1433 DEBUG_PRINT(("RTL8139C+ IntrMitigate register write(w) val=0x%04x\n", val));
1434}
1435
1436static uint32_t rtl8139_IntrMitigate_read(RTL8139State *s)
1437{
1438 uint32_t ret = 0;
1439
1440 DEBUG_PRINT(("RTL8139C+ IntrMitigate register read(w) val=0x%04x\n", ret));
a41b2ff2
PB		 1441
1442 return ret;
1443}
1444
9596ebb7 1445static int rtl8139_config_writeable(RTL8139State *s)
a41b2ff2
PB		 1446{
1447 if (s->Cfg9346 & Cfg9346_Unlock)
1448 {
1449 return 1;
1450 }
1451
6cadb320 1452 DEBUG_PRINT(("RTL8139: Configuration registers are write-protected\n"));
a41b2ff2
PB		 1453
1454 return 0;
1455}
1456
1457static void rtl8139_BasicModeCtrl_write(RTL8139State *s, uint32_t val)
1458{
1459 val &= 0xffff;
1460
6cadb320 1461 DEBUG_PRINT(("RTL8139: BasicModeCtrl register write(w) val=0x%04x\n", val));
a41b2ff2
PB		 1462
1463 /* mask unwriteable bits */
e3d7e843 1464 uint32_t mask = 0x4cff;
a41b2ff2
PB		 1465
1466 if (1 || !rtl8139_config_writeable(s))
1467 {
1468 /* Speed setting and autonegotiation enable bits are read-only */
1469 mask |= 0x3000;
1470 /* Duplex mode setting is read-only */
1471 mask |= 0x0100;
1472 }
1473
1474 val = SET_MASKED(val, mask, s->BasicModeCtrl);
1475
1476 s->BasicModeCtrl = val;
1477}
1478
1479static uint32_t rtl8139_BasicModeCtrl_read(RTL8139State *s)
1480{
1481 uint32_t ret = s->BasicModeCtrl;
1482
6cadb320 1483 DEBUG_PRINT(("RTL8139: BasicModeCtrl register read(w) val=0x%04x\n", ret));
a41b2ff2
PB		 1484
1485 return ret;
1486}
1487
1488static void rtl8139_BasicModeStatus_write(RTL8139State *s, uint32_t val)
1489{
1490 val &= 0xffff;
1491
6cadb320 1492 DEBUG_PRINT(("RTL8139: BasicModeStatus register write(w) val=0x%04x\n", val));
a41b2ff2
PB		 1493
1494 /* mask unwriteable bits */
1495 val = SET_MASKED(val, 0xff3f, s->BasicModeStatus);
1496
1497 s->BasicModeStatus = val;
1498}
1499
1500static uint32_t rtl8139_BasicModeStatus_read(RTL8139State *s)
1501{
1502 uint32_t ret = s->BasicModeStatus;
1503
6cadb320 1504 DEBUG_PRINT(("RTL8139: BasicModeStatus register read(w) val=0x%04x\n", ret));
a41b2ff2
PB		 1505
1506 return ret;
1507}
1508
1509static void rtl8139_Cfg9346_write(RTL8139State *s, uint32_t val)
1510{
1511 val &= 0xff;
1512
6cadb320 1513 DEBUG_PRINT(("RTL8139: Cfg9346 write val=0x%02x\n", val));
a41b2ff2
PB		 1514
1515 /* mask unwriteable bits */
1516 val = SET_MASKED(val, 0x31, s->Cfg9346);
1517
1518 uint32_t opmode = val & 0xc0;
1519 uint32_t eeprom_val = val & 0xf;
1520
1521 if (opmode == 0x80) {
1522 /* eeprom access */
1523 int eecs = (eeprom_val & 0x08)?1:0;
1524 int eesk = (eeprom_val & 0x04)?1:0;
1525 int eedi = (eeprom_val & 0x02)?1:0;
1526 prom9346_set_wire(s, eecs, eesk, eedi);
1527 } else if (opmode == 0x40) {
1528 /* Reset. */
1529 val = 0;
7f23f812 1530 rtl8139_reset(&s->dev.qdev);
a41b2ff2
PB		 1531 }
1532
1533 s->Cfg9346 = val;
1534}
1535
1536static uint32_t rtl8139_Cfg9346_read(RTL8139State *s)
1537{
1538 uint32_t ret = s->Cfg9346;
1539
1540 uint32_t opmode = ret & 0xc0;
1541
1542 if (opmode == 0x80)
1543 {
1544 /* eeprom access */
1545 int eedo = prom9346_get_wire(s);
1546 if (eedo)
1547 {
1548 ret |= 0x01;
1549 }
1550 else
1551 {
1552 ret &= ~0x01;
1553 }
1554 }
1555
6cadb320 1556 DEBUG_PRINT(("RTL8139: Cfg9346 read val=0x%02x\n", ret));
a41b2ff2
PB		 1557
1558 return ret;
1559}
1560
1561static void rtl8139_Config0_write(RTL8139State *s, uint32_t val)
1562{
1563 val &= 0xff;
1564
6cadb320 1565 DEBUG_PRINT(("RTL8139: Config0 write val=0x%02x\n", val));
a41b2ff2
PB		 1566
1567 if (!rtl8139_config_writeable(s))
1568 return;
1569
1570 /* mask unwriteable bits */
1571 val = SET_MASKED(val, 0xf8, s->Config0);
1572
1573 s->Config0 = val;
1574}
1575
1576static uint32_t rtl8139_Config0_read(RTL8139State *s)
1577{
1578 uint32_t ret = s->Config0;
1579
6cadb320 1580 DEBUG_PRINT(("RTL8139: Config0 read val=0x%02x\n", ret));
a41b2ff2
PB		 1581
1582 return ret;
1583}
1584
1585static void rtl8139_Config1_write(RTL8139State *s, uint32_t val)
1586{
1587 val &= 0xff;
1588
6cadb320 1589 DEBUG_PRINT(("RTL8139: Config1 write val=0x%02x\n", val));
a41b2ff2
PB		 1590
1591 if (!rtl8139_config_writeable(s))
1592 return;
1593
1594 /* mask unwriteable bits */
1595 val = SET_MASKED(val, 0xC, s->Config1);
1596
1597 s->Config1 = val;
1598}
1599
1600static uint32_t rtl8139_Config1_read(RTL8139State *s)
1601{
1602 uint32_t ret = s->Config1;
1603
6cadb320 1604 DEBUG_PRINT(("RTL8139: Config1 read val=0x%02x\n", ret));
a41b2ff2
PB		 1605
1606 return ret;
1607}
1608
1609static void rtl8139_Config3_write(RTL8139State *s, uint32_t val)
1610{
1611 val &= 0xff;
1612
6cadb320 1613 DEBUG_PRINT(("RTL8139: Config3 write val=0x%02x\n", val));
a41b2ff2
PB		 1614
1615 if (!rtl8139_config_writeable(s))
1616 return;
1617
1618 /* mask unwriteable bits */
1619 val = SET_MASKED(val, 0x8F, s->Config3);
1620
1621 s->Config3 = val;
1622}
1623
1624static uint32_t rtl8139_Config3_read(RTL8139State *s)
1625{
1626 uint32_t ret = s->Config3;
1627
6cadb320 1628 DEBUG_PRINT(("RTL8139: Config3 read val=0x%02x\n", ret));
a41b2ff2
PB		 1629
1630 return ret;
1631}
1632
1633static void rtl8139_Config4_write(RTL8139State *s, uint32_t val)
1634{
1635 val &= 0xff;
1636
6cadb320 1637 DEBUG_PRINT(("RTL8139: Config4 write val=0x%02x\n", val));
a41b2ff2
PB		 1638
1639 if (!rtl8139_config_writeable(s))
1640 return;
1641
1642 /* mask unwriteable bits */
1643 val = SET_MASKED(val, 0x0a, s->Config4);
1644
1645 s->Config4 = val;
1646}
1647
1648static uint32_t rtl8139_Config4_read(RTL8139State *s)
1649{
1650 uint32_t ret = s->Config4;
1651
6cadb320 1652 DEBUG_PRINT(("RTL8139: Config4 read val=0x%02x\n", ret));
a41b2ff2
PB		 1653
1654 return ret;
1655}
1656
1657static void rtl8139_Config5_write(RTL8139State *s, uint32_t val)
1658{
1659 val &= 0xff;
1660
6cadb320 1661 DEBUG_PRINT(("RTL8139: Config5 write val=0x%02x\n", val));
a41b2ff2
PB		 1662
1663 /* mask unwriteable bits */
1664 val = SET_MASKED(val, 0x80, s->Config5);
1665
1666 s->Config5 = val;
1667}
1668
1669static uint32_t rtl8139_Config5_read(RTL8139State *s)
1670{
1671 uint32_t ret = s->Config5;
1672
6cadb320 1673 DEBUG_PRINT(("RTL8139: Config5 read val=0x%02x\n", ret));
a41b2ff2
PB		 1674
1675 return ret;
1676}
1677
1678static void rtl8139_TxConfig_write(RTL8139State *s, uint32_t val)
1679{
1680 if (!rtl8139_transmitter_enabled(s))
1681 {
6cadb320 1682 DEBUG_PRINT(("RTL8139: transmitter disabled; no TxConfig write val=0x%08x\n", val));
a41b2ff2
PB		 1683 return;
1684 }
1685
6cadb320 1686 DEBUG_PRINT(("RTL8139: TxConfig write val=0x%08x\n", val));
a41b2ff2
PB		 1687
1688 val = SET_MASKED(val, TxVersionMask | 0x8070f80f, s->TxConfig);
1689
1690 s->TxConfig = val;
1691}
1692
1693static void rtl8139_TxConfig_writeb(RTL8139State *s, uint32_t val)
1694{
6cadb320
FB		 1695 DEBUG_PRINT(("RTL8139C TxConfig via write(b) val=0x%02x\n", val));
1696
1697 uint32_t tc = s->TxConfig;
1698 tc &= 0xFFFFFF00;
1699 tc |= (val & 0x000000FF);
1700 rtl8139_TxConfig_write(s, tc);
a41b2ff2
PB		 1701}
1702
1703static uint32_t rtl8139_TxConfig_read(RTL8139State *s)
1704{
1705 uint32_t ret = s->TxConfig;
1706
6cadb320 1707 DEBUG_PRINT(("RTL8139: TxConfig read val=0x%04x\n", ret));
a41b2ff2
PB		 1708
1709 return ret;
1710}
1711
1712static void rtl8139_RxConfig_write(RTL8139State *s, uint32_t val)
1713{
6cadb320 1714 DEBUG_PRINT(("RTL8139: RxConfig write val=0x%08x\n", val));
a41b2ff2
PB		 1715
1716 /* mask unwriteable bits */
1717 val = SET_MASKED(val, 0xf0fc0040, s->RxConfig);
1718
1719 s->RxConfig = val;
1720
1721 /* reset buffer size and read/write pointers */
1722 rtl8139_reset_rxring(s, 8192 << ((s->RxConfig >> 11) & 0x3));
1723
6cadb320 1724 DEBUG_PRINT(("RTL8139: RxConfig write reset buffer size to %d\n", s->RxBufferSize));
a41b2ff2
PB		 1725}
1726
1727static uint32_t rtl8139_RxConfig_read(RTL8139State *s)
1728{
1729 uint32_t ret = s->RxConfig;
1730
6cadb320 1731 DEBUG_PRINT(("RTL8139: RxConfig read val=0x%08x\n", ret));
a41b2ff2
PB		 1732
1733 return ret;
1734}
1735
718da2b9
FB		 1736static void rtl8139_transfer_frame(RTL8139State *s, const uint8_t *buf, int size, int do_interrupt)
1737{
1738 if (!size)
1739 {
1740 DEBUG_PRINT(("RTL8139: +++ empty ethernet frame\n"));
1741 return;
1742 }
1743
1744 if (TxLoopBack == (s->TxConfig & TxLoopBack))
1745 {
1746 DEBUG_PRINT(("RTL8139: +++ transmit loopback mode\n"));
1673ad51 1747 rtl8139_do_receive(&s->nic->nc, buf, size, do_interrupt);
718da2b9
FB		 1748 }
1749 else
1750 {
1673ad51 1751 qemu_send_packet(&s->nic->nc, buf, size);
718da2b9
FB		 1752 }
1753}
1754
a41b2ff2
PB		 1755static int rtl8139_transmit_one(RTL8139State *s, int descriptor)
1756{
1757 if (!rtl8139_transmitter_enabled(s))
1758 {
6cadb320
FB		 1759 DEBUG_PRINT(("RTL8139: +++ cannot transmit from descriptor %d: transmitter disabled\n",
1760 descriptor));
a41b2ff2
PB		 1761 return 0;
1762 }
1763
1764 if (s->TxStatus[descriptor] & TxHostOwns)
1765 {
6cadb320
FB		 1766 DEBUG_PRINT(("RTL8139: +++ cannot transmit from descriptor %d: owned by host (%08x)\n",
1767 descriptor, s->TxStatus[descriptor]));
a41b2ff2
PB		 1768 return 0;
1769 }
1770
6cadb320 1771 DEBUG_PRINT(("RTL8139: +++ transmitting from descriptor %d\n", descriptor));
a41b2ff2
PB		 1772
1773 int txsize = s->TxStatus[descriptor] & 0x1fff;
1774 uint8_t txbuffer[0x2000];
1775
6cadb320
FB		 1776 DEBUG_PRINT(("RTL8139: +++ transmit reading %d bytes from host memory at 0x%08x\n",
1777 txsize, s->TxAddr[descriptor]));
a41b2ff2 1778
6cadb320 1779 cpu_physical_memory_read(s->TxAddr[descriptor], txbuffer, txsize);
a41b2ff2
PB		 1780
1781 /* Mark descriptor as transferred */
1782 s->TxStatus[descriptor] |= TxHostOwns;
1783 s->TxStatus[descriptor] |= TxStatOK;
1784
718da2b9 1785 rtl8139_transfer_frame(s, txbuffer, txsize, 0);
6cadb320
FB		 1786
1787 DEBUG_PRINT(("RTL8139: +++ transmitted %d bytes from descriptor %d\n", txsize, descriptor));
a41b2ff2
PB		 1788
1789 /* update interrupt */
1790 s->IntrStatus |= TxOK;
1791 rtl8139_update_irq(s);
1792
1793 return 1;
1794}
1795
718da2b9
FB		 1796/* structures and macros for task offloading */
1797typedef struct ip_header
1798{
1799 uint8_t ip_ver_len; /* version and header length */
1800 uint8_t ip_tos; /* type of service */
1801 uint16_t ip_len; /* total length */
1802 uint16_t ip_id; /* identification */
1803 uint16_t ip_off; /* fragment offset field */
1804 uint8_t ip_ttl; /* time to live */
1805 uint8_t ip_p; /* protocol */
1806 uint16_t ip_sum; /* checksum */
1807 uint32_t ip_src,ip_dst; /* source and dest address */
1808} ip_header;
1809
1810#define IP_HEADER_VERSION_4 4
1811#define IP_HEADER_VERSION(ip) ((ip->ip_ver_len >> 4)&0xf)
1812#define IP_HEADER_LENGTH(ip) (((ip->ip_ver_len)&0xf) << 2)
1813
1814typedef struct tcp_header
1815{
1816 uint16_t th_sport; /* source port */
1817 uint16_t th_dport; /* destination port */
1818 uint32_t th_seq; /* sequence number */
1819 uint32_t th_ack; /* acknowledgement number */
1820 uint16_t th_offset_flags; /* data offset, reserved 6 bits, TCP protocol flags */
1821 uint16_t th_win; /* window */
1822 uint16_t th_sum; /* checksum */
1823 uint16_t th_urp; /* urgent pointer */
1824} tcp_header;
1825
1826typedef struct udp_header
1827{
1828 uint16_t uh_sport; /* source port */
1829 uint16_t uh_dport; /* destination port */
1830 uint16_t uh_ulen; /* udp length */
1831 uint16_t uh_sum; /* udp checksum */
1832} udp_header;
1833
1834typedef struct ip_pseudo_header
1835{
1836 uint32_t ip_src;
1837 uint32_t ip_dst;
1838 uint8_t zeros;
1839 uint8_t ip_proto;
1840 uint16_t ip_payload;
1841} ip_pseudo_header;
1842
1843#define IP_PROTO_TCP 6
1844#define IP_PROTO_UDP 17
1845
1846#define TCP_HEADER_DATA_OFFSET(tcp) (((be16_to_cpu(tcp->th_offset_flags) >> 12)&0xf) << 2)
1847#define TCP_FLAGS_ONLY(flags) ((flags)&0x3f)
1848#define TCP_HEADER_FLAGS(tcp) TCP_FLAGS_ONLY(be16_to_cpu(tcp->th_offset_flags))
1849
1850#define TCP_HEADER_CLEAR_FLAGS(tcp, off) ((tcp)->th_offset_flags &= cpu_to_be16(~TCP_FLAGS_ONLY(off)))
1851
1852#define TCP_FLAG_FIN 0x01
1853#define TCP_FLAG_PUSH 0x08
1854
1855/* produces ones' complement sum of data */
1856static uint16_t ones_complement_sum(uint8_t *data, size_t len)
1857{
1858 uint32_t result = 0;
1859
1860 for (; len > 1; data+=2, len-=2)
1861 {
1862 result += *(uint16_t*)data;
1863 }
1864
1865 /* add the remainder byte */
1866 if (len)
1867 {
1868 uint8_t odd[2] = {*data, 0};
1869 result += *(uint16_t*)odd;
1870 }
1871
1872 while (result>>16)
1873 result = (result & 0xffff) + (result >> 16);
1874
1875 return result;
1876}
1877
1878static uint16_t ip_checksum(void *data, size_t len)
1879{
1880 return ~ones_complement_sum((uint8_t*)data, len);
1881}
1882
a41b2ff2
PB		 1883static int rtl8139_cplus_transmit_one(RTL8139State *s)
1884{
1885 if (!rtl8139_transmitter_enabled(s))
1886 {
6cadb320 1887 DEBUG_PRINT(("RTL8139: +++ C+ mode: transmitter disabled\n"));
a41b2ff2
PB		 1888 return 0;
1889 }
1890
1891 if (!rtl8139_cp_transmitter_enabled(s))
1892 {
6cadb320 1893 DEBUG_PRINT(("RTL8139: +++ C+ mode: C+ transmitter disabled\n"));
a41b2ff2
PB		 1894 return 0 ;
1895 }
1896
1897 int descriptor = s->currCPlusTxDesc;
1898
c227f099 1899 target_phys_addr_t cplus_tx_ring_desc =
a41b2ff2
PB		 1900 rtl8139_addr64(s->TxAddr[0], s->TxAddr[1]);
1901
1902 /* Normal priority ring */
1903 cplus_tx_ring_desc += 16 * descriptor;
1904
6cadb320
FB		 1905 DEBUG_PRINT(("RTL8139: +++ C+ mode reading TX descriptor %d from host memory at %08x0x%08x = 0x%8lx\n",
1906 descriptor, s->TxAddr[1], s->TxAddr[0], cplus_tx_ring_desc));
a41b2ff2
PB		 1907
1908 uint32_t val, txdw0,txdw1,txbufLO,txbufHI;
1909
1910 cpu_physical_memory_read(cplus_tx_ring_desc, (uint8_t *)&val, 4);
1911 txdw0 = le32_to_cpu(val);
4ef1a3d3 1912 /* TODO: implement VLAN tagging support, VLAN tag data is read to txdw1 */
a41b2ff2
PB		 1913 cpu_physical_memory_read(cplus_tx_ring_desc+4, (uint8_t *)&val, 4);
1914 txdw1 = le32_to_cpu(val);
1915 cpu_physical_memory_read(cplus_tx_ring_desc+8, (uint8_t *)&val, 4);
1916 txbufLO = le32_to_cpu(val);
1917 cpu_physical_memory_read(cplus_tx_ring_desc+12, (uint8_t *)&val, 4);
1918 txbufHI = le32_to_cpu(val);
1919
6cadb320 1920 DEBUG_PRINT(("RTL8139: +++ C+ mode TX descriptor %d %08x %08x %08x %08x\n",
a41b2ff2 1921 descriptor,
6cadb320 1922 txdw0, txdw1, txbufLO, txbufHI));
a41b2ff2 1923
4ef1a3d3
IK		 1924 /* TODO: the following discard cast should clean clang analyzer output */
1925 (void)txdw1;
1926
a41b2ff2
PB		 1927/* w0 ownership flag */
1928#define CP_TX_OWN (1<<31)
1929/* w0 end of ring flag */
1930#define CP_TX_EOR (1<<30)
1931/* first segment of received packet flag */
1932#define CP_TX_FS (1<<29)
1933/* last segment of received packet flag */
1934#define CP_TX_LS (1<<28)
1935/* large send packet flag */
1936#define CP_TX_LGSEN (1<<27)
718da2b9
FB		 1937/* large send MSS mask, bits 16...25 */
1938#define CP_TC_LGSEN_MSS_MASK ((1 << 12) - 1)
1939
a41b2ff2
PB		 1940/* IP checksum offload flag */
1941#define CP_TX_IPCS (1<<18)
1942/* UDP checksum offload flag */
1943#define CP_TX_UDPCS (1<<17)
1944/* TCP checksum offload flag */
1945#define CP_TX_TCPCS (1<<16)
1946
1947/* w0 bits 0...15 : buffer size */
1948#define CP_TX_BUFFER_SIZE (1<<16)
1949#define CP_TX_BUFFER_SIZE_MASK (CP_TX_BUFFER_SIZE - 1)
1950/* w1 tag available flag */
1951#define CP_RX_TAGC (1<<17)
1952/* w1 bits 0...15 : VLAN tag */
1953#define CP_TX_VLAN_TAG_MASK ((1<<16) - 1)
1954/* w2 low 32bit of Rx buffer ptr */
1955/* w3 high 32bit of Rx buffer ptr */
1956
1957/* set after transmission */
1958/* FIFO underrun flag */
1959#define CP_TX_STATUS_UNF (1<<25)
1960/* transmit error summary flag, valid if set any of three below */
1961#define CP_TX_STATUS_TES (1<<23)
1962/* out-of-window collision flag */
1963#define CP_TX_STATUS_OWC (1<<22)
1964/* link failure flag */
1965#define CP_TX_STATUS_LNKF (1<<21)
1966/* excessive collisions flag */
1967#define CP_TX_STATUS_EXC (1<<20)
1968
1969 if (!(txdw0 & CP_TX_OWN))
1970 {
6cadb320 1971 DEBUG_PRINT(("RTL8139: C+ Tx mode : descriptor %d is owned by host\n", descriptor));
a41b2ff2
PB		 1972 return 0 ;
1973 }
1974
6cadb320
FB		 1975 DEBUG_PRINT(("RTL8139: +++ C+ Tx mode : transmitting from descriptor %d\n", descriptor));
1976
1977 if (txdw0 & CP_TX_FS)
1978 {
1979 DEBUG_PRINT(("RTL8139: +++ C+ Tx mode : descriptor %d is first segment descriptor\n", descriptor));
1980
1981 /* reset internal buffer offset */
1982 s->cplus_txbuffer_offset = 0;
1983 }
a41b2ff2
PB		 1984
1985 int txsize = txdw0 & CP_TX_BUFFER_SIZE_MASK;
c227f099 1986 target_phys_addr_t tx_addr = rtl8139_addr64(txbufLO, txbufHI);
a41b2ff2 1987
6cadb320
FB		 1988 /* make sure we have enough space to assemble the packet */
1989 if (!s->cplus_txbuffer)
1990 {
1991 s->cplus_txbuffer_len = CP_TX_BUFFER_SIZE;
2bc6f59b 1992 s->cplus_txbuffer = qemu_malloc(s->cplus_txbuffer_len);
6cadb320 1993 s->cplus_txbuffer_offset = 0;
718da2b9
FB		 1994
1995 DEBUG_PRINT(("RTL8139: +++ C+ mode transmission buffer allocated space %d\n", s->cplus_txbuffer_len));
6cadb320
FB		 1996 }
1997
1998 while (s->cplus_txbuffer && s->cplus_txbuffer_offset + txsize >= s->cplus_txbuffer_len)
1999 {
2000 s->cplus_txbuffer_len += CP_TX_BUFFER_SIZE;
2137b4cc 2001 s->cplus_txbuffer = qemu_realloc(s->cplus_txbuffer, s->cplus_txbuffer_len);
a41b2ff2 2002
6cadb320
FB		 2003 DEBUG_PRINT(("RTL8139: +++ C+ mode transmission buffer space changed to %d\n", s->cplus_txbuffer_len));
2004 }
2005
2006 if (!s->cplus_txbuffer)
2007 {
2008 /* out of memory */
a41b2ff2 2009
6cadb320
FB		 2010 DEBUG_PRINT(("RTL8139: +++ C+ mode transmiter failed to reallocate %d bytes\n", s->cplus_txbuffer_len));
2011
2012 /* update tally counter */
2013 ++s->tally_counters.TxERR;
2014 ++s->tally_counters.TxAbt;
2015
2016 return 0;
2017 }
2018
2019 /* append more data to the packet */
2020
2021 DEBUG_PRINT(("RTL8139: +++ C+ mode transmit reading %d bytes from host memory at %016" PRIx64 " to offset %d\n",
2022 txsize, (uint64_t)tx_addr, s->cplus_txbuffer_offset));
2023
2024 cpu_physical_memory_read(tx_addr, s->cplus_txbuffer + s->cplus_txbuffer_offset, txsize);
2025 s->cplus_txbuffer_offset += txsize;
2026
2027 /* seek to next Rx descriptor */
2028 if (txdw0 & CP_TX_EOR)
2029 {
2030 s->currCPlusTxDesc = 0;
2031 }
2032 else
2033 {
2034 ++s->currCPlusTxDesc;
2035 if (s->currCPlusTxDesc >= 64)
2036 s->currCPlusTxDesc = 0;
2037 }
a41b2ff2
PB		 2038
2039 /* transfer ownership to target */
2040 txdw0 &= ~CP_RX_OWN;
2041
2042 /* reset error indicator bits */
2043 txdw0 &= ~CP_TX_STATUS_UNF;
2044 txdw0 &= ~CP_TX_STATUS_TES;
2045 txdw0 &= ~CP_TX_STATUS_OWC;
2046 txdw0 &= ~CP_TX_STATUS_LNKF;
2047 txdw0 &= ~CP_TX_STATUS_EXC;
2048
2049 /* update ring data */
2050 val = cpu_to_le32(txdw0);
2051 cpu_physical_memory_write(cplus_tx_ring_desc, (uint8_t *)&val, 4);
4ef1a3d3 2052 /* TODO: implement VLAN tagging support, VLAN tag data is read to txdw1 */
a41b2ff2
PB		 2053// val = cpu_to_le32(txdw1);
2054// cpu_physical_memory_write(cplus_tx_ring_desc+4, &val, 4);
2055
6cadb320
FB		 2056 /* Now decide if descriptor being processed is holding the last segment of packet */
2057 if (txdw0 & CP_TX_LS)
a41b2ff2 2058 {
6cadb320
FB		 2059 DEBUG_PRINT(("RTL8139: +++ C+ Tx mode : descriptor %d is last segment descriptor\n", descriptor));
2060
2061 /* can transfer fully assembled packet */
2062
2063 uint8_t *saved_buffer = s->cplus_txbuffer;
2064 int saved_size = s->cplus_txbuffer_offset;
2065 int saved_buffer_len = s->cplus_txbuffer_len;
2066
2067 /* reset the card space to protect from recursive call */
2068 s->cplus_txbuffer = NULL;
2069 s->cplus_txbuffer_offset = 0;
2070 s->cplus_txbuffer_len = 0;
2071
718da2b9 2072 if (txdw0 & (CP_TX_IPCS | CP_TX_UDPCS | CP_TX_TCPCS | CP_TX_LGSEN))
6cadb320
FB		 2073 {
2074 DEBUG_PRINT(("RTL8139: +++ C+ mode offloaded task checksum\n"));
2075
2076 #define ETH_P_IP 0x0800 /* Internet Protocol packet */
2077 #define ETH_HLEN 14
718da2b9 2078 #define ETH_MTU 1500
6cadb320
FB		 2079
2080 /* ip packet header */
660f11be 2081 ip_header *ip = NULL;
6cadb320 2082 int hlen = 0;
718da2b9
FB		 2083 uint8_t ip_protocol = 0;
2084 uint16_t ip_data_len = 0;
6cadb320 2085
660f11be 2086 uint8_t *eth_payload_data = NULL;
718da2b9 2087 size_t eth_payload_len = 0;
6cadb320 2088
718da2b9 2089 int proto = be16_to_cpu(*(uint16_t *)(saved_buffer + 12));
6cadb320
FB		 2090 if (proto == ETH_P_IP)
2091 {
2092 DEBUG_PRINT(("RTL8139: +++ C+ mode has IP packet\n"));
2093
2094 /* not aligned */
718da2b9
FB		 2095 eth_payload_data = saved_buffer + ETH_HLEN;
2096 eth_payload_len = saved_size - ETH_HLEN;
6cadb320 2097
718da2b9 2098 ip = (ip_header*)eth_payload_data;
6cadb320 2099
718da2b9
FB		 2100 if (IP_HEADER_VERSION(ip) != IP_HEADER_VERSION_4) {
2101 DEBUG_PRINT(("RTL8139: +++ C+ mode packet has bad IP version %d expected %d\n", IP_HEADER_VERSION(ip), IP_HEADER_VERSION_4));
6cadb320
FB		 2102 ip = NULL;
2103 } else {
718da2b9
FB		 2104 hlen = IP_HEADER_LENGTH(ip);
2105 ip_protocol = ip->ip_p;
2106 ip_data_len = be16_to_cpu(ip->ip_len) - hlen;
6cadb320
FB		 2107 }
2108 }
2109
2110 if (ip)
2111 {
2112 if (txdw0 & CP_TX_IPCS)
2113 {
2114 DEBUG_PRINT(("RTL8139: +++ C+ mode need IP checksum\n"));
2115
718da2b9 2116 if (hlen<sizeof(ip_header) || hlen>eth_payload_len) {/* min header length */
6cadb320
FB		 2117 /* bad packet header len */
2118 /* or packet too short */
2119 }
2120 else
2121 {
2122 ip->ip_sum = 0;
718da2b9 2123 ip->ip_sum = ip_checksum(ip, hlen);
6cadb320
FB		 2124 DEBUG_PRINT(("RTL8139: +++ C+ mode IP header len=%d checksum=%04x\n", hlen, ip->ip_sum));
2125 }
2126 }
2127
718da2b9 2128 if ((txdw0 & CP_TX_LGSEN) && ip_protocol == IP_PROTO_TCP)
6cadb320 2129 {
718da2b9
FB		 2130#if defined (DEBUG_RTL8139)
2131 int large_send_mss = (txdw0 >> 16) & CP_TC_LGSEN_MSS_MASK;
2132#endif
2133 DEBUG_PRINT(("RTL8139: +++ C+ mode offloaded task TSO MTU=%d IP data %d frame data %d specified MSS=%d\n",
2134 ETH_MTU, ip_data_len, saved_size - ETH_HLEN, large_send_mss));
6cadb320 2135
718da2b9
FB		 2136 int tcp_send_offset = 0;
2137 int send_count = 0;
6cadb320
FB		 2138
2139 /* maximum IP header length is 60 bytes */
2140 uint8_t saved_ip_header[60];
6cadb320 2141
718da2b9
FB		 2142 /* save IP header template; data area is used in tcp checksum calculation */
2143 memcpy(saved_ip_header, eth_payload_data, hlen);
2144
2145 /* a placeholder for checksum calculation routine in tcp case */
2146 uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
2147 // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
2148
2149 /* pointer to TCP header */
2150 tcp_header *p_tcp_hdr = (tcp_header*)(eth_payload_data + hlen);
2151
2152 int tcp_hlen = TCP_HEADER_DATA_OFFSET(p_tcp_hdr);
2153
2154 /* ETH_MTU = ip header len + tcp header len + payload */
2155 int tcp_data_len = ip_data_len - tcp_hlen;
2156 int tcp_chunk_size = ETH_MTU - hlen - tcp_hlen;
2157
2158 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO IP data len %d TCP hlen %d TCP data len %d TCP chunk size %d\n",
2159 ip_data_len, tcp_hlen, tcp_data_len, tcp_chunk_size));
2160
2161 /* note the cycle below overwrites IP header data,
2162 but restores it from saved_ip_header before sending packet */
2163
2164 int is_last_frame = 0;
2165
2166 for (tcp_send_offset = 0; tcp_send_offset < tcp_data_len; tcp_send_offset += tcp_chunk_size)
2167 {
2168 uint16_t chunk_size = tcp_chunk_size;
2169
2170 /* check if this is the last frame */
2171 if (tcp_send_offset + tcp_chunk_size >= tcp_data_len)
2172 {
2173 is_last_frame = 1;
2174 chunk_size = tcp_data_len - tcp_send_offset;
2175 }
2176
2177 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO TCP seqno %08x\n", be32_to_cpu(p_tcp_hdr->th_seq)));
2178
2179 /* add 4 TCP pseudoheader fields */
2180 /* copy IP source and destination fields */
2181 memcpy(data_to_checksum, saved_ip_header + 12, 8);
2182
2183 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO calculating TCP checksum for packet with %d bytes data\n", tcp_hlen + chunk_size));
2184
2185 if (tcp_send_offset)
2186 {
2187 memcpy((uint8_t*)p_tcp_hdr + tcp_hlen, (uint8_t*)p_tcp_hdr + tcp_hlen + tcp_send_offset, chunk_size);
2188 }
2189
2190 /* keep PUSH and FIN flags only for the last frame */
2191 if (!is_last_frame)
2192 {
2193 TCP_HEADER_CLEAR_FLAGS(p_tcp_hdr, TCP_FLAG_PUSH|TCP_FLAG_FIN);
2194 }
6cadb320 2195
718da2b9
FB		 2196 /* recalculate TCP checksum */
2197 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum;
2198 p_tcpip_hdr->zeros = 0;
2199 p_tcpip_hdr->ip_proto = IP_PROTO_TCP;
2200 p_tcpip_hdr->ip_payload = cpu_to_be16(tcp_hlen + chunk_size);
2201
2202 p_tcp_hdr->th_sum = 0;
2203
2204 int tcp_checksum = ip_checksum(data_to_checksum, tcp_hlen + chunk_size + 12);
2205 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO TCP checksum %04x\n", tcp_checksum));
2206
2207 p_tcp_hdr->th_sum = tcp_checksum;
2208
2209 /* restore IP header */
2210 memcpy(eth_payload_data, saved_ip_header, hlen);
2211
2212 /* set IP data length and recalculate IP checksum */
2213 ip->ip_len = cpu_to_be16(hlen + tcp_hlen + chunk_size);
2214
2215 /* increment IP id for subsequent frames */
2216 ip->ip_id = cpu_to_be16(tcp_send_offset/tcp_chunk_size + be16_to_cpu(ip->ip_id));
2217
2218 ip->ip_sum = 0;
2219 ip->ip_sum = ip_checksum(eth_payload_data, hlen);
2220 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO IP header len=%d checksum=%04x\n", hlen, ip->ip_sum));
2221
2222 int tso_send_size = ETH_HLEN + hlen + tcp_hlen + chunk_size;
2223 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO transferring packet size %d\n", tso_send_size));
2224 rtl8139_transfer_frame(s, saved_buffer, tso_send_size, 0);
2225
2226 /* add transferred count to TCP sequence number */
2227 p_tcp_hdr->th_seq = cpu_to_be32(chunk_size + be32_to_cpu(p_tcp_hdr->th_seq));
2228 ++send_count;
2229 }
2230
2231 /* Stop sending this frame */
2232 saved_size = 0;
2233 }
2234 else if (txdw0 & (CP_TX_TCPCS|CP_TX_UDPCS))
2235 {
2236 DEBUG_PRINT(("RTL8139: +++ C+ mode need TCP or UDP checksum\n"));
2237
2238 /* maximum IP header length is 60 bytes */
2239 uint8_t saved_ip_header[60];
2240 memcpy(saved_ip_header, eth_payload_data, hlen);
2241
2242 uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
2243 // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
6cadb320
FB		 2244
2245 /* add 4 TCP pseudoheader fields */
2246 /* copy IP source and destination fields */
718da2b9 2247 memcpy(data_to_checksum, saved_ip_header + 12, 8);
6cadb320 2248
718da2b9 2249 if ((txdw0 & CP_TX_TCPCS) && ip_protocol == IP_PROTO_TCP)
6cadb320
FB		 2250 {
2251 DEBUG_PRINT(("RTL8139: +++ C+ mode calculating TCP checksum for packet with %d bytes data\n", ip_data_len));
2252
718da2b9
FB		 2253 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum;
2254 p_tcpip_hdr->zeros = 0;
2255 p_tcpip_hdr->ip_proto = IP_PROTO_TCP;
2256 p_tcpip_hdr->ip_payload = cpu_to_be16(ip_data_len);
6cadb320 2257
718da2b9 2258 tcp_header* p_tcp_hdr = (tcp_header *) (data_to_checksum+12);
6cadb320
FB		 2259
2260 p_tcp_hdr->th_sum = 0;
2261
718da2b9 2262 int tcp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
6cadb320
FB		 2263 DEBUG_PRINT(("RTL8139: +++ C+ mode TCP checksum %04x\n", tcp_checksum));
2264
2265 p_tcp_hdr->th_sum = tcp_checksum;
2266 }
718da2b9 2267 else if ((txdw0 & CP_TX_UDPCS) && ip_protocol == IP_PROTO_UDP)
6cadb320
FB		 2268 {
2269 DEBUG_PRINT(("RTL8139: +++ C+ mode calculating UDP checksum for packet with %d bytes data\n", ip_data_len));
2270
718da2b9
FB		 2271 ip_pseudo_header *p_udpip_hdr = (ip_pseudo_header *)data_to_checksum;
2272 p_udpip_hdr->zeros = 0;
2273 p_udpip_hdr->ip_proto = IP_PROTO_UDP;
2274 p_udpip_hdr->ip_payload = cpu_to_be16(ip_data_len);
6cadb320 2275
718da2b9 2276 udp_header *p_udp_hdr = (udp_header *) (data_to_checksum+12);
6cadb320 2277
6cadb320
FB		 2278 p_udp_hdr->uh_sum = 0;
2279
718da2b9 2280 int udp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
6cadb320
FB		 2281 DEBUG_PRINT(("RTL8139: +++ C+ mode UDP checksum %04x\n", udp_checksum));
2282
6cadb320
FB		 2283 p_udp_hdr->uh_sum = udp_checksum;
2284 }
2285
2286 /* restore IP header */
718da2b9 2287 memcpy(eth_payload_data, saved_ip_header, hlen);
6cadb320
FB		 2288 }
2289 }
2290 }
2291
2292 /* update tally counter */
2293 ++s->tally_counters.TxOk;
2294
2295 DEBUG_PRINT(("RTL8139: +++ C+ mode transmitting %d bytes packet\n", saved_size));
2296
718da2b9 2297 rtl8139_transfer_frame(s, saved_buffer, saved_size, 1);
6cadb320
FB		 2298
2299 /* restore card space if there was no recursion and reset offset */
2300 if (!s->cplus_txbuffer)
2301 {
2302 s->cplus_txbuffer = saved_buffer;
2303 s->cplus_txbuffer_len = saved_buffer_len;
2304 s->cplus_txbuffer_offset = 0;
2305 }
2306 else
2307 {
2bc6f59b 2308 qemu_free(saved_buffer);
6cadb320 2309 }
a41b2ff2
PB		 2310 }
2311 else
2312 {
6cadb320 2313 DEBUG_PRINT(("RTL8139: +++ C+ mode transmission continue to next descriptor\n"));
a41b2ff2
PB		 2314 }
2315
a41b2ff2
PB		 2316 return 1;
2317}
2318
2319static void rtl8139_cplus_transmit(RTL8139State *s)
2320{
2321 int txcount = 0;
2322
2323 while (rtl8139_cplus_transmit_one(s))
2324 {
2325 ++txcount;
2326 }
2327
2328 /* Mark transfer completed */
2329 if (!txcount)
2330 {
6cadb320
FB		 2331 DEBUG_PRINT(("RTL8139: C+ mode : transmitter queue stalled, current TxDesc = %d\n",
2332 s->currCPlusTxDesc));
a41b2ff2
PB		 2333 }
2334 else
2335 {
2336 /* update interrupt status */
2337 s->IntrStatus |= TxOK;
2338 rtl8139_update_irq(s);
2339 }
2340}
2341
2342static void rtl8139_transmit(RTL8139State *s)
2343{
2344 int descriptor = s->currTxDesc, txcount = 0;
2345
2346 /*while*/
2347 if (rtl8139_transmit_one(s, descriptor))
2348 {
2349 ++s->currTxDesc;
2350 s->currTxDesc %= 4;
2351 ++txcount;
2352 }
2353
2354 /* Mark transfer completed */
2355 if (!txcount)
2356 {
6cadb320 2357 DEBUG_PRINT(("RTL8139: transmitter queue stalled, current TxDesc = %d\n", s->currTxDesc));
a41b2ff2
PB		 2358 }
2359}
2360
2361static void rtl8139_TxStatus_write(RTL8139State *s, uint32_t txRegOffset, uint32_t val)
2362{
2363
2364 int descriptor = txRegOffset/4;
6cadb320
FB		 2365
2366 /* handle C+ transmit mode register configuration */
2367
2c3891ab 2368 if (s->cplus_enabled)
6cadb320
FB		 2369 {
2370 DEBUG_PRINT(("RTL8139C+ DTCCR write offset=0x%x val=0x%08x descriptor=%d\n", txRegOffset, val, descriptor));
2371
2372 /* handle Dump Tally Counters command */
2373 s->TxStatus[descriptor] = val;
2374
2375 if (descriptor == 0 && (val & 0x8))
2376 {
c227f099 2377 target_phys_addr_t tc_addr = rtl8139_addr64(s->TxStatus[0] & ~0x3f, s->TxStatus[1]);
6cadb320
FB		 2378
2379 /* dump tally counters to specified memory location */
2380 RTL8139TallyCounters_physical_memory_write( tc_addr, &s->tally_counters);
2381
2382 /* mark dump completed */
2383 s->TxStatus[0] &= ~0x8;
2384 }
2385
2386 return;
2387 }
2388
2389 DEBUG_PRINT(("RTL8139: TxStatus write offset=0x%x val=0x%08x descriptor=%d\n", txRegOffset, val, descriptor));
a41b2ff2
PB		 2390
2391 /* mask only reserved bits */
2392 val &= ~0xff00c000; /* these bits are reset on write */
2393 val = SET_MASKED(val, 0x00c00000, s->TxStatus[descriptor]);
2394
2395 s->TxStatus[descriptor] = val;
2396
2397 /* attempt to start transmission */
2398 rtl8139_transmit(s);
2399}
2400
2401static uint32_t rtl8139_TxStatus_read(RTL8139State *s, uint32_t txRegOffset)
2402{
2403 uint32_t ret = s->TxStatus[txRegOffset/4];
2404
6cadb320 2405 DEBUG_PRINT(("RTL8139: TxStatus read offset=0x%x val=0x%08x\n", txRegOffset, ret));
a41b2ff2
PB		 2406
2407 return ret;
2408}
2409
2410static uint16_t rtl8139_TSAD_read(RTL8139State *s)
2411{
2412 uint16_t ret = 0;
2413
2414 /* Simulate TSAD, it is read only anyway */
2415
2416 ret = ((s->TxStatus[3] & TxStatOK )?TSAD_TOK3:0)
2417 |((s->TxStatus[2] & TxStatOK )?TSAD_TOK2:0)
2418 |((s->TxStatus[1] & TxStatOK )?TSAD_TOK1:0)
2419 |((s->TxStatus[0] & TxStatOK )?TSAD_TOK0:0)
2420
2421 |((s->TxStatus[3] & TxUnderrun)?TSAD_TUN3:0)
2422 |((s->TxStatus[2] & TxUnderrun)?TSAD_TUN2:0)
2423 |((s->TxStatus[1] & TxUnderrun)?TSAD_TUN1:0)
2424 |((s->TxStatus[0] & TxUnderrun)?TSAD_TUN0:0)
3b46e624 2425
a41b2ff2
PB		 2426 |((s->TxStatus[3] & TxAborted )?TSAD_TABT3:0)
2427 |((s->TxStatus[2] & TxAborted )?TSAD_TABT2:0)
2428 |((s->TxStatus[1] & TxAborted )?TSAD_TABT1:0)
2429 |((s->TxStatus[0] & TxAborted )?TSAD_TABT0:0)
3b46e624 2430
a41b2ff2
PB		 2431 |((s->TxStatus[3] & TxHostOwns )?TSAD_OWN3:0)
2432 |((s->TxStatus[2] & TxHostOwns )?TSAD_OWN2:0)
2433 |((s->TxStatus[1] & TxHostOwns )?TSAD_OWN1:0)
2434 |((s->TxStatus[0] & TxHostOwns )?TSAD_OWN0:0) ;
3b46e624 2435
a41b2ff2 2436
6cadb320 2437 DEBUG_PRINT(("RTL8139: TSAD read val=0x%04x\n", ret));
a41b2ff2
PB		 2438
2439 return ret;
2440}
2441
2442static uint16_t rtl8139_CSCR_read(RTL8139State *s)
2443{
2444 uint16_t ret = s->CSCR;
2445
6cadb320 2446 DEBUG_PRINT(("RTL8139: CSCR read val=0x%04x\n", ret));
a41b2ff2
PB		 2447
2448 return ret;
2449}
2450
2451static void rtl8139_TxAddr_write(RTL8139State *s, uint32_t txAddrOffset, uint32_t val)
2452{
6cadb320 2453 DEBUG_PRINT(("RTL8139: TxAddr write offset=0x%x val=0x%08x\n", txAddrOffset, val));
a41b2ff2 2454
290a0933 2455 s->TxAddr[txAddrOffset/4] = val;
a41b2ff2
PB		 2456}
2457
2458static uint32_t rtl8139_TxAddr_read(RTL8139State *s, uint32_t txAddrOffset)
2459{
290a0933 2460 uint32_t ret = s->TxAddr[txAddrOffset/4];
a41b2ff2 2461
6cadb320 2462 DEBUG_PRINT(("RTL8139: TxAddr read offset=0x%x val=0x%08x\n", txAddrOffset, ret));
a41b2ff2
PB		 2463
2464 return ret;
2465}
2466
2467static void rtl8139_RxBufPtr_write(RTL8139State *s, uint32_t val)
2468{
6cadb320 2469 DEBUG_PRINT(("RTL8139: RxBufPtr write val=0x%04x\n", val));
a41b2ff2
PB		 2470
2471 /* this value is off by 16 */
2472 s->RxBufPtr = MOD2(val + 0x10, s->RxBufferSize);
2473
6cadb320
FB		 2474 DEBUG_PRINT((" CAPR write: rx buffer length %d head 0x%04x read 0x%04x\n",
2475 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr));
a41b2ff2
PB		 2476}
2477
2478static uint32_t rtl8139_RxBufPtr_read(RTL8139State *s)
2479{
2480 /* this value is off by 16 */
2481 uint32_t ret = s->RxBufPtr - 0x10;
2482
6cadb320
FB		 2483 DEBUG_PRINT(("RTL8139: RxBufPtr read val=0x%04x\n", ret));
2484
2485 return ret;
2486}
2487
2488static uint32_t rtl8139_RxBufAddr_read(RTL8139State *s)
2489{
2490 /* this value is NOT off by 16 */
2491 uint32_t ret = s->RxBufAddr;
2492
2493 DEBUG_PRINT(("RTL8139: RxBufAddr read val=0x%04x\n", ret));
a41b2ff2
PB		 2494
2495 return ret;
2496}
2497
2498static void rtl8139_RxBuf_write(RTL8139State *s, uint32_t val)
2499{
6cadb320 2500 DEBUG_PRINT(("RTL8139: RxBuf write val=0x%08x\n", val));
a41b2ff2
PB		 2501
2502 s->RxBuf = val;
2503
2504 /* may need to reset rxring here */
2505}
2506
2507static uint32_t rtl8139_RxBuf_read(RTL8139State *s)
2508{
2509 uint32_t ret = s->RxBuf;
2510
6cadb320 2511 DEBUG_PRINT(("RTL8139: RxBuf read val=0x%08x\n", ret));
a41b2ff2
PB		 2512
2513 return ret;
2514}
2515
2516static void rtl8139_IntrMask_write(RTL8139State *s, uint32_t val)
2517{
6cadb320 2518 DEBUG_PRINT(("RTL8139: IntrMask write(w) val=0x%04x\n", val));
a41b2ff2
PB		 2519
2520 /* mask unwriteable bits */
2521 val = SET_MASKED(val, 0x1e00, s->IntrMask);
2522
2523 s->IntrMask = val;
2524
2525 rtl8139_update_irq(s);
2526}
2527
2528static uint32_t rtl8139_IntrMask_read(RTL8139State *s)
2529{
2530 uint32_t ret = s->IntrMask;
2531
6cadb320 2532 DEBUG_PRINT(("RTL8139: IntrMask read(w) val=0x%04x\n", ret));
a41b2ff2
PB		 2533
2534 return ret;
2535}
2536
2537static void rtl8139_IntrStatus_write(RTL8139State *s, uint32_t val)
2538{
6cadb320 2539 DEBUG_PRINT(("RTL8139: IntrStatus write(w) val=0x%04x\n", val));
a41b2ff2
PB		 2540
2541#if 0
2542
2543 /* writing to ISR has no effect */
2544
2545 return;
2546
2547#else
2548 uint16_t newStatus = s->IntrStatus & ~val;
2549
2550 /* mask unwriteable bits */
2551 newStatus = SET_MASKED(newStatus, 0x1e00, s->IntrStatus);
2552
2553 /* writing 1 to interrupt status register bit clears it */
2554 s->IntrStatus = 0;
2555 rtl8139_update_irq(s);
2556
2557 s->IntrStatus = newStatus;
2558 rtl8139_update_irq(s);
2559#endif
2560}
2561
2562static uint32_t rtl8139_IntrStatus_read(RTL8139State *s)
2563{
2564 uint32_t ret = s->IntrStatus;
2565
6cadb320 2566 DEBUG_PRINT(("RTL8139: IntrStatus read(w) val=0x%04x\n", ret));
a41b2ff2
PB		 2567
2568#if 0
2569
2570 /* reading ISR clears all interrupts */
2571 s->IntrStatus = 0;
2572
2573 rtl8139_update_irq(s);
2574
2575#endif
2576
2577 return ret;
2578}
2579
2580static void rtl8139_MultiIntr_write(RTL8139State *s, uint32_t val)
2581{
6cadb320 2582 DEBUG_PRINT(("RTL8139: MultiIntr write(w) val=0x%04x\n", val));
a41b2ff2
PB		 2583
2584 /* mask unwriteable bits */
2585 val = SET_MASKED(val, 0xf000, s->MultiIntr);
2586
2587 s->MultiIntr = val;
2588}
2589
2590static uint32_t rtl8139_MultiIntr_read(RTL8139State *s)
2591{
2592 uint32_t ret = s->MultiIntr;
2593
6cadb320 2594 DEBUG_PRINT(("RTL8139: MultiIntr read(w) val=0x%04x\n", ret));
a41b2ff2
PB		 2595
2596 return ret;
2597}
2598
2599static void rtl8139_io_writeb(void *opaque, uint8_t addr, uint32_t val)
2600{
2601 RTL8139State *s = opaque;
2602
2603 addr &= 0xff;
2604
2605 switch (addr)
2606 {
2607 case MAC0 ... MAC0+5:
2608 s->phys[addr - MAC0] = val;
2609 break;
2610 case MAC0+6 ... MAC0+7:
2611 /* reserved */
2612 break;
2613 case MAR0 ... MAR0+7:
2614 s->mult[addr - MAR0] = val;
2615 break;
2616 case ChipCmd:
2617 rtl8139_ChipCmd_write(s, val);
2618 break;
2619 case Cfg9346:
2620 rtl8139_Cfg9346_write(s, val);
2621 break;
2622 case TxConfig: /* windows driver sometimes writes using byte-lenth call */
2623 rtl8139_TxConfig_writeb(s, val);
2624 break;
2625 case Config0:
2626 rtl8139_Config0_write(s, val);
2627 break;
2628 case Config1:
2629 rtl8139_Config1_write(s, val);
2630 break;
2631 case Config3:
2632 rtl8139_Config3_write(s, val);
2633 break;
2634 case Config4:
2635 rtl8139_Config4_write(s, val);
2636 break;
2637 case Config5:
2638 rtl8139_Config5_write(s, val);
2639 break;
2640 case MediaStatus:
2641 /* ignore */
6cadb320 2642 DEBUG_PRINT(("RTL8139: not implemented write(b) to MediaStatus val=0x%02x\n", val));
a41b2ff2
PB		 2643 break;
2644
2645 case HltClk:
6cadb320 2646 DEBUG_PRINT(("RTL8139: HltClk write val=0x%08x\n", val));
a41b2ff2
PB		 2647 if (val == 'R')
2648 {
2649 s->clock_enabled = 1;
2650 }
2651 else if (val == 'H')
2652 {
2653 s->clock_enabled = 0;
2654 }
2655 break;
2656
2657 case TxThresh:
6cadb320 2658 DEBUG_PRINT(("RTL8139C+ TxThresh write(b) val=0x%02x\n", val));
a41b2ff2
PB		 2659 s->TxThresh = val;
2660 break;
2661
2662 case TxPoll:
6cadb320 2663 DEBUG_PRINT(("RTL8139C+ TxPoll write(b) val=0x%02x\n", val));
a41b2ff2
PB		 2664 if (val & (1 << 7))
2665 {
6cadb320 2666 DEBUG_PRINT(("RTL8139C+ TxPoll high priority transmission (not implemented)\n"));
a41b2ff2
PB		 2667 //rtl8139_cplus_transmit(s);
2668 }
2669 if (val & (1 << 6))
2670 {
6cadb320 2671 DEBUG_PRINT(("RTL8139C+ TxPoll normal priority transmission\n"));
a41b2ff2
PB		 2672 rtl8139_cplus_transmit(s);
2673 }
2674
2675 break;
2676
2677 default:
6cadb320 2678 DEBUG_PRINT(("RTL8139: not implemented write(b) addr=0x%x val=0x%02x\n", addr, val));
a41b2ff2
PB		 2679 break;
2680 }
2681}
2682
2683static void rtl8139_io_writew(void *opaque, uint8_t addr, uint32_t val)
2684{
2685 RTL8139State *s = opaque;
2686
2687 addr &= 0xfe;
2688
2689 switch (addr)
2690 {
2691 case IntrMask:
2692 rtl8139_IntrMask_write(s, val);
2693 break;
2694
2695 case IntrStatus:
2696 rtl8139_IntrStatus_write(s, val);
2697 break;
2698
2699 case MultiIntr:
2700 rtl8139_MultiIntr_write(s, val);
2701 break;
2702
2703 case RxBufPtr:
2704 rtl8139_RxBufPtr_write(s, val);
2705 break;
2706
2707 case BasicModeCtrl:
2708 rtl8139_BasicModeCtrl_write(s, val);
2709 break;
2710 case BasicModeStatus:
2711 rtl8139_BasicModeStatus_write(s, val);
2712 break;
2713 case NWayAdvert:
6cadb320 2714 DEBUG_PRINT(("RTL8139: NWayAdvert write(w) val=0x%04x\n", val));
a41b2ff2
PB		 2715 s->NWayAdvert = val;
2716 break;
2717 case NWayLPAR:
6cadb320 2718 DEBUG_PRINT(("RTL8139: forbidden NWayLPAR write(w) val=0x%04x\n", val));
a41b2ff2
PB		 2719 break;
2720 case NWayExpansion:
6cadb320 2721 DEBUG_PRINT(("RTL8139: NWayExpansion write(w) val=0x%04x\n", val));
a41b2ff2
PB		 2722 s->NWayExpansion = val;
2723 break;
2724
2725 case CpCmd:
2726 rtl8139_CpCmd_write(s, val);
2727 break;
2728
6cadb320
FB		 2729 case IntrMitigate:
2730 rtl8139_IntrMitigate_write(s, val);
2731 break;
2732
a41b2ff2 2733 default:
6cadb320 2734 DEBUG_PRINT(("RTL8139: ioport write(w) addr=0x%x val=0x%04x via write(b)\n", addr, val));
a41b2ff2 2735
a41b2ff2
PB		 2736 rtl8139_io_writeb(opaque, addr, val & 0xff);
2737 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
a41b2ff2
PB		 2738 break;
2739 }
2740}
2741
2742static void rtl8139_io_writel(void *opaque, uint8_t addr, uint32_t val)
2743{
2744 RTL8139State *s = opaque;
2745
2746 addr &= 0xfc;
2747
2748 switch (addr)
2749 {
2750 case RxMissed:
6cadb320 2751 DEBUG_PRINT(("RTL8139: RxMissed clearing on write\n"));
a41b2ff2
PB		 2752 s->RxMissed = 0;
2753 break;
2754
2755 case TxConfig:
2756 rtl8139_TxConfig_write(s, val);
2757 break;
2758
2759 case RxConfig:
2760 rtl8139_RxConfig_write(s, val);
2761 break;
2762
2763 case TxStatus0 ... TxStatus0+4*4-1:
2764 rtl8139_TxStatus_write(s, addr-TxStatus0, val);
2765 break;
2766
2767 case TxAddr0 ... TxAddr0+4*4-1:
2768 rtl8139_TxAddr_write(s, addr-TxAddr0, val);
2769 break;
2770
2771 case RxBuf:
2772 rtl8139_RxBuf_write(s, val);
2773 break;
2774
2775 case RxRingAddrLO:
6cadb320 2776 DEBUG_PRINT(("RTL8139: C+ RxRing low bits write val=0x%08x\n", val));
a41b2ff2
PB		 2777 s->RxRingAddrLO = val;
2778 break;
2779
2780 case RxRingAddrHI:
6cadb320 2781 DEBUG_PRINT(("RTL8139: C+ RxRing high bits write val=0x%08x\n", val));
a41b2ff2
PB		 2782 s->RxRingAddrHI = val;
2783 break;
2784
6cadb320
FB		 2785 case Timer:
2786 DEBUG_PRINT(("RTL8139: TCTR Timer reset on write\n"));
2787 s->TCTR = 0;
2788 s->TCTR_base = qemu_get_clock(vm_clock);
2789 break;
2790
2791 case FlashReg:
2792 DEBUG_PRINT(("RTL8139: FlashReg TimerInt write val=0x%08x\n", val));
2793 s->TimerInt = val;
2794 break;
2795
a41b2ff2 2796 default:
6cadb320 2797 DEBUG_PRINT(("RTL8139: ioport write(l) addr=0x%x val=0x%08x via write(b)\n", addr, val));
a41b2ff2
PB		 2798 rtl8139_io_writeb(opaque, addr, val & 0xff);
2799 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2800 rtl8139_io_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2801 rtl8139_io_writeb(opaque, addr + 3, (val >> 24) & 0xff);
a41b2ff2
PB		 2802 break;
2803 }
2804}
2805
2806static uint32_t rtl8139_io_readb(void *opaque, uint8_t addr)
2807{
2808 RTL8139State *s = opaque;
2809 int ret;
2810
2811 addr &= 0xff;
2812
2813 switch (addr)
2814 {
2815 case MAC0 ... MAC0+5:
2816 ret = s->phys[addr - MAC0];
2817 break;
2818 case MAC0+6 ... MAC0+7:
2819 ret = 0;
2820 break;
2821 case MAR0 ... MAR0+7:
2822 ret = s->mult[addr - MAR0];
2823 break;
2824 case ChipCmd:
2825 ret = rtl8139_ChipCmd_read(s);
2826 break;
2827 case Cfg9346:
2828 ret = rtl8139_Cfg9346_read(s);
2829 break;
2830 case Config0:
2831 ret = rtl8139_Config0_read(s);
2832 break;
2833 case Config1:
2834 ret = rtl8139_Config1_read(s);
2835 break;
2836 case Config3:
2837 ret = rtl8139_Config3_read(s);
2838 break;
2839 case Config4:
2840 ret = rtl8139_Config4_read(s);
2841 break;
2842 case Config5:
2843 ret = rtl8139_Config5_read(s);
2844 break;
2845
2846 case MediaStatus:
2847 ret = 0xd0;
6cadb320 2848 DEBUG_PRINT(("RTL8139: MediaStatus read 0x%x\n", ret));
a41b2ff2
PB		 2849 break;
2850
2851 case HltClk:
2852 ret = s->clock_enabled;
6cadb320 2853 DEBUG_PRINT(("RTL8139: HltClk read 0x%x\n", ret));
a41b2ff2
PB		 2854 break;
2855
2856 case PCIRevisionID:
6cadb320
FB		 2857 ret = RTL8139_PCI_REVID;
2858 DEBUG_PRINT(("RTL8139: PCI Revision ID read 0x%x\n", ret));
a41b2ff2
PB		 2859 break;
2860
2861 case TxThresh:
2862 ret = s->TxThresh;
6cadb320 2863 DEBUG_PRINT(("RTL8139C+ TxThresh read(b) val=0x%02x\n", ret));
a41b2ff2
PB		 2864 break;
2865
2866 case 0x43: /* Part of TxConfig register. Windows driver tries to read it */
2867 ret = s->TxConfig >> 24;
6cadb320 2868 DEBUG_PRINT(("RTL8139C TxConfig at 0x43 read(b) val=0x%02x\n", ret));
a41b2ff2
PB		 2869 break;
2870
2871 default:
6cadb320 2872 DEBUG_PRINT(("RTL8139: not implemented read(b) addr=0x%x\n", addr));
a41b2ff2
PB		 2873 ret = 0;
2874 break;
2875 }
2876
2877 return ret;
2878}
2879
2880static uint32_t rtl8139_io_readw(void *opaque, uint8_t addr)
2881{
2882 RTL8139State *s = opaque;
2883 uint32_t ret;
2884
2885 addr &= 0xfe; /* mask lower bit */
2886
2887 switch (addr)
2888 {
2889 case IntrMask:
2890 ret = rtl8139_IntrMask_read(s);
2891 break;
2892
2893 case IntrStatus:
2894 ret = rtl8139_IntrStatus_read(s);
2895 break;
2896
2897 case MultiIntr:
2898 ret = rtl8139_MultiIntr_read(s);
2899 break;
2900
2901 case RxBufPtr:
2902 ret = rtl8139_RxBufPtr_read(s);
2903 break;
2904
6cadb320
FB		 2905 case RxBufAddr:
2906 ret = rtl8139_RxBufAddr_read(s);
2907 break;
2908
a41b2ff2
PB		 2909 case BasicModeCtrl:
2910 ret = rtl8139_BasicModeCtrl_read(s);
2911 break;
2912 case BasicModeStatus:
2913 ret = rtl8139_BasicModeStatus_read(s);
2914 break;
2915 case NWayAdvert:
2916 ret = s->NWayAdvert;
6cadb320 2917 DEBUG_PRINT(("RTL8139: NWayAdvert read(w) val=0x%04x\n", ret));
a41b2ff2
PB		 2918 break;
2919 case NWayLPAR:
2920 ret = s->NWayLPAR;
6cadb320 2921 DEBUG_PRINT(("RTL8139: NWayLPAR read(w) val=0x%04x\n", ret));
a41b2ff2
PB		 2922 break;
2923 case NWayExpansion:
2924 ret = s->NWayExpansion;
6cadb320 2925 DEBUG_PRINT(("RTL8139: NWayExpansion read(w) val=0x%04x\n", ret));
a41b2ff2
PB		 2926 break;
2927
2928 case CpCmd:
2929 ret = rtl8139_CpCmd_read(s);
2930 break;
2931
6cadb320
FB		 2932 case IntrMitigate:
2933 ret = rtl8139_IntrMitigate_read(s);
2934 break;
2935
a41b2ff2
PB		 2936 case TxSummary:
2937 ret = rtl8139_TSAD_read(s);
2938 break;
2939
2940 case CSCR:
2941 ret = rtl8139_CSCR_read(s);
2942 break;
2943
2944 default:
6cadb320 2945 DEBUG_PRINT(("RTL8139: ioport read(w) addr=0x%x via read(b)\n", addr));
a41b2ff2 2946
a41b2ff2
PB		 2947 ret = rtl8139_io_readb(opaque, addr);
2948 ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
a41b2ff2 2949
6cadb320 2950 DEBUG_PRINT(("RTL8139: ioport read(w) addr=0x%x val=0x%04x\n", addr, ret));
a41b2ff2
PB		 2951 break;
2952 }
2953
2954 return ret;
2955}
2956
2957static uint32_t rtl8139_io_readl(void *opaque, uint8_t addr)
2958{
2959 RTL8139State *s = opaque;
2960 uint32_t ret;
2961
2962 addr &= 0xfc; /* also mask low 2 bits */
2963
2964 switch (addr)
2965 {
2966 case RxMissed:
2967 ret = s->RxMissed;
2968
6cadb320 2969 DEBUG_PRINT(("RTL8139: RxMissed read val=0x%08x\n", ret));
a41b2ff2
PB		 2970 break;
2971
2972 case TxConfig:
2973 ret = rtl8139_TxConfig_read(s);
2974 break;
2975
2976 case RxConfig:
2977 ret = rtl8139_RxConfig_read(s);
2978 break;
2979
2980 case TxStatus0 ... TxStatus0+4*4-1:
2981 ret = rtl8139_TxStatus_read(s, addr-TxStatus0);
2982 break;
2983
2984 case TxAddr0 ... TxAddr0+4*4-1:
2985 ret = rtl8139_TxAddr_read(s, addr-TxAddr0);
2986 break;
2987
2988 case RxBuf:
2989 ret = rtl8139_RxBuf_read(s);
2990 break;
2991
2992 case RxRingAddrLO:
2993 ret = s->RxRingAddrLO;
6cadb320 2994 DEBUG_PRINT(("RTL8139: C+ RxRing low bits read val=0x%08x\n", ret));
a41b2ff2
PB		 2995 break;
2996
2997 case RxRingAddrHI:
2998 ret = s->RxRingAddrHI;
6cadb320
FB		 2999 DEBUG_PRINT(("RTL8139: C+ RxRing high bits read val=0x%08x\n", ret));
3000 break;
3001
3002 case Timer:
3003 ret = s->TCTR;
3004 DEBUG_PRINT(("RTL8139: TCTR Timer read val=0x%08x\n", ret));
3005 break;
3006
3007 case FlashReg:
3008 ret = s->TimerInt;
3009 DEBUG_PRINT(("RTL8139: FlashReg TimerInt read val=0x%08x\n", ret));
a41b2ff2
PB		 3010 break;
3011
3012 default:
6cadb320 3013 DEBUG_PRINT(("RTL8139: ioport read(l) addr=0x%x via read(b)\n", addr));
a41b2ff2 3014
a41b2ff2
PB		 3015 ret = rtl8139_io_readb(opaque, addr);
3016 ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
3017 ret |= rtl8139_io_readb(opaque, addr + 2) << 16;
3018 ret |= rtl8139_io_readb(opaque, addr + 3) << 24;
a41b2ff2 3019
6cadb320 3020 DEBUG_PRINT(("RTL8139: read(l) addr=0x%x val=%08x\n", addr, ret));
a41b2ff2
PB		 3021 break;
3022 }
3023
3024 return ret;
3025}
3026
3027/* */
3028
3029static void rtl8139_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
3030{
3031 rtl8139_io_writeb(opaque, addr & 0xFF, val);
3032}
3033
3034static void rtl8139_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
3035{
3036 rtl8139_io_writew(opaque, addr & 0xFF, val);
3037}
3038
3039static void rtl8139_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
3040{
3041 rtl8139_io_writel(opaque, addr & 0xFF, val);
3042}
3043
3044static uint32_t rtl8139_ioport_readb(void *opaque, uint32_t addr)
3045{
3046 return rtl8139_io_readb(opaque, addr & 0xFF);
3047}
3048
3049static uint32_t rtl8139_ioport_readw(void *opaque, uint32_t addr)
3050{
3051 return rtl8139_io_readw(opaque, addr & 0xFF);
3052}
3053
3054static uint32_t rtl8139_ioport_readl(void *opaque, uint32_t addr)
3055{
3056 return rtl8139_io_readl(opaque, addr & 0xFF);
3057}
3058
3059/* */
3060
c227f099 3061static void rtl8139_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
a41b2ff2
PB		 3062{
3063 rtl8139_io_writeb(opaque, addr & 0xFF, val);
3064}
3065
c227f099 3066static void rtl8139_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
a41b2ff2 3067{
5fedc612
AJ		 3068#ifdef TARGET_WORDS_BIGENDIAN
3069 val = bswap16(val);
3070#endif
a41b2ff2
PB		 3071 rtl8139_io_writew(opaque, addr & 0xFF, val);
3072}
3073
c227f099 3074static void rtl8139_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
a41b2ff2 3075{
5fedc612
AJ		 3076#ifdef TARGET_WORDS_BIGENDIAN
3077 val = bswap32(val);
3078#endif
a41b2ff2
PB		 3079 rtl8139_io_writel(opaque, addr & 0xFF, val);
3080}
3081
c227f099 3082static uint32_t rtl8139_mmio_readb(void *opaque, target_phys_addr_t addr)
a41b2ff2
PB		 3083{
3084 return rtl8139_io_readb(opaque, addr & 0xFF);
3085}
3086
c227f099 3087static uint32_t rtl8139_mmio_readw(void *opaque, target_phys_addr_t addr)
a41b2ff2 3088{
5fedc612
AJ		 3089 uint32_t val = rtl8139_io_readw(opaque, addr & 0xFF);
3090#ifdef TARGET_WORDS_BIGENDIAN
3091 val = bswap16(val);
3092#endif
3093 return val;
a41b2ff2
PB		 3094}
3095
c227f099 3096static uint32_t rtl8139_mmio_readl(void *opaque, target_phys_addr_t addr)
a41b2ff2 3097{
5fedc612
AJ		 3098 uint32_t val = rtl8139_io_readl(opaque, addr & 0xFF);
3099#ifdef TARGET_WORDS_BIGENDIAN
3100 val = bswap32(val);
3101#endif
3102 return val;
a41b2ff2
PB		 3103}
3104
060110c3 3105static int rtl8139_post_load(void *opaque, int version_id)
a41b2ff2 3106{
6597ebbb 3107 RTL8139State* s = opaque;
060110c3 3108 if (version_id < 4) {
2c3891ab
AL		 3109 s->cplus_enabled = s->CpCmd != 0;
3110 }
3111
a41b2ff2
PB		 3112 return 0;
3113}
3114
060110c3
JQ		 3115static const VMStateDescription vmstate_rtl8139 = {
3116 .name = "rtl8139",
3117 .version_id = 4,
3118 .minimum_version_id = 3,
3119 .minimum_version_id_old = 3,
3120 .post_load = rtl8139_post_load,
3121 .fields = (VMStateField []) {
3122 VMSTATE_PCI_DEVICE(dev, RTL8139State),
3123 VMSTATE_PARTIAL_BUFFER(phys, RTL8139State, 6),
3124 VMSTATE_BUFFER(mult, RTL8139State),
3125 VMSTATE_UINT32_ARRAY(TxStatus, RTL8139State, 4),
3126 VMSTATE_UINT32_ARRAY(TxAddr, RTL8139State, 4),
3127
3128 VMSTATE_UINT32(RxBuf, RTL8139State),
3129 VMSTATE_UINT32(RxBufferSize, RTL8139State),
3130 VMSTATE_UINT32(RxBufPtr, RTL8139State),
3131 VMSTATE_UINT32(RxBufAddr, RTL8139State),
3132
3133 VMSTATE_UINT16(IntrStatus, RTL8139State),
3134 VMSTATE_UINT16(IntrMask, RTL8139State),
3135
3136 VMSTATE_UINT32(TxConfig, RTL8139State),
3137 VMSTATE_UINT32(RxConfig, RTL8139State),
3138 VMSTATE_UINT32(RxMissed, RTL8139State),
3139 VMSTATE_UINT16(CSCR, RTL8139State),
3140
3141 VMSTATE_UINT8(Cfg9346, RTL8139State),
3142 VMSTATE_UINT8(Config0, RTL8139State),
3143 VMSTATE_UINT8(Config1, RTL8139State),
3144 VMSTATE_UINT8(Config3, RTL8139State),
3145 VMSTATE_UINT8(Config4, RTL8139State),
3146 VMSTATE_UINT8(Config5, RTL8139State),
3147
3148 VMSTATE_UINT8(clock_enabled, RTL8139State),
3149 VMSTATE_UINT8(bChipCmdState, RTL8139State),
3150
3151 VMSTATE_UINT16(MultiIntr, RTL8139State),
3152
3153 VMSTATE_UINT16(BasicModeCtrl, RTL8139State),
3154 VMSTATE_UINT16(BasicModeStatus, RTL8139State),
3155 VMSTATE_UINT16(NWayAdvert, RTL8139State),
3156 VMSTATE_UINT16(NWayLPAR, RTL8139State),
3157 VMSTATE_UINT16(NWayExpansion, RTL8139State),
3158
3159 VMSTATE_UINT16(CpCmd, RTL8139State),
3160 VMSTATE_UINT8(TxThresh, RTL8139State),
3161
3162 VMSTATE_UNUSED(4),
3163 VMSTATE_MACADDR(conf.macaddr, RTL8139State),
3164 VMSTATE_INT32(rtl8139_mmio_io_addr, RTL8139State),
3165
3166 VMSTATE_UINT32(currTxDesc, RTL8139State),
3167 VMSTATE_UINT32(currCPlusRxDesc, RTL8139State),
3168 VMSTATE_UINT32(currCPlusTxDesc, RTL8139State),
3169 VMSTATE_UINT32(RxRingAddrLO, RTL8139State),
3170 VMSTATE_UINT32(RxRingAddrHI, RTL8139State),
3171
3172 VMSTATE_UINT16_ARRAY(eeprom.contents, RTL8139State, EEPROM_9346_SIZE),
3173 VMSTATE_INT32(eeprom.mode, RTL8139State),
3174 VMSTATE_UINT32(eeprom.tick, RTL8139State),
3175 VMSTATE_UINT8(eeprom.address, RTL8139State),
3176 VMSTATE_UINT16(eeprom.input, RTL8139State),
3177 VMSTATE_UINT16(eeprom.output, RTL8139State),
3178
3179 VMSTATE_UINT8(eeprom.eecs, RTL8139State),
3180 VMSTATE_UINT8(eeprom.eesk, RTL8139State),
3181 VMSTATE_UINT8(eeprom.eedi, RTL8139State),
3182 VMSTATE_UINT8(eeprom.eedo, RTL8139State),
3183
3184 VMSTATE_UINT32(TCTR, RTL8139State),
3185 VMSTATE_UINT32(TimerInt, RTL8139State),
3186 VMSTATE_INT64(TCTR_base, RTL8139State),
3187
3188 VMSTATE_STRUCT(tally_counters, RTL8139State, 0,
3189 vmstate_tally_counters, RTL8139TallyCounters),
3190
3191 VMSTATE_UINT32_V(cplus_enabled, RTL8139State, 4),
3192 VMSTATE_END_OF_LIST()
3193 }
3194};
3195
a41b2ff2
PB		 3196/***********************************************************/
3197/* PCI RTL8139 definitions */
3198
5fafdf24 3199static void rtl8139_mmio_map(PCIDevice *pci_dev, int region_num,
6e355d90 3200 pcibus_t addr, pcibus_t size, int type)
a41b2ff2 3201{
efd6dd45 3202 RTL8139State *s = DO_UPCAST(RTL8139State, dev, pci_dev);
a41b2ff2
PB		 3203
3204 cpu_register_physical_memory(addr + 0, 0x100, s->rtl8139_mmio_io_addr);
3205}
3206
5fafdf24 3207static void rtl8139_ioport_map(PCIDevice *pci_dev, int region_num,
6e355d90 3208 pcibus_t addr, pcibus_t size, int type)
a41b2ff2 3209{
efd6dd45 3210 RTL8139State *s = DO_UPCAST(RTL8139State, dev, pci_dev);
a41b2ff2
PB		 3211
3212 register_ioport_write(addr, 0x100, 1, rtl8139_ioport_writeb, s);
3213 register_ioport_read( addr, 0x100, 1, rtl8139_ioport_readb, s);
3214
3215 register_ioport_write(addr, 0x100, 2, rtl8139_ioport_writew, s);
3216 register_ioport_read( addr, 0x100, 2, rtl8139_ioport_readw, s);
3217
3218 register_ioport_write(addr, 0x100, 4, rtl8139_ioport_writel, s);
3219 register_ioport_read( addr, 0x100, 4, rtl8139_ioport_readl, s);
3220}
3221
d60efc6b 3222static CPUReadMemoryFunc * const rtl8139_mmio_read[3] = {
a41b2ff2
PB		 3223 rtl8139_mmio_readb,
3224 rtl8139_mmio_readw,
3225 rtl8139_mmio_readl,
3226};
3227
d60efc6b 3228static CPUWriteMemoryFunc * const rtl8139_mmio_write[3] = {
a41b2ff2
PB		 3229 rtl8139_mmio_writeb,
3230 rtl8139_mmio_writew,
3231 rtl8139_mmio_writel,
3232};
3233
6cadb320
FB		 3234static inline int64_t rtl8139_get_next_tctr_time(RTL8139State *s, int64_t current_time)
3235{
5fafdf24 3236 int64_t next_time = current_time +
6ee093c9 3237 muldiv64(1, get_ticks_per_sec(), PCI_FREQUENCY);
6cadb320
FB		 3238 if (next_time <= current_time)
3239 next_time = current_time + 1;
3240 return next_time;
3241}
3242
eb38c52c 3243#ifdef RTL8139_ONBOARD_TIMER
6cadb320
FB		 3244static void rtl8139_timer(void *opaque)
3245{
3246 RTL8139State *s = opaque;
3247
3248 int is_timeout = 0;
3249
3250 int64_t curr_time;
3251 uint32_t curr_tick;
3252
3253 if (!s->clock_enabled)
3254 {
3255 DEBUG_PRINT(("RTL8139: >>> timer: clock is not running\n"));
3256 return;
3257 }
3258
3259 curr_time = qemu_get_clock(vm_clock);
3260
6ee093c9
JQ		 3261 curr_tick = muldiv64(curr_time - s->TCTR_base, PCI_FREQUENCY,
3262 get_ticks_per_sec());
6cadb320
FB		 3263
3264 if (s->TimerInt && curr_tick >= s->TimerInt)
3265 {
3266 if (s->TCTR < s->TimerInt || curr_tick < s->TCTR)
3267 {
3268 is_timeout = 1;
3269 }
3270 }
3271
3272 s->TCTR = curr_tick;
3273
3274// DEBUG_PRINT(("RTL8139: >>> timer: tick=%08u\n", s->TCTR));
3275
3276 if (is_timeout)
3277 {
3278 DEBUG_PRINT(("RTL8139: >>> timer: timeout tick=%08u\n", s->TCTR));
3279 s->IntrStatus |= PCSTimeout;
3280 rtl8139_update_irq(s);
3281 }
3282
5fafdf24 3283 qemu_mod_timer(s->timer,
6cadb320
FB		 3284 rtl8139_get_next_tctr_time(s,curr_time));
3285}
3286#endif /* RTL8139_ONBOARD_TIMER */
3287
1673ad51 3288static void rtl8139_cleanup(VLANClientState *nc)
b946a153 3289{
1673ad51 3290 RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque;
b946a153 3291
1673ad51 3292 s->nic = NULL;
254111ec
GH		 3293}
3294
3295static int pci_rtl8139_uninit(PCIDevice *dev)
3296{
3297 RTL8139State *s = DO_UPCAST(RTL8139State, dev, dev);
3298
3299 cpu_unregister_io_memory(s->rtl8139_mmio_io_addr);
b946a153
AL		 3300 if (s->cplus_txbuffer) {
3301 qemu_free(s->cplus_txbuffer);
3302 s->cplus_txbuffer = NULL;
3303 }
b946a153
AL		 3304#ifdef RTL8139_ONBOARD_TIMER
3305 qemu_del_timer(s->timer);
3306 qemu_free_timer(s->timer);
3307#endif
1673ad51 3308 qemu_del_vlan_client(&s->nic->nc);
b946a153
AL		 3309 return 0;
3310}
3311
1673ad51
MM		 3312static NetClientInfo net_rtl8139_info = {
3313 .type = NET_CLIENT_TYPE_NIC,
3314 .size = sizeof(NICState),
3315 .can_receive = rtl8139_can_receive,
3316 .receive = rtl8139_receive,
3317 .cleanup = rtl8139_cleanup,
3318};
3319
81a322d4 3320static int pci_rtl8139_init(PCIDevice *dev)
a41b2ff2 3321{
efd6dd45 3322 RTL8139State * s = DO_UPCAST(RTL8139State, dev, dev);
a41b2ff2 3323 uint8_t *pci_conf;
3b46e624 3324
efd6dd45 3325 pci_conf = s->dev.config;
deb54399
AL		 3326 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_REALTEK);
3327 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_REALTEK_8139);
0b5b3547
MT		 3328 /* TODO: value should be 0 at RST#. */
3329 pci_conf[PCI_COMMAND] = PCI_COMMAND_IO | PCI_COMMAND_MASTER;
3330 pci_conf[PCI_REVISION_ID] = RTL8139_PCI_REVID; /* >=0x20 is for 8139C+ */
173a543b 3331 pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
0b5b3547
MT		 3332 pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL;
3333 /* TODO: value should be 0 at RST# */
3334 pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin 0 */
3335 /* TODO: start of capability list, but no capability
3336 * list bit in status register, and offset 0xdc seems unused. */
3337 pci_conf[PCI_CAPABILITY_LIST] = 0xdc;
a41b2ff2 3338
a41b2ff2
PB		 3339 /* I/O handler for memory-mapped I/O */
3340 s->rtl8139_mmio_io_addr =
0b5b3547 3341 cpu_register_io_memory(rtl8139_mmio_read, rtl8139_mmio_write, s);
a41b2ff2 3342
efd6dd45 3343 pci_register_bar(&s->dev, 0, 0x100,
0392a017 3344 PCI_BASE_ADDRESS_SPACE_IO, rtl8139_ioport_map);
a41b2ff2 3345
efd6dd45 3346 pci_register_bar(&s->dev, 1, 0x100,
0392a017 3347 PCI_BASE_ADDRESS_SPACE_MEMORY, rtl8139_mmio_map);
a41b2ff2 3348
254111ec 3349 qemu_macaddr_default_if_unset(&s->conf.macaddr);
c1699988 3350
1673ad51
MM		 3351 s->nic = qemu_new_nic(&net_rtl8139_info, &s->conf,
3352 dev->qdev.info->name, dev->qdev.id, s);
3353 qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
6cadb320
FB		 3354
3355 s->cplus_txbuffer = NULL;
3356 s->cplus_txbuffer_len = 0;
3357 s->cplus_txbuffer_offset = 0;
3b46e624 3358
eb38c52c 3359#ifdef RTL8139_ONBOARD_TIMER
6cadb320
FB		 3360 s->timer = qemu_new_timer(vm_clock, rtl8139_timer, s);
3361
5fafdf24 3362 qemu_mod_timer(s->timer,
6cadb320
FB		 3363 rtl8139_get_next_tctr_time(s,qemu_get_clock(vm_clock)));
3364#endif /* RTL8139_ONBOARD_TIMER */
81a322d4 3365 return 0;
a41b2ff2 3366}
9d07d757 3367
0aab0d3a 3368static PCIDeviceInfo rtl8139_info = {
f82de8f0
GH		 3369 .qdev.name = "rtl8139",
3370 .qdev.size = sizeof(RTL8139State),
3371 .qdev.reset = rtl8139_reset,
be73cfe2 3372 .qdev.vmsd = &vmstate_rtl8139,
f82de8f0 3373 .init = pci_rtl8139_init,
e3936fa5 3374 .exit = pci_rtl8139_uninit,
8c52c8f3 3375 .romfile = "pxe-rtl8139.bin",
254111ec
GH		 3376 .qdev.props = (Property[]) {
3377 DEFINE_NIC_PROPERTIES(RTL8139State, conf),
3378 DEFINE_PROP_END_OF_LIST(),
3379 }
0aab0d3a
GH		 3380};
3381
9d07d757
PB		 3382static void rtl8139_register_devices(void)
3383{
0aab0d3a 3384 pci_qdev_register(&rtl8139_info);
9d07d757
PB		 3385}
3386
3387device_init(rtl8139_register_devices)
Empty description
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